JPS62117415A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS62117415A
JPS62117415A JP60257142A JP25714285A JPS62117415A JP S62117415 A JPS62117415 A JP S62117415A JP 60257142 A JP60257142 A JP 60257142A JP 25714285 A JP25714285 A JP 25714285A JP S62117415 A JPS62117415 A JP S62117415A
Authority
JP
Japan
Prior art keywords
tr
t1
circuit
impedance
electric potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60257142A
Inventor
Yoshihiro Mabuchi
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP60257142A priority Critical patent/JPS62117415A/en
Publication of JPS62117415A publication Critical patent/JPS62117415A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

Abstract

PURPOSE:To realize a pull-down or pull-up function of a chip input terminal so as to improve the packaging density of a semiconductor integrated circuit, by using the excessive transistor of a master slice substrate in a logic circuit. CONSTITUTION:The transistor T1 of an input buffer circuit 2 is a transistor (Tr) for pulling up a chip input terminal IN and its impedance at the time of conduction is determined by the electric potential of the output terminal 4 of a Tr circuit 1 for control connected with the gate of the Tr T1. All of the Trs T1-Tm of the Tr circuit 1 for control are under conducted conditions and electric potential divided by the impedance of each Tr at the time of conduction can be obtained at each node N1, N2,..., Nm-1, at which the drain and source of each adjacent Trs are connected. Therefore, the electric potential at the chip input terminal IN can be pulled up to a desired value, because the impedance of the Tr T1 can optionally be set by selecting the nodes to be connected with an output terminal 4.
JP60257142A 1985-11-15 1985-11-15 Logic circuit Pending JPS62117415A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60257142A JPS62117415A (en) 1985-11-15 1985-11-15 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60257142A JPS62117415A (en) 1985-11-15 1985-11-15 Logic circuit

Publications (1)

Publication Number Publication Date
JPS62117415A true JPS62117415A (en) 1987-05-28

Family

ID=17302297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60257142A Pending JPS62117415A (en) 1985-11-15 1985-11-15 Logic circuit

Country Status (1)

Country Link
JP (1) JPS62117415A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6342215A (en) * 1986-08-07 1988-02-23 Canon Inc Electronic equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6342215A (en) * 1986-08-07 1988-02-23 Canon Inc Electronic equipment

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