JPH0650816B2 - Gate circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate circuit used in a MOSFET integrated circuit.

(Prior Art) As the density of the MOSFET integrated circuit has been increased, the MOSFETs constituting it have become finer. Along with that, the so-called hot carrier effect has become a problem.
This is because the electric field in the device is strengthened
The reliability of T decreases. In order to suppress this effect, it is sufficient to lower the power supply voltage and weaken the electric field, but it is difficult to execute it for various reasons such as it is difficult to prepare such a special power supply voltage in the device incorporating the integrated circuit. Therefore, a method shown in FIG. 2 has been proposed as a method for suppressing the hot carrier effect in a circuit without lowering the power supply voltage (Nikkei Microdevice, Summer 1985, p. 48).

In FIG. 2, the MOSFET 21 is an N channel,
It is biased so as to be always conductive by the potential of the power supply 24 connected to the gate electrode. MOSFET 22 is N
A channel, whose gate electrode is connected to the input terminal 13, conducts or cuts off by the input applied to the input terminal 13, and the output on the output terminal 14 is a MOSFET.
It changes according to the state of 22. According to this circuit, the voltage between the output terminal 14 and the power supply V _SS is equal to that of the MOSFETs 21 and 2
It is divided by two, and a large voltage is not applied between the source and drain of each of the MOSFETs 21 and 22. Therefore, the electric field in the MOSFET is suppressed low, and the hot carrier effect can be suppressed.

(Problems to be Solved by the Invention) However, the circuit of FIG. 2 has the following practical problems.

First, the load capacitance connected to the output terminal 14 is connected to the MOSF.
When discharging through ET21 and 22, MOSFET2
The operation speed becomes slower than in the case where the output terminal 14 is directly connected to the drain electrode of the MOSFET 22 because there is no 1. Second, when the state of the circuit changes, the MOSFE
The potential that is transiently applied to the electrodes of T21 and T22 depends on the magnitude of the load capacitance connected to the output terminal 14 and the input terminal 13
2 is a complex function of the input waveform applied to, and the circuit of FIG. 2 does not guarantee that the electric field will be kept sufficiently small in any case.

In view of this point, the present invention theoretically guarantees that the hot carrier effect is suppressed without lowering the power supply voltage, the operating speed does not decrease, and the electric field in the MOSFET is sufficiently small in any case. An object is to provide a gate circuit.

(Means for Solving the Problems) Means provided by the present invention for solving the above-mentioned problems are as follows. The source electrode is connected to the first power supply and the gate electrode is connected to the second power supply.
MOSFET of the first conductivity type connected to the power supply of
A second MOSFET of a second conductivity type having a drain electrode connected to the drain electrode of the first MOSFET and a gate electrode connected to a third power source, and a source electrode of the second MOSFET.
Of the MOSFET of the first conductivity type, the gate electrode of which is connected to the input terminal and the drain electrode of which is connected to the output terminal, and the drain electrode of which is connected to the output terminal and the gate electrode of which is A fourth MOSFET of the second conductivity type connected to an input terminal, and a first MOSFET of the first conductivity type having a source electrode connected to the source electrode of the fourth MOSFET and a gate electrode connected to a fourth power supply. 5
And the drain electrode of the fifth MOSF
A second MOSFET of the second conductivity type connected to a drain electrode of ET, a gate electrode thereof connected to a fifth power supply, and a source electrode thereof connected to a sixth power supply; The gate circuit is characterized in that the second conductivity types are mutually opposite conductivity types.

(Example) Next, an Example is given and this invention is demonstrated in more detail.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In this embodiment, MOSFETs 1, 3 and 5 are P-channel devices, and MOSFETs 2, 4 and 6 are N-channel devices. First, from the state in which the potential applied to the input terminal 13 is low level, the MOSFET 3 is conducting and the MOSFET 4 is cut off, the potential of the input terminal 13 changes to a high level, the MOSFET 3 is cut off, and the MOSFET 4 is turned on. Consider the case. At this time, from the output terminal 14 to the MOSF
A current flows through the power supply V _SS through ET4, 5 and 6, and the potential of the output terminal 14 decreases. A constant voltage V ₂ is applied to the gate electrode of the MOSFET 5,
When the threshold voltage of 5 is V _TP , the potential of the connection point 16 is V ₂
When it reaches + V _TP , MOSFET5 cuts off and the connection point 16
Does not _drop below V ₂ + V _TP . Therefore, the potential of the output terminal 14 does not _drop below V ₂ + V _TP . Also,
The gate electrode of the MOSFET 6 is connected to the power source 12 having a constant potential, and therefore the drain current is always constant.
Therefore, in the process of the potential of the output terminal 14 decreasing, the flowing current is constant, which is also the MOSFET.
Regardless of whether or not there is 5.

On the contrary, consider a case where the potential applied to the input terminal 13 changes from the high level to the low level, the MOSFET 3 changes from the cut-off state to the conductive state, and the MOSFET 4 changes from the conductive state to the cut-off state. In this case, power supply V _DD to MO
A current flows through the SFETs 1, 2 and 3 to the output terminal 14, and the potentials of the output terminal 14 and the connection point 15 rise. When the potential of the connection point 15 reaches V ₁ -V _TN , the MOSFET 2 is cut off, and the potential of the connection point 15 and thus the potential of the output terminal 14 rises only to V ₁ -V _TN . However, V ₁ is MOSF
Constant potential applied to the gate electrode of ET2, also V _TN is the threshold voltage of the MOSFET 2. Further, the current flowing through the output terminal 14 at the time of this state switching is constant due to the action of the MOSFET 1 having a constant potential applied to the gate electrode, and this is independent of the presence or absence of the MOSFET 2.

As described above, in the circuit of FIG. 1, the potential of the output terminal 14 rises only to V ₁ -V _TN due to the action of the MOSFET _{2 and} V ₂ + V _TP due to the action of the MOSFET 5.
It can only go down. Therefore, no voltage greater than V _DD − (V ₂ + V _TP ) is applied between the source and drain of the MOSFETs 1, _{2 and 3} . Further, no voltage larger than (V ₁ −V _TN ) −V _SS is applied between the source and drain of the MOSFETs 4, 5 and 6. Therefore, these voltages can be made sufficiently small by appropriately adjusting V ₁ and V ₂ , and M
The hot carrier effect can be suppressed by keeping the electric field in the OSFET sufficiently weak. Also, MOSFETs 1 and 6
By the action, it is possible to prevent the operation speed from being slowed down by the MOSFET 2 and the MOSFET 5.

(Effects of the Invention) As described above, according to the present invention, it is possible to obtain a gate circuit that can suppress the hot carrier effect without lowering the power supply voltage and that does not slow down the operation speed, and use a fine element. It has a great effect in the MOSFET integrated circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 1, 2, 3, 4, 5, 6, 21, 22, 23 ... MOS
FET, 13 ... Input terminal, 14 ... Output terminal.

Claims (1)

[Claims] 1. A first conductivity type first MOS having a source electrode connected to a first power supply and a gate electrode connected to a second power supply.
An FET, a second MOSFET of a second conductivity type in which a drain electrode is connected to the drain electrode of the first MOSFET and a gate electrode is connected to a third power source, and a source electrode is a source electrode of the second MOSFET. And a gate electrode connected to an input terminal and a drain electrode connected to an output terminal, and a third MOSFET of the first conductivity type, a drain electrode connected to the output terminal, and a gate electrode connected to the input terminal. A fourth MOSFET of the second conductivity type; a fifth MOSFET of the first conductivity type, a source electrode of which is connected to a source electrode of the fourth MOSFET and a gate electrode of which is connected to a fourth power supply; The drain electrode is connected to the fifth M
A second MOSFET of the second conductivity type connected to a drain electrode of the OSFET, a gate electrode thereof connected to a fifth power source, and a source electrode thereof connected to a sixth power source;
And the second conductivity type are opposite conductivity types to each other.