JPS5927125B2 - Pulse generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse generation circuit using MOSFETs, particularly complementary MO8FETs.

Digital transition of input signal, i.e. from logic 0 to logic 1
There is a pulse generation circuit that generates a pulse synchronized with each change from logic 1 to logic 0, but such pulse generation circuits utilize the propagation delay time of an inverter.

That is, an input signal is supplied to first inverters in several stages (including 0 stages), and an output signal from the first inverter is supplied to the second inverters in odd-numbered stages.
Supplied to the inverter.

Output signals of the first and second inverters are provided to first and second inputs of a NAND gate and a NOR gate, respectively.

The output of the NAND gate becomes a first pulse via an inverter, and the output of the NOR gate becomes a second pulse having a phase different from the first pulse.

The pulse widths of the first and second pulses are determined by the propagation delay time depending on the number of stages of the second inverter.

In this way, if the pulse width of the output pulse is determined using the propagation delay time of the inverter, if you try to obtain a pulse with a certain long pulse width, it is necessary to increase the number of odd stages of the impark. This has the disadvantage that the number of elements and the area occupied therefor increase.

For example, since the propagation delay time per stage of a normal MOS inverter is about several ns, 9 to 11 stages of inverters are required to obtain a pulse width of several tens of ns.

Accordingly, an object of the present invention is to provide a pulse generating circuit that can generate pulses of arbitrary long pulse widths with a small number of circuit elements.

According to the present invention, there is provided a pulse generating circuit comprising a complementary inverter circuit, a resistive functional element connected in series with the inverter circuit, and a capacitor connected between an input terminal of the inverter circuit and a power source.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a complementary MOS transistor circuit, and FIGS. 2 and 3 show the input/output characteristics and power supply current of the complementary transistor circuit.

When a pulse signal is supplied from the input terminal 11 of the complementary MOS transistor circuit shown in FIG. In the input/output characteristic shown in FIG. 2, the voltage at the output terminal 12 varies from VSS to VDD.
Alternatively, in the region where VDD changes to VSS, a through current flows through both P-channel and N-channel MOS transistors 13 and 14, as shown in FIG. 3.

When the transition region is passed and either transistor 13 or 14 becomes non-conductive, the through current disappears and the output voltage becomes a constant level of either VDD or VSS.

That is, the through current flows only in the transition region, so if this through current is detected by some method, changes in the input signal can be known.

The present invention provides a pulse generation circuit that utilizes this through current.

FIG. 4 shows an embodiment of the present invention. According to this embodiment, the input end 15 is connected to the input end of a complementary inverter circuit 17, that is, the current path is connected in series with each other via a two-stage inverter 16. It is connected to the control electrodes, ie, the gates, of channel and N-channel MOS transistors 18 and 19.

One power supply terminal of the complementary inverter circuit 17 is connected to the power supply VD.
D is connected, and the other power supply terminal is connected to the power supply VSS through the drain and source of the N-channel MO8I-randisk 20.

The gate of the N-channel MOS transistor 20 is connected to the power supply V.
DD, and a connection point between the source of this transistor 20 and the source of the transistor 19 is connected to an output terminal 21.

In addition, the drain of the transistor 20 and the inverter circuit 1
A capacitor 22 is connected between the input terminals of transistors 18 and 19, that is, the gates of transistors 18 and 19.

In the circuit of FIG. 4, the N-channel MO8I-transistor 20 acts as a load resistor for detecting the through current flowing through the complementary transistors 18 and 19.

The capacitor 22 sets the rise time tr and fall time tf of the signal B output from the inverter 16 with respect to the input signal A, as shown in FIG.

A signal C appears at the output 21 with a pulse width corresponding to the time tr and 100 of the signal B.

Further, as the times tr and tf become larger, the through current i becomes wider and flows for a longer time.

of the output signal C. The level is approximately determined by the ratio of conduction resistances of transistors 18, 19 and 20 when they are all conductive.
．． The higher the conduction resistance of the transistor 20 is compared to the conduction resistance of the transistor 19, the closer the level of the output signal C is to VDD.

As described above, according to the present invention, the output signal, that is, the pulse width of the output pulse, can be arbitrarily changed by changing the capacitance of the capacitor 22, so there is no need to use multiple stages of inverters to obtain a long pulse width as in the conventional case. Output pulses with a long pulse width can be obtained with a small number of elements.

In the above embodiment, the complementary MOS transistors are P-type Wel
The circuit shown is composed of one layer, but N
When a complementary MO8t-transistor is constructed by one layer of type Wel, a circuit as shown in FIG. 6 is obtained.

That is, one power supply terminal of the complementary inverter circuit 23 is connected to the power supply VDD via the P-channel MOS transistor 24, and the other power supply terminal is connected to the power supply VSS.

In the above embodiment, an MO8I transistor is used as the load resistor of the complementary impark circuit, but it may be a linear resistor.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of the complementary inverter circuit, Fig. 2 is a diagram showing the input/output characteristic curve of the complementary inverter circuit, Fig. 3 is a curve diagram showing the through current of the complementary inverter circuit, and Fig. 4 is a diagram showing the input/output characteristic curve of the complementary inverter circuit. FIG. 5 is a circuit diagram of a pulse generating circuit according to one embodiment of the invention, FIG. 5 is a time chart of signals in a predetermined portion of FIG. 4, and FIG. 6 is a circuit diagram of a pulse generating circuit according to another embodiment. 15... Input terminal, 16... Two-stage impark, 17... Complementary inverter circuit, 18
...P-channel MOS transistor, 19.
...N-channel MOS transistor, 20...
...N-channel MOS transistor, 21...
...output terminal, 22...capacitor.

Claims (1)

[Claims] 1. A transistor series circuit consisting of complementary transistors whose current paths are connected in series with each other, a resistance function element connected in series between the transistor series circuit and the power supply means, and the transistor series circuit and the resistance function element. an output means connected to a connection point of the complementary transistor, an input means connected to a control electrode of the complementary transistor, and a capacitive element connected between the control electrode and the power supply means.