JPH0736505B2 - Schmitt trigger circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a CMOS logic circuit, and in particular, the hysteresis width can be set in a very wide range, manufacturing variations are small, and even if the hysteresis width is set wide, the original value is ensured. The present invention relates to a Schmitt trigger circuit capable of obtaining the above operation.

[Conventional technology]

Conventionally, a CMOS Schmitt trigger circuit has been constructed as shown in FIG. FIG. 5 shows FIG. 4 at the transistor level. The input signal IN received at the input terminal 55 is received by the CMOS inverter 41 in which the P-channel MOS transistor 51 and the N-channel MOS transistor 53 are connected in series,
The output is inverted by the same CMOS inverter 43, the output is output from the output terminal 57 as the output signal OUT, and the CMOS inverter 42 in which the P-channel MOS transistor 52 and the N-channel MOS transistor 54 are connected in series is connected to the CMOS inverter 41. It was configured to return to the connection point with 43.

[Problems to be solved by the invention]

The operation of the above-described conventional Schmitt trigger circuit will be described with reference to FIG. The inversion voltages V _IH , V _IL and the hysteresis width V _H shown in FIG. 6 are obtained by combining the conductivity (hereinafter, referred to as gm) of the MOS transistors 51, 52, 53 and 54 shown in FIG. 5 with a certain value. Is set.

In the case of this circuit, the following conditions are necessary to obtain the operation as the Schmitt trigger circuit. That is, the gm of each MOS transistor 51, 52, 53 and 54 is changed to gm51, gm52, gm53, respectively.
And gm54, gm51 / gm54> 1 and gm53 / gm52> 1 must be satisfied.

Hysteresis width by increasing gm51 / gm54 or gm53 / gm52
V _H becomes smaller, and conversely, if it approaches “1”, the hysteresis width
V _H becomes large. However, when it becomes "1" or less, it cannot operate as a Schmitt trigger circuit. Therefore, when gm51 / gm54 or gm53 / gm52 is set close to “1” in order to increase the hysteresis width V _H , the above conditions are not satisfied and the device does not operate due to manufacturing variations and the like. Where MOS transistor 5
Since 1 and 52 are P-channel type and MOS transistors 53 and 54 are N-channel type, gm51 / gm54 and gm51
m53 / gm52 is the ratio of the P-channel type MOS transistor and the N-channel type MOS transistor, and is easily affected by manufacturing variations. Therefore, if the hysteresis width V _H is increased, there is a drawback that the manufacturing variation greatly affects the Schmitt trigger circuit, which increases the risk of not operating.

[Means for solving problems]

According to the present invention, a first transistor of one conductivity type, a first resistive element, a second resistive element, and a second transistor of another conductivity type are connected in series between power supply terminals. An input signal is applied to the input electrodes of the first and second transistors, a third transistor of one conductivity type is connected in parallel to the first resistive element, and a third resistive element is connected in parallel to the second resistive element. The fourth transistor of the conductivity type is connected, and the signal at the common connection point of the first resistive element, the second resistive element, the third transistor and the fourth transistor is transmitted via the first inverter. A Schmitt trigger circuit is obtained which outputs as an output signal and feeds this output signal back to each input electrode of the third and fourth transistors via the second inverter.

〔Example〕

 The present invention will now be described in more detail with reference to the drawings.

In the Schmitt trigger circuit of the present invention, as shown in FIG. 1, the gates of the P-channel type MOS transistor 11 and the N-channel type MOS transistor 15 are commonly connected to the input terminal 17, and the drain of the P-channel type MOS transistor 11 is connected. N-channel MOS transistor 13 drain and resistor 12
N-channel MOS transistor 15 connected to one end of
Is connected to the drain of the P-channel MOS transistor 16 and one end of the resistor 14, and the other ends of the resistors 12 and 14 are connected to the source of the N-channel MOS transistor 13 and the source of the P-channel MOS transistor 16, respectively. Connect to the input side of the inverter 20 with CMOS configuration
Of the N-channel type MOS transistor 13 and the P-channel type MOS transistor 16 and the inverter 2
It has a circuit configuration connected to the output side of 3.

Next, the operation of this embodiment will be described with reference to FIG. First, if the input terminal 17 is V _SS potential (negative power supply potential or ground potential), the connection point 18 is V _DD potential (positive power supply potential), the output terminal 19 is V _SS potential, and the connection point 24 is V _DD potential. , The P-channel type MOS transistor 11 is in the ON state, and the N-channel type MOS transistors 13, 15 and P
The channel type MOS transistor 16 is in the OFF state. From this state, increase the potential of the input terminal 17 N channel type
When the threshold voltage V _T of the MOS transistor 15 is reached, the N-channel type MOS transistor 15 enters the ON state and acts to lower the potential of the connection point 18. The potential of connection point 18 is V _DD −V _TH 13
When the voltage drops below (threshold voltage of N-channel type 13), the N-channel type MOS transistor 13 is turned ON, and the potential of the connection point 18 is prevented from decreasing. When the potential of the input terminal 17 is further increased, the potential of the connection point 18 is further reduced, and when the threshold voltage of the inverter 20 is reached, the output terminal 19 changes from the V _SS potential to the V _DD potential, and the connection point 24 Is V _DD
Since the potential changes to the V _SS potential, the N-channel MOS transistor 13 is turned off and the P-channel MOS transistor 1 is turned on, so that the potential at the connection point 18 is lowered and then accelerated. If N channel type MOS transistor 1
Assuming that the gm of 5 is much smaller than that of the other transistors, the potential at the connection point 18 does not easily drop. But input terminal 17
When the potential of the P-channel MOS transistor 11 is turned off when the potential of V _DD − | V _TP | (V _TP : threshold voltage of the P-channel MOS transistor) is reached, the connection point 18
The electric potential of will fall and will invert.

When the potential of the input terminal 17 is changed from the V _DD potential to the V _SS potential, the P-channel MOS transistor and the N-channel MOS transistor described above are reversed, and the same operation is performed.

From the above description, the maximum value of the inversion voltage V _IH shown in FIG. 2 is V _IH
It becomes V _DD − | V _TP |. The minimum value of the inversion voltage V _IL is V _IL
It is understood that it is V _SS + V _TN (V _{T of} V _TN NMOS). And the maximum value of the hysteresis width V _H is V _H V _DD − (V _TN + | V
_TP |).

In addition, N-channel MO for obtaining hysteresis characteristics
S-transistor 13 and P-channel MOS transistor 16
Are N when the potential of the input terminal 17 rises.
The size of the hysteresis is determined by the ratio of the gm of the channel type MOS transistor 13 and the N channel type MOS transistor 15, and when the potential of the input terminal 17 falls, the gm of the P channel type MOS transistor 16 and the P channel type MOS transistor 11 is reduced. The size of the hysteresis varies depending on the ratio, and the hysteresis characteristics are determined by the N-channel type MOS transistor and the P-channel type MOS transistor, regardless of whether the input terminal 17 rises or falls, so that it is less susceptible to manufacturing variations. It has become.

FIG. 3 is an equivalent circuit diagram of another embodiment of the present invention. Third
The circuit shown in the figure is obtained by replacing the resistors 12 and 14 in the embodiment shown in FIG. 1 with a P-channel type MOS transistor 32 and an N-channel type MOS transistor 34, respectively. The gates and sources of the MOS transistors 32 and 34 are all connected in common. The circuit operation and other characteristics of this embodiment are the same as those of the embodiment shown in FIG. 1 and have the same advantages.

〔The invention's effect〕

As described above, by adopting the circuit configuration of the present invention, the hysteresis width can be set in a very wide range, it is less likely to be inoperable due to manufacturing variations, etc., and the Schmitt trigger has a small influence on hysteresis characteristics due to manufacturing variations. A circuit can be constructed.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of an embodiment of the present invention, and FIG.
FIG. 3 is an operation waveform diagram for explaining the operation of the embodiment in FIG.
FIG. 4 is an equivalent circuit diagram of another embodiment of the present invention, FIG. 4 is a block diagram showing a conventional example, FIG. 5 is an equivalent circuit diagram in which the block diagram of FIG. 4 is partially detailed, and FIG. FIG. 7 is an operation waveform diagram for explaining a circuit. 11,16,31,32,36,51,52 …… P-channel MOS transistor, 13,15,33,34,35,53,54 …… N-channel MOS transistor, 20,23,37,38, 41,42,43,58 …… Inverter, 12,14 …… Resistance.

Claims (1)

[Claims] 1. A first transistor of one conductivity type, a first resistive element, a second resistive element, and a second transistor of another conductivity type are connected in series between power supply terminals. An input signal is applied to the input electrodes of the first and second transistors, the third conductive type third transistor is provided in parallel with the first resistive element, and the third conductive type third transistor is provided in parallel with the second resistive element. The one conductivity type fourth transistors are respectively connected in parallel, and a signal at a connection point between the first resistive element and the second resistive element is output through a first inverter and the output Is fed back to the input electrodes of the third and fourth transistors via a second inverter.