JPS60254911A - Hysteresis circuit of complementary mis transistor - Google Patents

Abstract

PURPOSE:To easily set a hysteresis loop with simple constitution by selecting properly values of a resistance connected in parallel to a PMOS transistor (TR) and a resistance connected in parallel to an NMOSTR. CONSTITUTION:When an input signal falls from a high level to a low level, the potential at a point M varies from a low level to a high level with a transfer characteristics Mu which is lower than the transfer characteristic Md at the point M in the low-to-high level transition of the input by a value depending upon the voltage drop across a resistance R1. Then when the input falls to a level low enough to invert the output of an inverter composed of trailing P2 and N2 to a low level after the potential at the point M is received, a PMOSTRP12 turns on to short-circuit the R1 again, and an NMOSTRN12 turns on to make R2 effective instead. At this time, the potential at the point M draws what is called a hysteresis loop with different routes as shown by the transfer characteristic Md at the time of low-to-high level variation of the input signal and the transfer characteristics Mu at the point M at the time of high-to-low level variation of the input signal. Further, values of R1 and R2 are adjusted to easily specify the width of hysteresis.

Description

DETAILED DESCRIPTION OF THE INVENTION (1.) Technical Field of the Invention The present invention relates to a hysteresis circuit provided with hysteresis characteristics using a complementary MIS circuit (hereinafter described as an 0M03 circuit).

(2) Technology background Hysteresis circuit refers to input/output characteristics.

This is a circuit in which the output characteristics take different loops when the input rises and when the input falls. This hysteresis circuit is 1, for example C
Generates clean digital signals without chattering or oscillation when receiving signals that change slowly, such as signals from R time constant circuits, or when receiving signals in a noisy environment. used as a means.

(3) Problems with conventional technology The conventional hysteresis circuit using 0MO3.

P-type MISI-transistor (hereinafter referred to as PMO3) transistor) and N-type MISI-transistor (hereinafter referred to as NM
Since the hysteresis characteristic is generated by changing the dark value of O3) (explained as a transistor), there is a problem in that the hysteresis loop is determined by the shape of the transistor, making it difficult to control the loop. Furthermore, since a launch circuit or the like is required for the output of gates having different dark values, there is a drawback that the number of components increases.

(4) Purpose of the Invention An object of the present invention is to provide a hysteresis circuit using the 0M03 circuit, which has a simple configuration and allows easy setting of a hysteresis loop.

(5) Structure of the invention and the above-mentioned object is that according to the present invention, an input circuit to which an input signal is applied, a first P-type MIS transistor connected to the input circuit and connected in series, and a first N
type M I S ) transistor.

A first impedance element connected in parallel between the source and drain of the first P-type MIS) transistor, and a second impedance element connected in parallel between the source and drain of the first N-type MIS) transistor. an inverter circuit connected to a common drain terminal of the P-type MIS) transistor and the N-type MIS) transistor, and an inverter circuit connected to a common drain terminal of the P-type MIS) transistor and the first N-type MIS) transistor; This is achieved by providing a complementary MISI-type transistor hysteresis circuit characterized by a common feedback connection to the gate terminals of the MISI-type transistors.

(6) Embodiment of the invention FIG. 1 is a circuit diagram of this embodiment, in which the input signal IN is 1
MO3) Transistor P++ and NMOS transistor N+
+, and the source of the PMOS transistor P++ is the power supply V. 0 and the drain is connected to PMO5
I-ransistor Pl? connected to the source. Also, N
The source of the MOS transistor N++ is connected to the power supply v6S, and the drain is connected to the source of the NMo5 transistor N12. And PMO3I - transistor P12
and the drains of the NMOS transistor N12 are commonly connected. Also, 1MO3) transistor P12 and NMO3)
Resistors R1 and R'2 are connected in parallel between the source and drain of the transistor N12, respectively.

Next, the common drain of the 1MO3) transistor P12 and the NMOS transistor Nl2 is connected to the secondary stage PMO3I-
C consisting of transistor P2 and NMO3) transistor N2
Connected to each gate of the MOS inverter, this CMOS
The output terminal OUT of the inverter is commonly feedback-connected to the gates of the aforementioned 1MO3) transistor P12 and NMOS transistor N12.

Next, the operation of the embodiment of the present invention having the above-described configuration will be explained.

When the input is at a low level (5. level).

NMO3) transistor N++ is off and 1MO3
) The transistor p++ is in the on state. Therefore, 1M
O3) Transistor P12 and NMO3) Transistor N12
The common drain terminal M point is at high level (Habo■I). level). Due to the high level of M point, NMO3
) The transistor N2 is on and the pMOS transistor P2 is off. Therefore, the output OUT is at a low level. This output OUT is fed back to P, MOS)
Transistor P l 2. NMOS, ) transistor N12
Since it enters the gate in common, P+2 is turned on.

N12 is in an off state. Therefore, resistor R1 is PMO3
) is short-circuited by the ON state of transistor P12. M
The point is when transistor pH, P+2 is on or N12
is in the off state.

It is almost at the same level as VO(,. Therefore,
When the input is at a low level, the circuit of FIG. 1 can be thought of as an equivalent circuit as shown in FIG.

Next, the case where the input transitions from low level to high level will be described. Threshold voltage of transistor N++ (input is NMOS)
When Vth (referred to as N++) is exceeded, the NMOS transistor N++ changes from the off state to the on state. Then, the input is from vth(N++) to PMO3) Ranjisk P
While the voltage rises to the dark value voltage (referred to as Vth (P++)), PMO3) transistor P++ is also in the on state, so PMO3) transistor P++, PMO3I
- transistor P l 2. Current flows through the path R2, NMOS transistor N11. Since point M is connected to the upper end of resistor R2, due to the voltage drop across R2,
Due to the voltage drop across R2, it has a higher transfer characteristic than the other end of R2, that is, the drain terminal of the NMOS transistor N++. However, the current flowing through the above-mentioned path may be lower than Vth (N++) or Vth (P++).
At higher inputs, N++ and P++ are turned off, respectively, so that N++ becomes almost zero.

Also, at an intermediate input from Vth (N++) to Vth (P++), P+ 1. Since the on-resistance of N+l changes according to the input level, this current value starts to increase from O at vth(N++), reaches its maximum value exactly in the middle, and reaches Vth(N++).
P++) to return to O again. Therefore, when the input changes from low level to high level, the 1M point changes from low level to high level, but the resistance R2
Therefore, the transfer curve Md changes so that it is higher than the transfer curve without the resistor R2 by the voltage drop across the resistor R2.

Then, the potential at point 9M is inverted by the impark circuit consisting of R2 and N2 in the next stage, and PMO3) Ranjisk P l
2. Since the circuit configuration is to drive the common gate of the NMOS transistor N12, when the potential at point M crosses the threshold of this inverter and drops,
The output OUT rises from a low level to a high level as shown by Ou in FIG.

P+2 is turned off and N12 is turned on, R2 is short-circuited, and R1 comes into the current path from P++ to N++ described above. In this way, the output is inverted to a high level (when the input becomes sufficiently high level, the 2M point is the resistance R
1 and is held at a low level by the on-states of NMOS transistors N12 and N++.

The equivalent circuit of FIG. 1 at this time becomes as shown in FIG. 3.

Next, a case will be described in which the input changes from high level to low level from such a state. input signal.

When it falls from a high level and reaches Vth (P++), PMO
S transistor P++ is turned on. After that, up to Vth (N++), the NMOS transistor N
++ is also in the on state, so when the input is between Vth (P++) and Vth (N++).

The PMOS transistor P++ and the NMOS transistor N++ are simultaneously turned on, and current flows through the resistor R1. In this case, the 2M point is the lower end of the resistance R+, that is, NM
Since this is the potential of the drain terminal of the OS transistor N++, the potential at the 1M point changes to be lower than the potential at the upper end of P+ by the voltage drop. In other words, as shown in the voltage transfer characteristic in Figure 4, when the input signal falls from a high level to a low level, the potential at point M is the same as that at point M when the input transitions from low level to high level. Transfer characteristic Md
The transmission characteristic Mu changes from a low level to a high level due to the voltage drop across the resistor R1. Then, in response to the potential at point M, the inverter consisting of R2 and N2 in the subsequent stage is inverted, and when the wedge input becomes low enough to make the output low, P+ is short-circuited again by turning on P+2, and instead R2 is enabled when N+2 is off.

At this time, when P++, P, and ++ are turned on, the M point is stably maintained at a high level. In other words, the potential at the 1M point is
As shown in the transfer characteristic Md when the input signal changes from low level to high level and the transfer characteristic Mu at point M when the input signal changes from high level to low level, it passes through different paths and draws a so-called hysteresis loop. It turns out.

The transfer characteristics shown in FIGS. 4 and 5 will be explained in more detail with reference to the transfer characteristics of 8 and V shown in FIG. 6 and the diagram of the conduction state of each transistor shown in FIG. When the input changes from low level to high level, the potential at point M ■. Let's consider how the output and output change. When the input is at a sufficiently low level.

Since P++ is on and N11 is off, the M point is at a high level and the V voltage is at a low level. That V. l, r are P+2 and N
Because it has been returned to Gate 12.

P+2 is on and N12 is off. The equivalent circuit is shown in FIG. In other words, since P+2 is sufficiently turned on, the short circuit of resistor R1 is removed and the upper end of resistor R2 is at the potential of point M.
8, but since N++ is off and P++ is on, vM is at a high level. (2) Since 8 is at a high level, R2 is off and N2 is on. Therefore, the level of ■ is low. Therefore, when the input is at a sufficiently low level, M
The potential vM at the point is at a high level as shown in the previous point (■) in the transfer characteristic in Figure 4, and at this time, each transistor (P
II, N+ 1. R2, N2. P l 2゜N12)
As shown in the first column of FIG. 7, the states of are (on, off, off, on, on, off), respectively. The input is coming up! 'When the threshold value vth(N++) of J++ is reached, N
+1 will gradually turn on from off. P+
+, on the other hand, goes from deep on to shallow on. meanwhile,
Potential of point M connected to N++ via resistor R2 ■8
begins to descend as shown in ■～■. At this time ■. is R2
The potential will fall in a way that is shifted to a higher location than when it is not present. When ■ is from ■ to ■, (P+ l, N+ l
, R2, N2. PI 2. N+ 2) as shown in the second column of Figure 7 (on, on, off).

on, on, off). The inverter at the next stage operates in response to this ■□ level, so when VM falls below the threshold value Vth (R2) of R2, R2 starts to turn on, as shown in ■. ■While 4 goes further down to ■, Figure 7 3
As shown in the column, R2 turns on and each transistor (
P+ +, N+ +.

P 21 N21 P 121 N+ 2) are respectively (on.

On, on, on, on, off). ■As o descends from ■, R2 gradually turns on deeply, so ■
, will rise from a low level to a high level, as shown in FIG. 5 Ou. The output ■Yu was returned and P
■ Since +2 and N12 are being driven. When becomes less than ■, VC and JT reach vth (N12), N12 turns from off to on, and each transistor CPI1. NIr,P
2°N2. PI 2. The states of N+2) are (on, on, on, on, on, on) as shown in the fourth column of FIG. 7, respectively. And ■. When becomes ■, the output ■ becomes the PMO3 threshold value ■ of transistor P12. o-
Since it exceeds Vth (P l 2), P+ 2 changes from on to off. At this time, each transistor (P+ +, N
+ +, P2. N2. The state of PI 2°N12) is the 7th
As shown in the fifth column of the figure, each (on, on, on,
off, on).

Then, V goes up further, like ■, vth(N2)
If it becomes below, N2 turns off, so V. ,,IT goes high and each transistor (P++.

N+ +, P2. N2. PI 2. The states of N+2) are respectively (ON, ON) as shown in the 6th column of FIG.

on, off, off, on). Then, when the input voltage reaches a sufficiently high level and exceeds Vth (P++), P
Since ll is turned off, each transistor (P++, N++.

P2'l N2. PI 2. N+ 2) are each
(off, on, on, off, off, on), and at this time, N12 is sufficiently on, so the short circuit is removed from resistor R2, and P+2 is sufficiently off, so resistor R1 becomes P+
It is connected between the + drain terminal and point M, and the equivalent circuit of the circuit of FIG. 1 becomes as shown in FIG. 3. In reality, when ■ and N move from a low level to a high level, when vM becomes ■, ■ rises and when it becomes ■, V
. R12 and N12 enter the transition state upon feedback from lJT. And ■. As 0□ rises, R12 transitions from deep on to shallow on and then off to recover R1 from the short circuit state, and conversely, N12 transitions from off to shallow on and then deep on, gradually turning R2 on. It will lead to a short circuit condition. Therefore, the 1M point is in a state where R+ is short-circuited (second
) to the state in which R2 is short-circuited (FIG. 3). Therefore.

■ While V goes from ■ to ■. M shifted upward
It will move from d to Mu, which has shifted downward, but this change is caused by a slight change from Md to Mu, ■8 will fall, so ■, will rise, and in response to this, M will further increase.
This is a phenomenon caused by a positive feedback loop in which the transition to u progresses, so in reality the transition from Md to Mu is completed all at once.

■ also rises to the state of ■ quite steeply at once. Therefore, ■□ in the deformed surface state corresponding to ■ and ■ does not exist, and this is shown by a dashed line in FIG.

Conversely, when 1N falls from a high level to a low level, the circuit of FIG. 1 shifts from the state of FIG. 3 to the state of FIG. 2. At this time ■. will pass through the solid line below 9 where there is a voltage drop across R1 compared to the characteristic shown by the dotted line in FIG. 4 when R1 is not present. ■, 1° begins to fall from a high level to a low level, and when it becomes lower than vth (P++), the pH turns from off to on, and ■8 gradually increases as shown in Figure 4 ■~■~■ However, at this time ■□ is a low M
It will go up through u. At this time, since V is at a high level, R12 is off and N12 is on, so the circuit is as shown in FIG. ■, further rises to Vth (N2), that is, when it reaches ■ in Figure 4, N2
starts to turn on.

■ begins to gradually decline. Then, ■□ further increases, ■□ decreases, and when it reaches ■, R12 begins to change from OFF to ON, and a transition occurs in the exact opposite direction to the change from point ■ to point ■ mentioned above. 1
A positive feedback loop acts so that the impedance on the high potential side decreases and the impedance on the low potential side increases from point M. is M d to M u , i.e. the fourth
The transition from ■ to ■ in the figure has been completed, and the voltage V has gone from the potential corresponding to ■ to a very steep and low level (habo V s s
).

In this way, the output V OUT of the gate changes at different levels in response to the rising and falling edges of the inputs (1) and (N), and a hysteresis characteristic is realized.

This hysteresis characteristic is caused by the two resistors R as mentioned above.
This is generated by inserting resistors 1 and R2 and switching them appropriately depending on the output level to effectively act on the current path caused by simultaneous ON of P++ and N++.Is the potential at point 9M taken from the upper ends of resistors R1 and R2? The transmission characteristics of the drive point of the inverter made up of R2°N2 are shifted in opposite directions by switching whether the input signal is taken from the lower end in response to the transition of the input signal from high level to low level or from low level to high level to high level. This gives a hysteresis characteristic to the response of the entire gate.

From this principle, it is clear that the shift amount of the potential change at point M is P+
It is related to the product of the current value when N1+ and N1+ are simultaneously turned on and the value of R1°R2, and this R+.

It can be seen that the width of hysteresis can be easily defined by adjusting the value of R2.

In this way, the hysteresis loop of the hysteresis circuit of the present invention consists of R1. N
It can be easily changed by appropriately selecting the value of R2 connected in parallel to the Mo5 transistor. Of course P l 2. By adjusting the impedance of N12 when it is off, hysteresis characteristics can be achieved using the same principle even if R1 and R2 are omitted.

In addition, in Fig. 7, ■→■−■ and ■−[phase]→■
Because the transition occurs instantaneously due to positive feedback,■.

■, ■, [phase] does not exist constantly.

(7) Effects of the Invention According to the present invention, a hysteresis circuit can be configured with a small number of elements, and the width of the hysteresis loop can be easily selected depending on the values of the resistors R1 and R2. Also, the input is 0MO3)
Since it is connected to the common gate of the transistors, the input impedance is large and it is easy and advantageous to apply it to a one-time constant circuit.

Furthermore, since it is composed of 0 MO3) transistors, it is possible to reduce power consumption. In addition, due to the action of a positive feedback loop, the second half of the transition speed is fast and high-speed characteristics are excellent.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of the above embodiment when the input signal is at a low level, and Fig. 3 is an equivalent circuit diagram of the above embodiment when the input signal is at a high level. An equivalent circuit diagram, FIG. 4 is a voltage transfer characteristic diagram between the input signal and the M point of the above embodiment, and FIG.
FIG. 6 is a voltage transfer characteristic diagram between point M and point (2) in the above embodiment, and FIG. 7 is a chart showing the conduction state of each transistor in the above embodiment. P+ +, P12. P2...PMO3I- transistor, N+ +, N+ 21 N2... NMOS transistor, R1, R2... resistor. Patent Applicant: Fujitsu Limited Figure 1 Figure 2 Figure 3 V':)'+

Claims (3)

[Claims] (1) An input circuit to which an input signal is applied, and a first P-type MI connected to the input circuit and connected in series.
an SI-transistor and a first N-type MIS transistor;
a first impedance element connected in parallel between the source and drain of the first P-type MIS transistor; and a second impedance element connected in parallel between the source and drain of the first N-type MIS transistor. , said PM
an inverter circuit connected to a common drain terminal of the IS transistor and the N-type MIS transistor; A hysteresis circuit for a complementary MIS transistor, characterized in that the output of the inverter is commonly feedback-connected to the gate terminal of the first P-type MIS transistor and the gate terminal of the first N-type MIS transistor. (2) The input circuit includes a second P-type MIS) transistor whose source is connected to the high-potential power supply side and whose drain is connected to the first P-type MIS) transistor, and whose source is connected to the low-potential power supply side. and the drain is the first N-type MIS)
a second N-type MIS transistor connected to a transistor, and an input signal is commonly connected to the gates of the second P-type MIS transistor and the second N-type MIS transistor. Claim 1:
Complementary MIS) transistor hysteresis circuit described in Section 1. (3) The gate of the inverter is the first P type Mis.
) transistor and the first N-type MIS) A third P-type M whose drains are commonly connected to the output terminal thereof, and which are connected in series between the power supply.
2. The complementary MIS transistor hysteresis circuit according to claim 1, comprising an IS) transistor and a third N-type MIS) transistor.