JPS5911031A - Hysteresis circuit - Google Patents

Abstract

PURPOSE:To constitute a titled circuit with less number of elements, by providing a pair of C-MOSFETs and a variable resistance circuit and obtaining hysteresis characteristics between input and output signals via the control of the variable resistance circuit. CONSTITUTION:An FET18 and an FET block 35 form the 1st C-MOS inverter and FETs 22, 23 form the 2nd C-MOS inverter. When an L level is inputted to an input terminal 15, an output terminal 24 goes to an L level. Then, the source and drain of an FET21 are interrupted, a resistance value of the variable resistance circuit 51 is large and the block 35 is operated by FETs 19, 20. Since the on-resistance of the FET20 is high, the gm of the block 35 is low, and the threshold value of the 1st C-MOS inverter is at a high level to ground. When an H level is inputted to the terminal 15, the terminal 24 goes to an H level, the resistance value of the circuit 51 is small and the gm of the block 35 is high. Thus, the threshold value of the 1st C-MOS inverter is low to ground.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a hysteresis circuit, and particularly to a hysteresis circuit that is configured with (- to 408) and operates with low power consumption.

(Background technology) The hysteresis circuit has two voltages: ■, 1 (threshold potential) when the input signal input to the signal input terminal changes from L' to 'H', and 1 (threshold potential) when the input signal changes from H' to L11. V
□Different from 2 (threshold potential), \'TI?
'Compared to T2, C is higher than ground potential! There are 1" and more that operate as a model.

This hysteresis circuit can be used to prevent chuckling at the input terminal of a digital circuit, an interface circuit for an open digital circuit, a CI + oscillation circuit, etc.
One year after the establishment of semiconductor integrated circuits, 141L was created.
Effective.

The conventional (゛-1\10S structure hysteresis circuit is shown in Fig. 1 as 71<-1-t, and this figure shows t.5.) It is connected to the first and second input terminals of the gates (hereinafter referred to as NANI) (1+1hl-)2, and is also connected to the second input terminal of the third NAND gate 4. lth N A
N I) The output of the gate 2 is connected to the first input of the second N gate 3.
The output terminal of the ANI) gate 3 is connected to the output terminal 5, and is also connected to the first input terminal of the third NANI) gate 4. Also, the output terminal of the 3rd NANI) gate is connected to the 2nd NANI)
It is connected to the second input terminal of the NAND gate.

Figure 2 shows the two-person NA, NI) game used in Figure 1.
-(2,3,/I) shows the internal structure of each σ1-circuit diagram) 1, the first input terminal 6 goes to the first P channel 1
0S1・゛to;1II9 and 10 to the first N channel
8 is connected to the gate of FI No. TIO (・ru. The second input terminal 7 is connected to the gate of the second P channel %I (J S FF',
T8 and the second N-channel 10SF are connected to the gates of C']']l. The source sides of the first and second channels MO8II'']I8,0 are both
It is connected to the first power supply potential input terminal 12, and each drain terminal is connected to the output terminal 1.1 and the first N channel.10S
J・”ET Connected to the 100 drain side.

1st N-channel λ40SF+", 'self () source side is 2nd N-channel M OS l="1', TI
The source side of TI+ is connected to the second F[ source potential input terminal 13.

Explain.

l) When inputting an input signal to both the first and second input terminals 6 and 7.

To P channel 108 FLET 8 and 9 are both O
N (conduction between source and train), 40S to N channel; 'r to, + t together (moon pad (between north train or disconnected) 1''. Yotsu'C1
The output terminal 1 = 1 has the 1st source potential level (“H” level) J+, and the 6°2) 1st input terminal 6 has the 1st potential level (“H” level)
When inputting "," and inputting "L" to the second input terminal 7.

1) 40S to the channel 1゛8 is ON,! l
is 0 'I' L, N channel hl (JS Fl
SI'J"IO is ON, 11 is (-)I・'1・-Z-Z-U.

Therefore, the "H" level should be output to the output terminal 1/l.

3) When "I" is input to the first input terminal 6 and "H" is input to the second input terminal 6.

To P channel 1081・1 bow T8 is 0 mouths, g6
-1ONL, N channel ■\40SF, l T10 is OFF, 1] is ON.

Therefore, the "IH1" level is output to the output terminal 14.
do.

4) When 'H' is input to the first and second input terminals 6 and 7.

12 channel MO8Fl bow T8,9 (monthly pa F and N
blood. 1. The channel MO8I" is ON. Therefore, the "L" level is output to the output terminals I1 and 1.

A NAN gate like this is connected to the NAN case 1 shown in Figure 1.
・If 1 is uniformly used as impark as shown in 2, ■) 40 S 1"ID'l" is 2
Because they are parallel, gl]1 is good (and N channel hIIc)81.
・Because g17 is bad<1g-), ℃・ru. , 20) LIS for N A N 1.1 game 1-3, 4 ■,
, NANI-1-1-2 ■, r is high.

Therefore, when a single signal is input to the input terminal IK in FIG. V of gate 2, (V4.,,
) is 1 (, the person receiving the signal; tt, Z) NA N I
) The quotient 1-td) of the gate 4 is effective from \/, (■, , 7), and the pulse shown in FIG. 3 can be taken out from the output terminal 5.

However, the conventional circuit has the following drawbacks.

1) At the NANl) gate (・1～Sei'1-Lono,
In Figure 1, we need as many elements as 12 -J
-ro (because each gate 4σ requires 3 gates with 4 elements /l
X3=+2).

2) Figure 1 shows the output as S・1 (・Noritsubu flop ゛σ)
From the Q output side (V is pressed, the S signal is pressed) Z
) response signal (("-about 500ns for MOS), a pulse is output to the Q output even if the control flop is not sufficiently centered. (Q output σ) "H"
level or NANI) The output of gate 4 returned to the "L" level before it went to the "L" level.d). ) For this reason, when this circuit was used in a Wanzoda Sotomono Multi or an oscillation circuit, there was a possibility that a reprinting malfunction would occur.

(Benefits of the invention) In order to eliminate the above-mentioned drawbacks, the present invention has a small number of prime numbers, θ) and σ), and there is no possibility of malfunction even when used in an oscillation circuit or an oscillation circuit. The purpose is to provide a hysteresis circuit, and its characteristics are that the input terminal and the gate are commonly connected to the input terminal, and the source and
Complementary characteristic I' of a pair of drain circuits connected in multiple rows
vl OS ) transistor, a variable resistance circuit inserted in series with the north drain circuit, a power source means for supplying current to 1rj column circuits including the source/drain circuit and the variable resistance circuit, and the pair of M (,, ) An output terminal coupled to the connection point of the source-drain circuit of the S l transistor, and means for controlling the variable resistor circuit according to the potential of the output terminal. and the Fi
The hysteresis circuit has a hysteresis characteristic between the input analog signal and the output binary signal through the J variable resistor circuit control.

(Structure and operation of the invention) Hereinafter, embodiments of the invention will be described with reference to the drawings. FIG. 4 shows a first embodiment of the invention, and will be described in detail below. In Fig. 4, the signal input terminal 15 is connected to P
Channel 8・+os t”+v′r+8 and Nchi 4.nne.

4 (18Fl'': connected to the gate of TI9, respectively).

High potential (power supply potential) input terminal 1 (brim, P channel M
Connected to the source of OS F11T18, 22 and the gate of N-channel MO81・"E i' 20,
Low potential (ground telegraph) input terminal 17 is N channel M
OS L' IG i" 2 (1, 21.

2; Connected to 3 sources. To N channel channel 1
081. The drains of T20 and 210 are both connected to the source of +9, 1.1 +; 11
1 yen drain is 1 bit; TI8 train and 1 yen drain
JT22, 2:< is connected to the gate of 1'; T22:3 is connected to the output terminal i'? b+ and 1
・' The gate of ICTRI is red-(b・ro. At this time, 1・'I・;l" Since the power supply potential is manually applied to the gate of 20, is there always continuity between the source and drain? It is assumed that the ON resistance (for example, 2 to 20 Ω) is set large and that it operates as a resistance means to achieve a temperature of ℃.
gll by i' 19+, 20, 21
, controllable oJ, to N channel 10S I PA 1 bow'1
゛Flock;35 again, sea lion゛゛1゛20,21
Then, if there is an upstream ++l variable resistance circuit 51 and -C, then J. 11.1 bow 11J8 and 1.I.)'1゛ block: 35 form the first (゛-8 to +08 Inohata), and 1" I bow T22, 2:3 forms the 42nd
A 1OS inverter is formed to (- of the
It works with ~.

(1) When the "L" level is input to the input terminal 15, the output terminals 2 and 1 are at the "L" level.

The °L level of output terminals 2 and 1 is 141.
Since it is also input to the gate of 21, 1.' ]”,
]"21's source train old ■ or 01゛1゛ (cut off), and the resistance value of the oJ variable resistor circuit 5I is thick (1 = "E go block 35 is 1.l 13711 yen, the type that operates by 20 It has become.

At this time, I・"l・;l' 19 and 20 are connected in series, and the ON resistance of I・"141"20 is high (1・God because of the number 1 (Ω)) T block: gll of 35 is low, 1.T; T+8 and L' gll: i'
Flock: It is composed of 35 (knee MUS innovator ■1 is in a high state with respect to the ground, and it is ℃・ro.

(g) When the ``■1'' level is input to the input terminal A15, the output terminals 2 and 1 become 'f5' level, and the source and train of T2+ are turned on (conducted), 0
j The resistance value of the variable resistance path 51 is small (for example, 1 to I(l
KΩ door pa 1, shore flock 35, do + i ′r +9
．． 20 and 21 form a motionless shape. In this case, since T2C1 and T21 are connected in parallel, the resistance value of the variable resistance circuit 51 becomes small, and FII]T
The block 350g1,1 becomes taller. For this reason 1・']
・;1 of the C-MOS inverter composed of 18 and 1・1 bow'F block 35 is in a low state (near conduction (to 108 VT)) with respect to the ground. Also, b] Although the ON resistance of the variable resistance circuit 51 becomes smaller, the current consumption in the steady state does not increase because 1. (Σ
When the 1-signal shown in the waveform is input to the input terminal 15 in Fig. 4, as described in (1) and (2) above, ■ TLI self-powered waveform (threshold voltage when rising) and ■ Tl
! 1. (threshold 'direct pressure when the input waveform falls) are different, so 1・l・;TI8 and 1・I
i,;Illpro,ri;35 ('
The output waveform of the -MUS inverter is in the 1-H shape shown in Figure 6j), and is composed of 1.' IJ T22 and 23.・1 waveform) is a −4″ hexagonal shape shown in FIG. 6 1・).

FIG. 5 shows a second embodiment of the invention. .

This is done by connecting the T200 cable to the power source potential input terminal 1 (i is connected to the input terminal 15 and θ) in Fig. 4, and the operating state is the same as in the first embodiment. All < I
il, 1.1.:T2 (1"" 11 connected in series with the ijJ variable resistance circuit 511 composed of 1.'Ei'21 connected in parallel with l) 1.111
(1 constructed by l, I 1; 71 + block 3
5, when the FI switch 1121 is turned ON, (J to'to' switches g and □1, and jil
, t,: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 (if the -jC waveform shown in FIG. 6 is input to one point, then FIG. 51).

The waveforms l) and J. in Fig. 6 are generated at point 1.

In these first and second embodiments, ■T)+L is approximately ■I)I)
/2, ■ Use 1- when setting TLII to Vl)I)/2 or higher (when setting hysteresis to Vl)+)/2 or higher).

FIG. 7 shows a third embodiment of the invention.

This is a change from the first embodiment to the P channel side, where 1.N+; Input terminal 2
5 is P channel 1, channel [vl (gate of JS FET28 and gate of N channel MUS II'gate; gate 1 of T29).
A is connected to ~.

The power supply potential input terminal 2G is a P channel M (, JSI,
'T: 'a+, 31, 320 north, and the ground potential input terminal 27 is connected between the N channels O8, ``No. 1 U'' 2!I, 33 north and P channel 4
0 S FE T3 (connected to the gate of l. 1
・Both drains of ゛1shi'II': 311, 3 are 1
．． I E 71 + 4 so 1't; T: 兇;;
U; Connected to gate 3. 1.゛ times I゛: 2゜:
U: 3 train is output terminal: 31 and Yen': T: 3
Connect to Kate No. 1. 1・' l: T: +o gate is input with ground 'tK, so source
The train is always ON, but if you increase the ON resistance (
Take the number 1 (Ω) and use it as a resistance 1-roto-4-stone.

Also, day, ;l1lZ・), '30, '31 1) Chi)・Nnel 1\・IOS Ft; door j
"Is the variable resistance circuit 52 i'i'?" has been completed. Do1・)
T flock: 30 and 1.111: 2 by T2'l
1 le 1 (-10S inverter further 1N +,;
11: U2. ;U;3 causes the second (1- to IOS
The inverter is configured as follows.

(1) When the I level is input to the input terminal 25, the output of the first (-108 inverter) is
] level, the output of the second ('-MOS inverter is at the ``L'' level. The output 1d of the second c-MOS inverter is transmitted to the gate of II''T; 0 between the source, l, and rain of l' 3+
N((JN resistance number 1 (Ω). L: T3+
Since the ON resistance of (for example, J~IC1KΩ) is 1, the resistance of the variable resistance circuit 52 is 1, and 1,1.・I
1'2'l and 1' year old 1' flock: J is made up of 6 (- to .Ichika).

(2) Input the level 'I(') to the input terminal.
The first <J) (, r, -MU S inverter's output 'L' level and the second ('-MOS inverter's output (output terminal) also generates i'II' level. Output terminal's 'L' level. '11 level is transmitted to the other gate, and the voltage between the source and drain of Fl'3+ is 01.'
F-J-ru. Therefore, the resistance value of the variable resistance circuit 52 is large (1.l +,; 11 flocks; 36 is gll
l is low, the first (“- to ~l of the 108 inverter, 1
．． is low (・state) with respect to the clan.

(j), (2,> 46 in any case, N −
Turn on NIOS 2 (when turning on, go to P-1082
8, 3+ (monthly power, conversely N-MOS 29 or 0) When it is idle, go to P- -10828°3tl
, 3+ is turned on (・), so there is no increase in the consumption flow in the steady state.

When the waveform C in Figure 6 is input to point C in Figure 7, 215
1) in Figure 7, I) in Figure 6 for 1), and 4i, -1-7) in Figure 6.

gJj, Figure 8 shows an example of the first embodiment of this invention.
).

This Jl is 1' of Silk 7 diagram.G: Graph the gate of T3++ 1'? lbif)n.

Input terminal A is connected to 27 (and is connected to input terminal 25, B). The operating state is the same as the third embodiment,
1・1・;T3(l and 100 columns connected. l・1 and T3
The configuration was destroyed by RI 111 K1'' (anti-circuit 52 and 5
J formed by 1.1.IT28 connected to 2 and inner row
1・1・c′1゛ Block: 36 ni Oha te 1・1
ze: By turning on i'3+, (by switching gll by 1. , 31
v of the first C-10S inverter configured by
This changes l. Figure 6 C at point C in Figure 8
When inputting the e-type, Fig. 8 1), PIl at 16 points,
56 Figure 1), a 1.1 waveform is generated"-4). In the 13th and 4th embodiments, TLII is approximately VDI) /
2. Used when setting TI(L\'I)l) to less than /2 (when hysteresis is set to vI3D/2 or less).

FIG. 9 shows a fifth embodiment of the present invention, which is a combination of the first and third embodiments.

Input end f: U7 is l-' f-tunnel channel I
'tl O S t'l=; Connected to the gate of T42 ℃・a), , 'JJ';. 61 potential input terminal 38
is 11chi 4・ne, 1 and M2S yen, 7+11・10,
Old, small] source and N-chi V channel to I (JSl
・I t,]Ill・1;39 is connected to the gate of the clan l potential input terminal ・;39 is the N channel [)81・
It is connected to the No.1 T・1, U,・+5, /I′7σ) source and the gate of No.1・1・;T・10. FI゛汀・10、Formerly 0）Drain is 1・"I!;i' l
In the source of I l, also 1・'lI; T43,・
The train of 11j is connected to the source of 1・'ET/12 (・a).

1. 1st morning old, 12th train is the next stage F D
TJ], connected to the gate of 47, J・”E i”
/I+), 47 train is output terminal・18,1・”
l> 1” old, connected to the gate of 15.

The gate of 1・1・;T=I(J has a ground potential, and the gate of 1・+l,; Therefore, 1・1・: T.ltl, /13θ)
The connection between the source and drain is turned ON, but the ON resistance is made thick (for example, 2 to 20 1 < !i), and it operates as a resistance means. Tlt
l , II , l 1 by 1'chi tunnel tuk 19, I
; 3 Ka・, To' l Bow T, 12 disorder + 15, N channel 8 10 SF Tonorock 50, 1・I・; T
71:3, /15 by i. iJ variable low resistance circuit 51
KALI'I'

(1) Input terminal: (7's level is manually operated A1)
5(jK yo"J+flfl friend g, l l, 7, the output of the IOS inverter is 'H' level to the first (°-),
1.1.Use (small).

・The second sign 1 constituted by 17 - [\□I (J
The output (output terminal) of the S input becomes the "L" level.The "L" level of the output terminal is 1. Turn on the T old,
l・゛to]T, 15 is stirred (N゛'l・゛. Therefore, "J(resistance II) of variable resistance circuit 5; 3 becomes small, and 1
-1 light block, one gl, 1 is good, the resistance value of the i-+1 variable resistance circuit 54 becomes large, 1·l I,: T
gll, of block 50 is lower and goes to the first C-10
The threshold voltage of the 8 inno(meter) is high (with respect to ground).

(2) When input terminal 37K is set to "H" level manually, the output voltage of the first (°--108 inverter) is
I level, 24-52 (knee hp+(>S) The output of the inverter (output terminal A) becomes the "I+'" level. If the 'II' level of the output terminal is 1.1 1+ Ill, the ()
Turn on 1・1・゛, 1・゛1 bow 111, +r, l
Gome 1・TI,; Ttl page.

The gll+ of the circle is low, and the I part 1 square block 500g,
1 is high (because VT is low with respect to ground). Therefore, if the waveform is input manually to the input terminal in Figure 9; output)
, 1.] point (Mushi 2 innovator output, Fig. 6 1),
1.; The waveform is the same as the cow.

・41, I()1 is the sixth embodiment of this invention).

This connects the gate of 1・'+4 1'・1(-) in Figure 0 to the ground potential input terminal: 7'. c <Input terminal; Connect to 37 and connect to 7, 1.1.:T43's case I.
is connected to the power supply potential input terminal: (input terminal; 37 instead of 8.The operating state is the same as the fifth embodiment, and is connected in parallel with 1.1.)]゛.1(). 1゛”
Variable resistance circuit 5 configured by I゛; i'old: (
, 53 connected in series with 1.I,; 71+ block 11).Furthermore, 1.+ 1.
: Variable resistance circuit composed of rIs・15! 'i
4 + 5・1 and series connected l゛” t: i”=
+2 and 06° C. ``C hysteresis or I'' lever leaks into the I part 1. -) Mari, 1 mill, lltl old θ) ON, 0 1'l', 1
・1st Ill. ,,,5's 01・゛to', ON makes gl of the valley block, , cut name, e, also, I pa]・)'1
゛Old, 12 sources 11 rivers? By changing the l light f) ring, 1・'I=; i” block・circle,
It is composed of 50 (by changing the ~' construction of 108 impark to -).

In Figure 1(), the waveform in Figure 6 is manually entered at one point (input terminal: U7),
Figure 11, I: The waveform is original. , these fifth and sixth embodiments are ~"I, Ll+ ~'Ill) / 2
-, "TIIL wovIl+) / 2 D), t(
Hypsis VIl+) / 20 sides;

The present invention can be manufactured with 6 elements or 8 elements, and when the output waveform is generated, the hysteresis is 1°C.
Therefore, even if it is used in an oscillation circuit or a one-shot mono multi circuit as in the past, there will be no malfunction. It is possible to use it].

[Brief explanation of the drawing]

Figure 1 is a conventional hysteresis circuit, Figure 2 is a circuit diagram of the (-to 408 NANI) gate used in Figure 1;
Figure 3 is a waveform diagram used in Figure 1, and Figure 4 is the waveform diagram used in Figure 1.
Fig. 5 is a circuit diagram showing a second embodiment of the present invention, Fig. 6 is a waveform diagram of each part, and Fig. 7 is a circuit diagram showing a thirteenth embodiment of the present invention. Figure 8 is a circuit diagram showing the eleventh embodiment of the present invention, Figure 9) is a circuit diagram showing the fifth embodiment of the present invention, and Figure 10 is a circuit diagram showing the fifth embodiment of the present invention. Sixth invention
FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1', +, 2. '3, :37...input terminal,
211, :(,l,-18・output end i,1)i,
22, 28, 3tl, 3+, II0. old, old, 40・
...12 channels 8 IO8+・"t;l", yen, 2 (1, 21, 2! l, : 33, 42. / 1: 3.
II5.・17... N chi tunnel to II8 t”l bow T. Ifi, 26.38・Power supply potential input terminal, 17,
'77, :39...Ground potential input terminal, 3
'i + 50...to N channel = I OS, 1
”L Bow'1゛)゛Lock, :36, II9...
J] Channel OS J-II, Tf. 7ri,'
,) I, 52, 53, 54...variable resistance circuit. Figure 1 Figure 2 Figure 3 Figure 1: Figure 4 Figure 5 Figure 6 250°

Claims (1)

[Claims] An input terminal, a gate commonly connected to the input terminal, and a source train circuit connected in the inner column. The inserted variable resistance circuit and the north
A kite connected to the train circuit and the iiJ variable resistance circuit series circuit.
the power supply means connected to the connection point of the north train circuit of the one MO8l transistor; -J-filter means I11
-1 A 41-character hysteresis circuit that provides a hysteresis characteristic between an input analog signal and an output 2-signal through the control of the above-mentioned 6'' variable resistance circuit.