KR960003963B1 - Driving integration circuit for lcd - Google Patents

Abstract

No content.

Description

Integrated circuit for driving liquid crystal display

1 is a block diagram showing an integrated circuit for driving a liquid crystal display according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing one sampling circuit of the sampling circuit group of FIG.

3 is a waveform diagram showing an example of operation of the sampling circuit group of FIG.

4 is an input / output characteristic diagram for explaining the input voltage range of the sample hold circuit during the second step.

5 is an input / output characteristic diagram for explaining the operating voltage range of the voltage follower circuit during the second stage.

6 is an input / output characteristic diagram for explaining an input voltage range and an operating voltage range of the sampling circuit of FIG.

7 is a block diagram showing a modification of the sampling circuit group of FIG.

FIG. 8 is a circuit diagram showing an example in which one sampling circuit of the sampling circuit group of FIG. 7 is taken out. FIG.

9 is a waveform diagram showing an operation example of the sampling circuit group of FIG.

FIG. 10 is a plan view showing an example of use of an integrated circuit for driving a liquid crystal display having a sampling circuit group in the middle of FIG.

Fig. 11 is a block diagram showing an integrated circuit for driving a liquid crystal display according to a second embodiment of the present invention.

FIG. 12 is a circuit diagram showing one sampling circuit of the sampling circuit group of FIG.

13 is a waveform diagram showing an operation example of the sampling circuit group of FIG.

14 is a block diagram showing a modification of the sampling circuit group of FIG.

FIG. 15 is a circuit diagram showing an example in which one sampling circuit of the sampling circuit group of FIG. 14 is taken out. FIG.

16 is a block diagram showing an example of a conventional liquid crystal display driving integrated circuit.

17 is a circuit diagram showing an example of a sampling circuit during the sixteenth embodiment.

18 is a waveform diagram showing an operation example of a sampling circuit during the sixteenth embodiment.

19 is a circuit diagram showing another example of the sampling circuit during the sixteenth embodiment.

* Explanation of symbols for main parts of the drawings

1a... , 1b... : Integrated Circuit for Driving Liquid Crystal Display 2: Liquid Crystal Display Panel

3: liquid crystal display 4a... , 4b... : Wiring group

10a-10n, 30a-30n, 40a-40n: sampling circuit

11, 11a-11n, 31,31a-31n: control circuit

12, 12a-12n: sample hold circuit 13, 13a-13n: voltage follower circuit

15, 15a-15n: Output terminals 21, 22: Clock, Inverter

23, 24: inverter circuit 25: analog switch circuit

26: Hold capacity 251, 271, 272, 274: P-channel transistor

252, 273, 275: N-channel transistor 300: address counter

311: address decoder

42, 42a-42n: first digital data sample hold circuit

43, 43a-43n: digital analog conversion circuit 45: digital processing circuit

Vcc1: first power supply voltage Vss: ground potential

Vcc2: Second supply voltage VI: Analog signal voltage

VL: Analog Voltage DO-D3: Digital Data Signal

TO-T3: digital signal ФS, S: first sampling signal

ФL, L: second sampling signal

ФDA, DA: third sampling signal

DS0-DS3, DL0-DL3, VH: Sample Hold Voltage

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a liquid crystal display driving integrated circuit for driving display of an active, matrix type liquid crystal display device, and more particularly, to a sampling circuit for sampling a liquid crystal display signal and outputting a display driving signal.

FIG. 16 shows a sampling circuit group provided in a liquid crystal display driving integrated circuit for driving a liquid crystal display panel for driving a conventional active, matrix type liquid crystal display panel.

In Fig. 16, reference numerals 70a-70n are a plurality of sampling circuits in parallel, reference numerals 71a-71n are control circuits, reference numerals 72a-72b are voltage conversion circuits, and reference numerals 73a-73n. Is a sample hold circuit, reference numerals 74a-74n are voltage follower circuits, and reference numerals 77a-77n are output terminals. The analog signal voltage VI (for example, an image signal) is commonly input to each of the sample hold circuits 73a to 73n. Each control circuit 71a-71n is cascaded to form a shift register as a whole.

FIG. 17 shows a sampling circuit of one sampling circuit of the sampling circuit group of FIG.

In FIG. 17, reference numeral 71 denotes a control circuit for generating a predetermined control signal, reference numeral 72 denotes a voltage conversion circuit for voltage-converting the control signal to generate a sampling signal, and reference numeral 73 denotes an analog A sampling and holding circuit for sampling and holding the signal voltage VI based on the sampling signal, and reference numeral 74 denotes a voltage follower circuit for impedance-converting and outputting the sampled and held voltage.

A power supply voltage Vcc1 is supplied as an operating power supply of the control circuit 71, and a power supply voltage Vcc2 (>) as an operating power supply of the voltage conversion circuit 72, the sample hold circuit 73, and the voltage follower circuit 74. Vcc1) is supplied in common.

18 is a waveform diagram showing an example of the operation of the sampling circuit group of FIG.

When the sampling signal is input to the first stage control circuit 71a and is transmitted by the transmission clock signal?, The outputs 75a-75n of the control circuits 71a-71n in turn become high level, and the voltage conversion circuit 72a The output signal (each complementary sampling signal) 76a-76n of -72n goes high level in turn, and the sample hold circuits 73a-73n sample hold the analog signal voltage VI in turn. The output of each voltage follower circuit 74a-74n is output as a liquid crystal display drive signal via the output terminals 77a-77n.

By the way, in the sampling circuit shown in FIG. 17, the voltage conversion circuit 72 is susceptible to the influence of the threshold value, the temperature, the wiring load, etc. of the MOS transistor being used, and the waveform of the sampling signal (signal delay, rise time, fall). It is difficult to set the time accurately).

When the waveform of the sampling signal is not set correctly in this manner, in the sampling circuit group of FIG. 16, a malfunction occurs in which a period in which two sampling circuits simultaneously sample occurs.

In other words, the sampling signal in each sampling circuit is partially overlapped, and a period ta in which sampling starts in the sampling circuit 70b in the next stage occurs before the sampling ends in the sampling circuit 70a in one stage. Throw it away. Therefore, charges sampled and held by the sampling circuit 70a of one stage are mixed into the sampling circuit 70b of the next stage, and an error occurs in the sampling data.

FIG. 19 shows a modification of the sampling circuit of FIG. 17. FIG.

In this sampling circuit, reference numeral 101 denotes a control circuit for generating a sampling signal, reference numeral 102 denotes a sample hold circuit for sample-holding an analog signal voltage VI based on the sampling signal, and reference numeral 103. ) Is a voltage follower circuit which outputs an impedance-converted voltage by holding the sample held voltage. The power supply voltage Vcc is commonly supplied as an operating power source for the control circuit 101, the sample hold circuit 102, and the voltage follower circuit 103.

In the sample hold circuit of FIG. 19, since the output signal of the control circuit 101 is directly input to the sample hold circuit 102 as the sampling signal, it is easy to accurately set the waveform of the sampling signal.

Therefore, in the liquid crystal display driving integrated circuit in which many such sampling circuits are provided in parallel, a period in which two sampling circuits sample at the same time does not occur, so that an error does not occur in the sampling data.

However, in the sampling circuit of FIG. 19, since the operating voltage common to the voltage follower circuit 103 is supplied to the control circuit 101 and the sample hold circuit 102, the control circuit 101 and the sample hold circuit 102 are controlled. It is necessary to design a pattern to the circuit pattern corresponding to a high voltage, and there exists a problem that the area of the mask pattern for circuit pattern formation enlarges.

In order to drive a large active, matrix type liquid crystal display panel, it is necessary to perform each sampling operation of the sampling circuit group at a high speed, but if the control circuit 101 is high voltage, the power consumption due to the high speed is greatly increased. There is.

By the way, in the conventional liquid crystal display driving integrated circuit, the drive signal output is required as a voltage range of about 10 V, and thus, as the operating power supply voltage of the voltage follower circuit 74 of the seventeenth way or the voltage follower circuit 103 of the 19th way. I needed about 13V.

Moreover, the number of sampling circuits required by the integrated circuit for driving the conventional small active and mattress type liquid crystal display panel is small, and the sampling rate has no problem even at a low speed.

For this reason, in the conventional liquid crystal display driving integrated circuit, the sampling circuit shown in FIG. 17 or 19 can be used without any problem.

However, recent advances in the technical aspects and driving methods of the active and matrix liquid crystal display panels have allowed the voltage range of the drive signals to be about 4.5V.

Therefore, it is desired to realize a sampling circuit optimized to have an input voltage range of about 4.5V so as to output a drive signal having such a voltage range.

Also, in a field different from the integrated circuit for driving a liquid crystal display, in the case of cascading an integrated circuit for a sample hold, an integrated circuit for a buffer amplification, and an integrated circuit for an analog digital conversion, an operation power supply and amplification of the integrated circuit for a sample hold are amplified. A technique for setting along the operating power supply of the integrated circuit is disclosed in DATEL / INTERSIL ENGINEERING PRODUCT HANDBOOK, 1979, pages 200 to 201, published by INTERSIL (USA). However, even if this technique is used as it is in an integrated circuit for driving a liquid crystal display, the above demands are not realized.

As described above, in the conventional liquid crystal display driving integrated circuit, it is difficult to accurately set the waveform of the sampling signal, thereby causing a malfunction in which two sampling circuits simultaneously sample. Alternatively, it is necessary to design the pattern of the control circuit as a high voltage-responsive circuit pattern, which causes a problem that the area of the mask pattern is enlarged and power consumption is greatly increased due to the high speed.

Moreover, the realization of the liquid crystal display drive integrated circuit optimized for the liquid crystal display device whose voltage range of a drive signal is about 4.5V is desired.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is easy to accurately set the waveform of the sampling signal, and can prevent the malfunction of sampling by two sampling circuits at the same time, so that the pattern of the control circuit can be designed as a low voltage corresponding circuit pattern. The liquid crystal display can prevent the mask pattern from being enlarged in size and at the same time suppress the increase in power consumption due to the high speed, and can be optimized for the case where the voltage range of the drive signal is about 4.5V, if necessary. It is an object to provide a driving integrated circuit.

The integrated circuit for driving a liquid crystal display of the present invention includes a plurality of control circuits each having a first power supply voltage Vcc1 supplied as an operating power source and generating a sampling signal, respectively, and corresponding to the plurality of control circuits, respectively. A plurality of sample-hold circuits for supplying a power supply voltage Vcc1 as an operating power source and for analog-holding the analog signal voltage by a sampling signal correspondingly supplied from the plurality of control circuits by inputting an analog signal voltage in common; The second power supply voltage Vcc2, which is provided corresponding to the plurality of sample hold circuits and is respectively higher than the first power supply voltage Vcc1, is supplied as an operating power source and the sample hold voltage correspondingly output by the plurality of sample hold circuits is impedance. A plurality of voltage follower circuits which are converted and output, and the plurality of voltage follower circuits The installation and respective output voltages of the plurality of voltage follower circuits in response characterized in that it includes a plurality of output terminals for outputting to an external device as a liquid crystal display drive.

In addition, each of the liquid crystal display driving integrated circuits of the present invention is provided with a plurality of control circuits each of which is supplied with a first power supply voltage Vcc1 as an operating power source to generate a sampling signal, and correspondingly to the plurality of control circuits, respectively. A plurality of digital data sample hold circuits for supplying a first power supply voltage Vcc1 as an operating power source to sample and hold the digital data signal by a sampling signal correspondingly supplied from the plurality of control circuits by inputting the digital data signal in common; And digitally analog the sample hold voltages provided corresponding to the plurality of digital data sample fold circuits, respectively, to which the first power supply voltage Vcc1 is supplied as an operating power supply and correspondingly supplied from the plurality of digital data sample hold circuits. A plurality of digital analog conversion circuits to convert, and a plurality of these A second power supply voltage Vcc2 provided corresponding to the digital and analog conversion circuits and higher than the first power supply voltage Vcc1, respectively, is supplied as an operating power supply, and the analog voltages correspondingly output by the plurality of digital-analog conversion circuits are outputted. A plurality of voltage follower circuits for outputting an impedance conversion and a plurality of output terminals provided corresponding to the plurality of voltage follower circuits for outputting the respective output voltages of the plurality of voltage follower circuits to the liquid crystal display drive for output. It is characterized by including.

Since the output signal of the control circuit is directly input to the sample hold circuit as the sampling signal, it is easy to accurately set the waveform of the sampling signal. Therefore, a period in which the two sampling circuits sample at the same time does not occur, and no error occurs in the sampling data.

In addition, since the operating voltage lower than that of the voltage follower circuit is supplied to the control circuit and the sample hold circuit, it is not necessary to design the pattern of the control circuit and the sample hold circuit as the high voltage corresponding circuit pattern, thereby making it possible to avoid the enlargement of the mask pattern.

In addition, since the control circuit and the sampling and holding circuits can be designed for low voltage, an increase in power consumption due to the high speed is suppressed when the sampling of the sampling circuit needs to be made at a high speed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 shows a sampling circuit group provided in an integrated circuit for driving a liquid crystal display according to the first embodiment of the present invention.

Here, reference numerals 10a-10n are a plurality of sampling circuits in parallel, reference numerals 11a-11n are control circuits, reference numerals 12a-12n are sample hold circuits, and reference numerals 13a-13n are voltages. The follower circuit, reference numerals 15a-15n, are output terminals. The analog signal voltage VI (for example, an image signal) is input in common to the sample hold circuits 12a-12n of the respective sampling circuits. The control circuits 11a-11n of the respective sampling circuits are cascaded to form shift registers as a whole.

2 shows a sampling circuit of one sampling circuit of the sampling circuit group of FIG.

In Fig. 2, reference numeral 11 denotes a control circuit for generating a sampling signal, reference numeral 12 denotes a sample hold circuit for sample-holding the analog signal voltage VI by the sampling signal, and reference numeral 13 denotes Voltage follower circuit 15, which outputs the sample-held voltage by impedance conversion, is an output terminal. The first power supply voltage Vcc1 and the ground potential Vss are commonly connected as the operating power supply of the control circuit 11 and the sample hold circuit 12, and the first voltage voltage as the operating power supply of the voltage follower circuit 13. The second power supply voltage Vcc2 higher than Vcc1 and the ground potential Vss are supplied.

The control circuit 11 is complementary to the transmission clock signal? The shift register consisting of the two-stage clock inverters 21 and 22 controlled by the < RTI ID = 0.0 > and / or < / RTI > It consists of inverter circuits 23 and 24 that output S and ФS.

The sample hold circuit 12 is for holding connected between the analog switch circuit 25 to which the analog signal voltage VI is input in one stage, and the other end of the analog switch circuit 25 and the ground potential Vss. Dose 26. The analog switch circuit 25 includes an insulated gate type (MOS type) P channel transistor 251 having a substrate connected to a power supply voltage Vcc1 and an N channel transistor 252 having a substrate connected to a ground power supply Vss. Sampling signals connected in parallel and complementary to each gate ( S and ФS) are input.

The voltage follower circuit 13 includes a P-channel transistor 271 for a current source whose source and substrate are connected to a power supply voltage Vcc2 and a bias voltage Vb is supplied to a gate, and a drain of the P-channel transistor 271. An input P-channel transistor 272 to which a source is connected, a substrate is connected to a power supply voltage Vcc2, and a sample-hold voltage is input to the gate by the sample-hold circuit 12, and the P-channel transistor 272 A source is connected to the N-channel transistor 273 connected to the drain and the ground potential Vss, and a drain of the P-channel transistor 271 for the current source, the substrate is connected to the power supply voltage Vcc2, and the gate and the source are output. An output P-channel transistor 274 connected to the terminal 15 and a drain and a source are connected between the drain and the ground potential Vss of the P-channel transistor 274, and the drain and the gate are connected to each other. To ground potential (Vss) Inherited comprises a N-channel transistor 275.

Incidentally, the transistor used in the voltage follower circuit 13 is not limited to the MOS type except for the input gate, and a bipolar type may be used.

FIG. 3 is a waveform diagram showing an example of operation in the sampling circuit group of FIG.

The sampling signal is inputted to the control circuit 11a of the first stage so that the transmission clock signal ( And (F), the output signals 14a-14n (complementary sampling signals of the control circuits 11a-11n, respectively) And [phi]] in turn become the high level, and the sample circuits 12a-12n sample hold the analog signal voltage VI in sequence. The outputs of the voltage follower circuits 13a-13n of each sampling circuit are output as display drive signals of the liquid crystal display panel via the output terminals 15a-15n.

4 is an input / output characteristic diagram for explaining an input voltage range of the sample hold circuit 12.

5 is an input / output characteristic diagram for explaining an operating voltage range of the voltage follower circuit 13.

6 is an input / output characteristic diagram for explaining an input voltage range and an operating voltage range of the sampling circuit of FIG.

As described above, in the sampling circuit of FIG. 2, since the output signal of the control circuit 11 is directly input to the sample hold circuit 12 as the sampling signal, it is easy to accurately set the waveform of the sampling signal. Therefore, in the sampling circuit group of FIG. 1, a period in which two sampling circuits sample at the same time does not occur, and an error does not occur in the sampling data.

In addition, since the operating voltage lower than the voltage follower 13 is supplied to the control circuit 11 and the sample hold circuit 12, the pattern of the control circuit 11 and the sample hold circuit 12 can be designed as a high voltage corresponding circuit pattern. Since there is no need, the area of a mask pattern can be avoided to enlarge.

In addition, since the control circuit 11 and the sample hold circuit 12 can be designed in a low voltage correspondence, when the sampling of the sampling circuit needs to be made high, the increase in power consumption caused by the high speed is suppressed.

In addition, the input voltage range of the sample hold circuit 12 can operate in the range of the power supply voltage Vcc1 of FIG. 1, as shown in FIG. As shown in FIG. 5, the operating voltage range of the voltage follower circuit 13 is about 0.5V smaller on the lower limit side than about the range of the second power supply voltage Vcc2, and about 1.2V smaller on the upper limit side, about 1.7V in total. small. Combining these two characteristics, as shown in Fig. 6, the lower limit of the input voltage range is determined by the lower limit of the operating voltage range of the voltage follower circuit 13, and the upper limit of the input voltage range is the sample hold circuit 12. Is determined from the power supply voltage Vcc1.

Therefore, in order to optimize the output of the drive signal having a voltage range of about 4.5V, in other words, in order to guarantee the input voltage range 4.5V operation, the power supply voltage Vcc1 of the sample hold circuit 12 is 5V or less (for example, 5V), and the power voltage Vcc2 of the voltage follower circuit 13 is selected so that the operating voltage range of the voltage follower circuit 13 has a predetermined linear region (1.2V or more higher than the power supply voltage Vcc1). . In this example, 6.2V (= 5V + 1.2V) may be defined and the input voltage may be defined as 0-5V.

7 shows a modification of the sampling circuit group of FIG.

This sampling circuit group divides the clock signal? As compared with the sampling circuit group of FIG. 1 and complements the address signal group [(A0 and ), (A1 and ), (A2 and ), (A3 and ), And the control circuits 31a to 31n of the sample hold circuits 30a to 30n are different, and otherwise, the same reference numerals are used.

As shown in FIG. 8, each of the control circuits 31a to 31n is supplied with an address signal having different combinations from the address counter 300, and decodes the address decoder 311 to generate the sampling signal. The waveform decoded by the address decoder 311 is subjected to waveform shaping to obtain a complementary sampling signal ( Inverter circuits 312 and 313 for outputting S and ФS.

FIG. 9 is a waveform diagram showing an example of operation in the sampling circuit group of FIG.

Each of the control circuits 31a-31n is provided with sampling signals 34a-34n (complementary sampling signals respectively) when the corresponding address signal inputs are all at " H " level. S and ФS)]. The sample hold circuits 12a-12n respectively correspondingly hold the analog signal voltage VI by the sampling signals 34a-34n. The voltage follower circuits 13a-13n respectively correspond to the impedance voltages of the output voltages of the sample hold circuits 12a-12n and output them.

According to the sampling circuit group shown in FIG. 7, the switching control is performed such that the output order of the sampling signals 34a to 34n is reversed or in reverse order by controlling whether the address counter 300 is counted up or counted down. The switching control can be performed such that the sample operation order of the circuits 12a-12n is reversed or in reverse order.

FIG. 10 shows an example of use of an integrated circuit for driving a liquid crystal display having the sampling circuit group of FIG.

In Fig. 10, reference numerals 1a, 1b, ... are integrated circuits each having a sampling circuit group as shown in Fig. 7, and reference numeral 2 is a liquid crystal display panel. A plurality of integrated circuits 1a..., 1b... Are provided along both edges of a horizontal direction (X direction) of the liquid crystal display unit 3 of the liquid crystal display panel 2, and an integrated circuit on one side of the liquid crystal display unit 3. The wiring group 4a ... to which the display drive signal is supplied in (1a ...) and the wiring group 4b ... to which the display drive signal is supplied in the integrated circuit 1b ... on the other side are alternately formed. Here, the arrangement direction of the output terminals 15a-15n of the integrated circuit 1a ... on one side and the arrangement direction of the output terminals 15a-15n of the integrated circuit 1b ... on the other side are inverted.

Here, the integrated circuits 1a ... on one side are sampled in the order of the sample hold circuits 12a-12n, and the integrated circuits 1b ... on the other side are sampled in the order of the sample hold circuits 12n-12a. Therefore, it is necessary to make the direction of the sampling operation order the same on both sides, and it becomes possible according to the liquid crystal display drive integrated circuit of FIG.

In addition, reference numerals 1c, 1d, ... are provided along both edges of the vertical direction (Y direction) of the liquid crystal display unit 3 on the liquid crystal display panel 2 to form a horizontal wiring of the liquid crystal display unit 3 during the tenth period. An integrated circuit for sequentially driving a group (not shown).

11 shows a sampling circuit group provided in the liquid crystal display driving integrated circuit according to the second embodiment of the present invention.

In Fig. 11, reference numerals 40a-40n denote a plurality of sampling circuits arranged in parallel, and the control circuits 11a-11n, the voltage follower circuits 13a-13n, and the output terminals 15a-15n are arranged in the first intermediate direction. Same thing as Reference numerals 42a-42n denote first digital data sample hold circuits, and reference numerals 43a-43n denote digital analog converter circuits, and Vcc1 is supplied as an operating power source, respectively.

FIG. 12 is a diagram showing one sampling circuit of the sampling circuit group shown in FIG.

FIG. 13 is a waveform diagram showing an operation example of the sampling circuit group of FIG.

The sampling circuit shown in FIG. 12 is a first digital data sample hold circuit 42 and a digital-analog conversion circuit 43 instead of the sample hold circuit 12 for analog signal voltage samples compared with the sampling circuit shown in FIG. The points of use are different, and since the control circuit 11, the voltage follower circuit 13, and the output terminal 15 are the same, the same reference numerals are used for the second diagram.

The first digital sample hold circuit 42 receives, for example, a sample supplied with a 4-bit digital data signal D0-D3 and supplied from a corresponding control circuit 11. The signals D0-D3 are sampled and held by S and ФS.

The first digital data sample hold circuit 42 includes a clock inverter 42i1 (i = 0-3) that the digital data signals D0-D3 correspondingly input and are driven by the sampling signal? S. Inverter 42i2 (i = 0-3) connected to the next stage corresponding to clock inverter 43i1, and inversely connected in correspondence to this inverter 42i1, and the sampling signal ( It consists of a clock inverter 42i3 (k = 0-3) driven by S), and a sample hold voltage DS0-DS3 is obtained at the output terminal of the inverter 42i1.

The digital-analog converting circuit 43 digital-analog converts the sample hold voltage DS0-DS3 supplied from the corresponding first digital data sample hold circuit 41 to perform the digital processing circuit 45 and the sample-hold circuit. It consists of 12.

One example of the digital processing circuit 45 includes the second sampling signal? L and the digital-analog conversion start signal L. FIG. L and the output voltages of the inverters 4504 and 4505 and the first digital data sample hold circuit 42 are generated by the second sampling signals? L and The second digital data sample hold circuit sampled and held by L) is compared with the output signals DS0-DS3 and the digital signals T0-T3 of the circuit, and the third sampling signal? DA and And a timing control circuit for generating DA).

The second digital data sample hold circuit includes a clock and an inverter 45i1 (i = 0-3) that the sample hold voltages DS0-DS3 correspondingly input and are driven by the second sampling signal? L. The inverter 45i2 (i = 0-3) connected to the next stage corresponding to the clock and the inverter 45i1, and the second sampling signal ( A clock driven by L), an inverter 45i3 (i = 0-3), and a second sample hold voltage DL0-DL3 is obtained at the output of the inverter 45i1.

The timing control circuit has an OR gate 46i1 (i = 0) in which the second sample hold voltage DL0-DL3 corresponds to one input terminal and the digital signal T0-T3 correspondingly inputs to the other input terminal. -3) and the NAND gate 46i2 (i =) in which the second sample hold voltage DL0-DL3 corresponds to one input terminal and the digital signal T0-T3 corresponds to the other input terminal. 0-3), NAND gates 46i3 (i = 0-3) corresponding to the respective outputs of these NAND gates 46i2 and the respective outputs of the OR gate 46i1, and these NAND gates 46i3; Signal complementary to the NAND gate 4604 inputted by each output of the < RTI ID = 0.0 >)< / RTI > An inverter 4605 for generating DA).

The digital signals T0-T3 are signals whose contents start to be converted step by step in synchronization with the timing of the digital and analog conversion start signal L. FIG.

The sample hold circuit 12 is inputted with an analog voltage VL whose magnitude starts to change linearly in synchronization with the digital and analog conversion start timing, and is supplied with the third sampling circuit ФDA supplied from the digital processing circuit 45. And The analog voltage VL is sampled and held by DA) to output a sample hold voltage VH. According to the digital and analog conversion circuit 43 in the twelfth time, the contents of the digital signals T0-T3 and the contents of the sample hold voltages DS0-DS3 for the 4-bit digital data signals D0-D3 are used. The matching timing is determined, and digital and analog conversion are possible by the operation of sample-holding the analog voltage VL whose magnitude changes linearly at the timing.

Therefore, according to the integrated circuit of the second embodiment, compared with the integrated circuit of the first embodiment, the digital data signals D0-D3 are sampled and the analog voltage VH corresponding thereto is output. The same effect is obtained.

In addition, the control circuits 11a-11n, the first digital data sample hold circuits 42a-42n, the digital and analog converter circuits 43a-43n, the voltage follower circuits 13a-13n, and the output terminals (11) By providing three systems 15a-15n corresponding to three colors for color liquid crystal display, an integrated circuit for driving a color liquid crystal display can be configured.

FIG. 14 shows a modification of the sampling circuit group of FIG.

This sampling circuit group includes an address counter 300 similarly to the sampling circuit group shown in FIG. 7, and the control circuits 31a-31n of each sampling circuit have an address decoder 311 as shown in FIG. Are different from each other, and since they are identical, the same reference numerals are assigned to the eleventh degree.

FIG. 15 is a circuit diagram showing one sampling circuit in the sampling circuit group of FIG. 14, with the same reference numerals as in FIG. 8 or 12. FIG.

According to the integrated circuit having the sampling circuit group shown in FIG. 14, as shown in FIG. 10, it can be provided along the edges in the horizontal direction of the liquid crystal display unit 3 on the liquid crystal display panel 2 and used.

In addition, drawing reference numbers which refer to the respective constituent requirements of the claims of the present application are provided to aid the understanding of the present invention, and are not intended to limit the technical scope of the present invention to the embodiments shown in the drawings.

As described above, according to the present invention, it is easy to accurately set the waveform of the sampling signal, to prevent the malfunction of sampling by the two sampling circuits at the same time, and to design the pattern of the control circuit as the low voltage corresponding circuit pattern. In addition, it is possible to realize a sampling circuit which can prevent the mask pattern from being enlarged and at the same time suppress the increase in power consumption due to the high speed.

Claims (14)

Each of the plurality of control circuits 11a-11n and 31a-31n for supplying a sampling signal by supplying the first power supply voltage Vcc1 as an operating power source and generating the sampling signal, respectively, is provided in correspondence with the plurality of control circuits, respectively. Vcc1) is supplied as an operating power source, and a plurality of sample hold circuits 12a-12n which input analog signal voltages in common and sample-hold the analog signal voltages by sampling signals correspondingly supplied from the plurality of control circuits. And a sample provided corresponding to the plurality of sample hold circuits, each of which is supplied with a second power supply voltage Vcc2 higher than the first power supply voltage Vcc1 as an operating power source, and outputs correspondingly from the plurality of sample hold circuits. A plurality of voltage follower circuits 13a-13n for impedance-converting the hold voltage and outputting them are provided corresponding to the plurality of voltage follower circuits. Of the voltage follower to each of the output voltage of the circuit for the liquid crystal display driving integrated circuit comprising: a plurality of output terminals (15a-15n) for outputting to the outside as shown for driving the liquid crystal device. 2. The integrated circuit for driving a liquid crystal display according to claim 1, wherein the second power supply voltage (Vcc2) is selected so that an operating voltage range of the voltage follower circuit has a predetermined linear region. 3. The integrated circuit for driving a liquid crystal display according to claim 1 or 2, wherein said second power supply voltage (Vcc2) is 1.2V or more higher than said first power supply voltage (Vcc1). The liquid crystal display according to claim 1, wherein the plurality of control circuits (11a-11n) are cascaded to form a shift register, and transmit a sampling signal input to the control circuit of the first stage by a transmission clock signal. Integrated circuit for driving. 2. The apparatus of claim 1, further comprising an address counter 300 for dividing a clock signal to output an address signal, wherein the control circuits 31a-31n decode the address signal supplied to the address counter to decode the sampling signal. An integrated circuit for driving a liquid crystal display, characterized by having an address decoder (311) generated. 2. The integrated circuit for driving a liquid crystal display according to claim 1, wherein voltages output from the plurality of output terminals are supplied as a display input of an active, matrix type liquid crystal display device. A plurality of control circuits 11a-11n and 31a-31n each having a first power supply voltage Vcc1 supplied as an operating power supply to generate a sampling signal, are provided corresponding to the plurality of control circuits, respectively, and the first power supply voltage is respectively provided. A plurality of first digital data sample hold circuits, which are supplied as an operating power source, with which digital data signals are commonly input and sample-hold the digital data signals by corresponding sampling signals supplied from the plurality of control circuits. 42a to 42n, corresponding to the plurality of first digital data sample hold circuits, wherein the first power supply voltage Vcc1 is supplied as an operating power source, respectively, and corresponds to the plurality of first digital data sample hold circuits. A plurality of digital and analog converter circuits 43a to 43n for digital-analog converting the sample-hold voltage supplied by the A second power supply voltage Vcc2, which is provided in correspondence with the analog conversion circuit and is respectively higher than the first power supply voltage Vcc1, is supplied as an operating power supply, and the analog outputs are output correspondingly by the plurality of digital and analog conversion circuits. A plurality of voltage follower circuits 13a-13n for impedance-converting and outputting a voltage and the plurality of voltage follower circuits provided to correspond to the plurality of voltage follower circuits to output each output voltage of the plurality of voltage follower circuits externally for driving the display of the liquid crystal device. And a plurality of output terminals (15a-15n) for the liquid crystal display drive integrated circuit. 8. The digital data sample hold circuit (45i1, 45i2, 45i3) according to claim 7, wherein the sound digital and analog converting circuit includes: second digital data sample hold circuits 45i1, 45i2, 45i3 (i) for holding the output voltage of the first digital data sample hold circuit by a second sampling signal; = 0-3)), comparing the output signal of the second digital data sample hold circuit with the digital signal whose contents start to change step by step in synchronization with the digital and analog conversion start timing, and generating a timing signal upon detection of coincidence Timing control circuits 46i1, 46i2, 46i3 (i = 0-3), 4604, 4605 and digital, analog voltages start to deform linearly in synchronization with the timing of the analog conversion start, and an analog voltage is inputted. And a sample hold circuit (12) for sample-holding the analog voltage by a third sampling signal supplied. The control circuit, the first digital data sample hold circuit, the digital, analog conversion circuit, the voltage follower circuit, and the output terminal are respectively provided in three lines corresponding to three colors for color liquid crystal display. An integrated circuit for driving a liquid crystal display, characterized by the above-mentioned. 8. The integrated circuit for driving a liquid crystal display according to claim 7, wherein the second power supply voltage (Vcc2) is selected so that an operating voltage range of the voltage follower circuit has a predetermined linear region. 8. The integrated circuit for driving a liquid crystal display according to claim 7, wherein the second power supply voltage (Vcc2) is 1.2V or more higher than the first power supply voltage (Vcc1). 8. The liquid crystal display according to claim 7, wherein the plurality of control circuits (11a-11n) are cascaded to form a shift register, and transmit a sampling signal input to the control circuit of the first stage by a transmission clock signal. Integrated circuit for driving. 8. The apparatus of claim 7, further comprising an address counter (300) for dividing a clock signal to output an address signal, wherein the control circuits (31a-31n) have an address decoder (311) supplied from the address counter. An integrated circuit for driving a liquid crystal display. 8. The integrated circuit for driving a liquid crystal display according to claim 7, wherein voltages output from the plurality of output terminals are supplied as a display input of an active, matrix type liquid crystal display device.