JP3268075B2 - Drive circuit for liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a liquid crystal display device, and more particularly to a driving circuit for a liquid crystal display device to which a digital image signal is applied and which performs gradation display corresponding to the digital value.

[0002]

2. Description of the Related Art Conventionally, there has been known a driving circuit of a liquid crystal display device which receives a digital image signal and performs gradation display corresponding to the digital value.

FIG. 9 shows a driving circuit of a liquid crystal display device when an image signal is given as digital data. FIG. 11 specifically shows the data memory and the selection control circuit in FIG.

[0004] The drive circuit shown in FIG. 9 is a data sampling signal for storing digital image data in a memory.
A shift register 901 for shifting TSMPn, a data memory 902 for taking in and storing the image data signals D0 to D3 in synchronization with the data sampling signal TSMPn, and decoding and decoding the image data signals D0 to D3, and 16 external reference power supplies corresponding to the values. A decoder 903 that outputs any one of V0 to V15 to an output circuit, and an output circuit that receives outputs of the decoder and outputs outputs O1 to On.

The data memory and the selection control circuit in FIG. 9 will be described more specifically with reference to FIG. The data memory synchronizes with the sampling signal TSMPn corresponding to the n-th picture element of the liquid crystal display device to synchronize the image data signals D0 to D0.
Sampling memory 1101 for storing D3, and sampling memory 11 in response to output enable signal OE.
It is composed of a hold memory 1102 that takes in the output of “01”. The selection control circuit portion has a decoder 1103 for selecting any one of the control signals S0 to S15 according to the output of the hold memory 1102, and control inputs S0 to S15, and connects the reference power supplies V0 to V15 to the output On. It comprises analog switches 1104 to 1119.

This drive circuit operates as follows. The image data signals D0 to D3 are stored in the sampling memory in synchronization with the sampling signal TSMPn corresponding to the n-th picture element of the liquid crystal display device. Then, after the sampling in one horizontal period is completed, the image data stored in the sampling memory by the output enable signal OE is taken into the hold memory and output to the decoder. The decoder decodes the 4-bit image data D0 to D3, turns on one of the analog switches according to the value (0 to 15), and sets 16 types of external reference power supply V0.
To V15 are output to the output On.

In the above example, the image data has 4 bits, that is, 1 bit.
In the case of six gradations, since it is necessary to externally supply the same number of reference power supplies as the number of gradations and to provide the same number of analog switches for each output, there is a limit in increasing the number of gradations.
Therefore, as shown in FIG.
A method has been proposed in which an A / A converter 1003 converts the voltage into an analog voltage and outputs the analog voltage. In the case of this drive circuit,
Even if the number of gradations is increased, the circuit scale does not extremely increase as in the conventional examples shown in FIGS.

The D / A converter 1003 shown in FIG. 10 has several circuit types.
As the / A converter, an operation speed may be slow, but a converter with high accuracy and easy integration is required. So Figure 1
It has been proposed to use a charge-redistribution type D / A converter as shown in FIG.

A circuit configuration of the D / A converter will be described. One end of the capacitor C1 is connected to a high-side power supply VH via an analog switch 1201 having a control input S1, and is connected to a low-side power supply VL via an analog switch 1202 having a control input S2. Capacitor C1
Is connected to an analog switch 12 having a control input S9.
09 is connected to one end.

One end of the capacitor C2 is connected to a high-side power supply VH via an analog switch 1203 having a control input S3.
Switch 1 which is connected to
It is connected to the low-side power supply VL via the line 204. The other end of the capacitor C2 is connected to one end of the analog switch 1209.

One end of the capacitor C3 is connected to a high-side power supply VH via an analog switch 1205 having a control input S5.
Switch 1 connected to the switch and having a control input S6
It is connected to the low-side power supply VL via 206. The other end of the capacitor C3 is connected to one end of an analog switch 1209.

One end of the capacitor C4 is connected to a high-side power supply VH via an analog switch 1207 having a control input S7.
Switch 1 connected to the switch and having a control input S8
It is connected to the low-side power supply VL via a power supply 208. The other end of the capacitor C4 is connected to one end of the analog switch 1209.

Assuming that the capacitance of the capacitor C1 is a reference capacitance C0, the capacitance of C2 is 2C0, the capacitance of C3 is 4C0, and the capacitance of C4 is 8C0.

One end of the analog switch 1209 is connected to the low-side power supply VL via an analog switch 1210 having a control input S10. Analog switch 12
09 is an analog switch 1 having a control input S11.
It is connected to the low-side power supply VL via 211. The other end of the analog switch 1209 is connected to an output OS of an operational amplifier 1213 via an analog switch 1212 having a control input S12. One end of the capacitor C5 is connected to the other end of the analog switch 1209, and the other end of the capacitor C5 is connected to the output OS of the operational amplifier 1213. The other end of the analog switch 1209 is connected to the inverting input of the operational amplifier 1213. Operational amplifier 12
The low-side power supply VL is connected to the non-inverting input of 13. The analog switches 1201 to 1212 are closed (on) when the control input is logic high (H) and are opened (off) when the control input is logic low (L).

This D / A converter operates as follows. First, analog switch control inputs S2, S4, S
6, S8, S10, S11 and S12 are set to "H" to discharge the electric charges of the capacitors C1 to C5. Next, the image data D0 to D3
The capacitors C1 to C4 are charged with electric charges in accordance with the respective bits. That is, the control input S10 of the analog switch is turned on, and one end of each of the capacitors C1 to C4 is connected to the low-side power supply VL.
Level, and when each image data is "1", the control inputs S1, S3, S5, and S5 of the analog switches are connected so that the other ends of the capacitors C1 to C4 are connected to the high-side power supply VH.
S7 is set to "H". Next, the control inputs S1, S3, S5, S7, S10, S11, S12 of the analog switches are set to "L", and the control inputs S2, S4, S6, S of the analog switches are set.
8 and S9 are set to "H" to set the capacitors C1 and C2.
, C3, C4 are transferred to the capacitor C5. That is, the output OS of the D / A converter in FIG.
VOS = (D0 C0 + D1 ・ 2C0 + D2 ・ 4C0 + D
3 · 8C0) / 16C0 (VH-VL). For example, if the image data is (D0, D1, D2
, D3) = (1, 1, 0, 1), the voltage VOS of the output OS of the D / A converter = 11/16 (VH-VL)
). As described above, D / A is performed according to the value of the image data.
The voltage VOS of the output OS of the converter is 0/16 (VH−
(VL) to 15/16 (VH-VL).

[0016]

[Problems to be solved by the invention]

I. Conventional Example: Cases of FIGS. 9 and 11 1) As described above, since it is necessary to externally apply the same number of reference voltages as the number of gray scales, there is a limit to increasing the number of gray scales. In order to realize full color display, R,
Each of G and B requires 8 bits, that is, 2 ⁸ = 256 gradations. However, providing 256 reference voltage sources requires a large circuit scale and is practically difficult.

2) It is necessary to provide a switch for selecting an externally applied reference voltage for each output. Similarly to the above 1), in the case of 256 gradations, 256 analog switches are provided for each output. It becomes necessary and the number of circuit elements becomes enormous.

II. Conventional Example In the case of FIGS. 10 and 12 1) Although the increase in the reference voltage source and the analog switch can be suppressed as described in I above, (the number of image data + 1) capacitors are required, and these are required for the image data. It is necessary to assign corresponding weights. Therefore, when the image data is 4 bits and 16 gradations as shown in FIG. 9, the capacitances C0 and 2C0
, 4C0, 8C0, and 16C0, but the number of circuit elements increases as the number of gradations increases. For example, when the image data has 8 bits and 256 gradations, the capacity C
0, 2C0, 4C0, 8C0, 16C0, 32C0, 6
Nine capacitors, 4C0, 128C0, 256C0, are required, and the number of circuit elements becomes enormous.

2) Also, the capacitors need to be weighted, and in the case of 256 gradations, it is necessary to have a capacitance ratio of 1: 256. When these are realized by an integrated circuit, the minimum unit capacitor needs to have a certain size (about 0.1 to 1 pF) or more in order to suppress the influence of the parasitic capacitance, which causes an increase in the integrated circuit pattern. . Further, as long as the capacitors need to be weighted, it is impossible to completely eliminate errors in pattern design.

An object of the present invention is to provide a driving circuit for a liquid crystal display device which solves the above problems, suppresses an increase in the number of circuit elements, and realizes high-precision multi-tone display.

[0021]

According to the present invention, there is provided a driving circuit for a liquid crystal display device, comprising: means for storing inputted digital image data; a reference voltage source inputted from outside or generated internally; Means for selecting any one of the reference voltages from the reference voltage source according to the stored digital image data; means for selecting a next higher or lower reference voltage of the selected reference voltage; A D / A converter that interpolates and outputs an analog voltage at an intermediate level between the reference voltages, and a unit that outputs the analog voltage as a gray scale display signal, wherein the D / A converter has a plurality of equal capacitance values. It is characterized by comprising a plurality of capacitors, an operational amplifier for amplifying a signal, and a switch circuit for controlling the transfer of charges between the plurality of capacitors. Further, the output power of the D / A converter
Voltage is positive for the highest voltage reference
Output, and negative polarity for the lowest voltage reference power supply
The D / A converter is configured so that the
It is characterized by being performed.

Further, the D / A converter may output an output voltage corresponding to a display gradation by repeating an operation of distributing charges to a plurality of capacitors having the same capacitance value.

[0023]

Further, there is provided means for selecting and switching a reference voltage source of the D / A converter from a plurality of reference voltage sources inputted from outside or generated internally in accordance with the stored digital image data. May be provided.

[0025]

[0026]

[0027]

[0028]

According to the present invention, input digital image data is stored. According to the stored digital image data
Select one of the reference voltages from the reference voltage source.
The next higher or lower reference of the selected reference voltage
The voltage is selected. D / A converter is the selected standard
An intermediate level analog voltage between the voltages is interpolated and output by repeating the operation of distributing charges to a plurality of capacitors having the same capacitance value . Analog voltage is gradation display
Output as a signal .

[0029]

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a driving circuit showing one embodiment of the present invention. 2 and 3 show examples of the circuit configuration of the D / A converter in FIG. FIG. 5 is a circuit configuration example of the operational amplifiers of FIGS. 1, 2, and 3. FIG. 6 is a block diagram of the drive circuit of the present invention. FIGS. 7 and 8 are timing charts showing an example of the operation of the drive circuit of the present invention.

In this embodiment, the case where the image data is 6 bits, that is, 64 gradations will be described. As shown in FIG. 6, the data memory 902 stores the image data signals D0 to D5, and the voltage levels of 64 gradations corresponding thereto are stored in five reference voltage sources V0 to V4, the selection control circuit 602 and the D / A.
It is assumed that the signal is output by the converter 601. FIG. 1 specifically shows one output of FIG.

The drive circuit of the liquid crystal display device shown in FIG. 1A includes a sampling memory 101 for storing image data signals D0 to D5, a hold memory 102 for taking in the image data stored in the sampling memory 101, and image data. High-side reference power supply selection circuit 1 for selecting high-side reference power supply VH of D / A converter 106 according to D4 and D5
04, analog switches SH0 to SH4 for connecting any one of the external reference power supplies V0 to V4 to the high-side reference power supply VH of the D / A converter 106, corresponding to the output of the high-side reference power supply selection circuit 104; D according to D4 and D5
The low-side reference power supply selection circuit 105 for selecting the low-side reference power supply VL of the / A converter 106, and one of the external reference power supplies V0 to V4 is D / A corresponding to the output of the low-side reference power supply selection circuit 105. Analog switches SL0 to SL4 connected to the low-side reference power supply VL of the converter 106, D / A
D / A converter selection control circuit 1 for generating signals S1 to S6 for controlling on / off of analog switches of converter 106 from image data signals D0 to D3 and clock signal CK
03, 1 corresponding to lower 4 bits D0 to D3 of image data
D / A converter 10 that outputs voltage levels of 6 gradations
6. The operational amplifier 107 amplifies the output OS of the D / A converter 106. Sampling memory 10
1 and the hold memory 102 are composed of a D flip-flop 108 shown in FIG. The analog switch is a CMOS transfer gate 110 as shown in FIG.
And an inverter 111.

FIG. 2 shows an example of a circuit configuration of the D / A converter 106 shown in FIG. The D / A converter of FIG. 2 has the same capacitance value (about 0.1 to 1 pF on an integrated circuit).
It comprises the capacitors C1, C2, C3, the operational amplifier 107, and the six analog switches (201 to 206). The signals S1 to S6 for controlling the on / off of these analog switches are the image data signals D0.
ＤD3 and the clock signal CK are generated by the D / A converter selection control circuit of FIG. The high-side reference power supply VH is connected to one end of a capacitor C1 via an analog switch 201 having a control input S1. The other end of the capacitor C1 is connected to a low-side reference power supply. One end of the capacitor C1 is connected to one end of the capacitor C2 via an analog switch 202 having a control input S2. The other end of the capacitor C1 is connected to the other end of the capacitor C2 via an analog switch 203 having a control input S3. One end of the capacitor C2 is connected to a low-side reference power supply VL via an analog switch 204 having a control input S4. The other end of the capacitor C2 is connected to an inverting input of the operational amplifier 107 via an analog switch 205 having a control input S5. Operational amplifier 10
The output OS 7 is connected to the inverting input of the operational amplifier 107 via an analog switch 206 having a control input S6. The output OS of the operational amplifier 107 is a capacitor C3
Is connected to one end. The other end of the capacitor C3 is connected to the inverting input of the operational amplifier 107. The low-side reference power supply VL is connected to the non-inverting input of the operational amplifier 107.

FIG. 5 is a circuit diagram of the operational amplifier 107.
The drain of P-channel MOS transistor 501 is connected to power supply Vcc. The source of P-channel MOS transistor 501 is P-channel MOS transistor 50
1 gate. The drain of P-channel MOS transistor 502 is connected to power supply Vcc. The gate of P-channel MOS transistor 502 is
It is connected to the source of the channel MOS transistor 501. The source of P-channel transistor 501 is connected to the drain of P-channel MOS transistor 503. The non-inverting input is a P-channel MOS transistor 5
03 is connected to the gate. The source of P-channel MOS transistor 503 is connected to the drain of N-channel MOS transistor 505. P channel MO
The source of S transistor 502 is connected to the drain of N channel MOS transistor 504. The inverting input is connected to the gate of the N-channel MOS transistor 504. The source of N-channel MOS transistor 504 is connected to the drain of N-channel MOS transistor 505. N channel MOS transistor 50
The gate of No. 5 is connected to the bias voltage Vb. The source of N-channel MOS transistor 505 is connected to ground. The drain of N-channel MOS transistor 506 is connected to power supply Vcc. N channel M
The gate of the OS transistor 506 is connected to the source of the P-channel MOS transistor 502. The source of N-channel MOS transistor 506 is connected to output OA. The drain of N-channel MOS transistor 507 is connected to output OA. N channel MOS
The gate of the transistor 507 is connected to the bias voltage Vb. The source of N-channel MOS transistor 507 is connected to ground.

The driving circuit of the liquid crystal display device having the above configuration operates as follows.

The image data signals D0 to D5 are stored in the sampling memory 101 by the sampling signal TSMPn corresponding to the n-th picture element of the liquid crystal display. After the sampling in one horizontal period is completed, the image data stored in the sampling memory 101 by the output enable signal OE is taken into the hold memory 102, and the high-side reference power supply selection circuit 104, the low-side reference power supply selection circuit 105 And D / A converter selection control circuit 103
Is output to First, the analog switches SH0 to SH4 are output by the output signals H0 to H4 of the high-side reference power supply selection circuit corresponding to the upper 2 bits of the 6 bits of image data.
4 is turned on to change the high-side reference power supply VH of the D / A converter 106 to the reference power supplies V0 to V0.
Connect to one of 4. Similarly, for the low-side reference power supply VL, the output signals L0 to L
By turning on any one of the analog switches SL0 to SL4 in response to the signal 4, it is connected to one of the reference power supplies V0 to V4. The upper two bits D4 of the image data,
Table 1 shows an example of the correspondence between D5 and the reference power supply connected to VH and VL.
Shown in

[0038]

[Table 1]

Next, the lower 4 bits D0 to D3 of the image data
D / A converter 1 converts 16 voltage levels corresponding to
06, it is output as an intermediate level between VH and VL. Regarding this operation, the D / A converter 106 shown in FIG.
FIG. 7 shows an example of a timing chart when the circuit of FIG. 2 is used.

Hereinafter, according to the timing chart of FIG. 7, the lower four bits (D0, D1, D2, D3) of the image data will be described.
) = (1, 1, 0, 1) as an example.

(1) The output enable signal OE becomes active (in this case, "H"), and the reference power supplies VH and VL of the D / A converter according to Table 1 as in the above-described example.
Are connected to any of the reference power supplies V0 to V4. At the same time, the analog switch control inputs S1, S3, S4, S5,
S6 is set at "H", and the control input S2 of the analog switch is set at "L". The analog switches connected to these signals are turned on at "H" and turned off at "L". The capacitor C1 has VH-VL (= VR, where VH> VL).
), And the capacitors C2, C3
Is discharged.

(2) Next, after the control inputs S1, S4, S5, and S6 of the analog switch are set to "L", the control input S2 of the analog switch is set to "H" to charge the capacitor C1. The charge is distributed to the capacitor C2. Since the capacitors C1 and C2 have the same capacity, the voltage level of the capacitors C1 and C2 becomes 1/2 VR with respect to the low-side reference power supply VL.

(3) Next, the control input S of the analog switch
After setting both S2 and S3 to "L", the control input S4 of the analog switch is set to "H", and one end on the positive charge side of the capacitor C2 is connected to the non-inverting input of the operational amplifier. At this time, the control input S5 of the analog switch corresponds to the image data D3.
Controls the on / off of the analog switch connected to.
If D3 is 0, it is off; if it is 1, it is on. In this example, D
Since 3 = 1, the negative input of the capacitor C2 is connected to the inverting input of the operational amplifier by setting the control input S5 of the analog switch to "H". Since both inputs of the operational amplifier have the same potential (imaginary short), the charge of the capacitor C2 is transferred to the capacitor C3, and the voltage level VOS of the output OS of the D / A converter is VL + 1 / 2V.
It becomes R.

(4) Next, the control input S of the analog switch
5 is set to "L" and the control input S3 of the analog switch is turned on while the control input S4 of the analog switch is set to "H" to discharge the electric charge of the capacitor C2.

(5) In the same manner as in (2), the capacitor C2
To 1 / 4VR.

(6) The same processing as (3) is performed. However,
In this example, since D2 = 0, the control input S5 of the analog switch remains "L", and the charge of the capacitor C2 is not transferred to the capacitor C3. Accordingly, the voltage level of the output OS of the D / A converter, VOS = VL + 1 / 2VR, is maintained.

(7) In the same manner as (4), the capacitor C2
To discharge the charge.

(8) In the same manner as in (2), the capacitor C2
To 1 / 8VR.

(9) The same processing as (3) is performed. In this example, since D1 = 1, the control input S5 of the analog switch
Becomes "H" and the electric charge of the capacitor C2 is changed to the capacitor C3.
Is forwarded to Therefore, the voltage level VOS of the output OS of the D / A converter VOS = VL + 1 / 2VR + 1 / 8VR = VL +
It becomes 5 / 8VR.

(10) In the same manner as in (4), the capacitor C
Discharge the charge of 2.

(11) In the same manner as in (2), the capacitor C
Charge 1 / 16VR to 2.

(12) The same processing as (3) is performed. In this example, since D0 = 1, the control input S5 of the analog switch
Becomes "H", and the electric charge of the capacitor C2 is transferred to the capacitor C3. Therefore, the voltage level VOS of the output OS of the D / A converter includes (D0, D1, D2, D3) =
A voltage level corresponding to (1,1,0,1) is output. That is, the voltage level V of the output OS of the D / A converter
OS = VL + 1 / 2VR + ／ VR + 1 / 16VR = V
L + 1/16 VR. Image data D0 to D3 and VO
Table 2 shows an example of S level correspondence.

[0053]

[Table 2]

The above description has been made for the case of 16 gradations. However, by further repeating the charge distribution, the multi-gradation can be performed without increasing the number of elements such as capacitors by the same D / A converter as in FIG. Is possible.

In the above description, the reference power supply VH> VL
However, the same applies to the case where the reference power supply VH <VL.

Next, another example of the D / A converter 106 shown in FIG. 1 is shown in FIG. In this case, it is possible to configure five analog switches. The high-side reference power supply VH is connected to one end of a capacitor C1 via an analog switch 301 having a control input S1. The other end of the capacitor C1 is connected to a low-side reference power supply. Capacitor C
One end of an analog switch 30 having a control input S2
2 is connected to one end of the capacitor C2. One end of the capacitor C2 is connected to an inverting input of the operational amplifier 107 via an analog switch 304 having a control input S4. One end of the capacitor C2 is connected to the low-side reference power supply V via an analog switch 303 having a control input S3.
Connected to L. The other end of the capacitor C2 is connected to the low-side reference power supply VL. Output O of operational amplifier 107
S is connected to the inverting input of the operational amplifier 107 via an analog switch 305 having a control input S5. The output OS of the operational amplifier 107 is connected to one end of the capacitor C3. The other end of the capacitor C3 is an operational amplifier 10
7 inverting input. The low-side reference power supply VL is connected to the non-inverting input of the operational amplifier 107.

FIG. 8 shows a timing chart when the circuit example of FIG. 3 is used. In the circuit example of FIG. 3, the reference power supply VH
If> VL, one end on the negative charge side of the capacitor C2 is connected to the non-inverting input of the operational amplifier and the charge is transferred to C3, so that the voltage level of VOS is negative with respect to VL as shown in FIG. Become. The description of the operation is similar to that of FIG.

FIG. 4 shows another example of the D / A converter 106 shown in FIG. The high-side reference power supply VH is connected to one end of a capacitor C1 via an analog switch 401 having a control input S1. The other end of the capacitor C1 is connected to the low-side reference power supply VL. One end of the capacitor C1 is connected to one end of the capacitor C2 via an analog switch 402 having a control input S2. The other end of the capacitor C1 is connected to the other end of the capacitor C2 via an analog switch 403 having a control input S3. One end of the capacitor C2 is connected to a low-side reference power supply VL via an analog switch 404 having a control input S4.
One end of the capacitor C2 is connected to an inverting input of the operational amplifier 107 via an analog switch 405 having a control input S5. One end of the capacitor C2 is connected to the control input S
It is connected to the non-inverting input of the operational amplifier 107 via an analog switch 406 having a 6. Capacitor C2
The other end of the analog switch 407 having a control input S7
Is connected to the inverting input of the operational amplifier 107 via the. The output OS of the operational amplifier 107 is connected to the inverting input of the operational amplifier 107 via an analog switch 410 having a control input S10. Output O of operational amplifier 107
S is connected to the inverting input of the operational amplifier 107 via the capacitor C3. The high-side reference power supply VH is controlled by a control input S8.
1 via an analog switch 408 having
07 non-inverting input. Low side reference power supply V
L is connected to the non-inverting input of the operational amplifier 107 via an analog switch 409 having a control input S9.

The D / A converter of FIG. 4 can be switched to the circuit function shown in FIG. 2 or the circuit function shown in FIG. 3 by analog switches 401 to 410. The operation is the same as in FIG. 2 or FIG. 3, and the description of the operation is omitted.

Here, in the driving circuit of FIG. 1, the D / A converter of FIG. 2 and the D / A converter of FIG. 3 are used in combination, or as shown in FIG. When the reference power supply VH of the D / A converter is connected to the highest reference voltage in the embodiment of FIG. 1, the non-inverting input of the operational amplifier is connected to the reference power supply VH, and the output voltage VOS of the operational amplifier is connected. Are output in the positive direction with reference to the reference power supply VH. When the reference power supply VL of the D / A converter is connected to the lowest reference voltage, the non-inverting input of the operational amplifier is connected to the reference power supply VL, and as shown in the circuit example of FIG. Output is made in the negative direction with reference to the reference power supply VL. This makes it possible to suppress an increase in the reference voltage source of the drive circuit when the number of gradations is increased. For example, in the embodiment of FIG.
, V4 are not required, and the same function can be realized by three external reference power supplies.

In the above embodiment, the case where the electric charge is distributed to two equal capacitance capacitors has been described. However, three or more equal capacitance capacitors can be used. The reference power supplies V0 to V4 can be generated inside the drive circuit by a resistor divider circuit or the like, in addition to the case where they are externally supplied, and a part of them can be shared with the power supply voltage. is there.

According to the present invention, it is possible to reduce an increase in the number of circuit elements accompanying the increase in the number of gradations in a liquid crystal drive circuit that performs gradation display corresponding to digital image data.
In particular, the use of the D / A converters shown in FIGS. 2 to 4 makes it possible to increase the number of gradations by simple timing control without increasing the number of capacitors and analog switches, and to achieve high-precision integration. is there. As shown in the embodiment of FIG. 1, a D / A converter generally used for a liquid crystal drive circuit requires higher integration than high-speed operation, and the present invention can realize this. As described above, it is extremely useful for increasing the number of gradations.

[0063]

As described in detail above, the driving circuit of the liquid crystal display device according to the present invention comprises a means for storing the input digital image data and a reference which is externally input or internally generated. One of the reference voltage sources according to a voltage source and the stored digital image data.
Means for selecting one reference voltage, means for selecting the next higher or lower reference voltage of the selected reference voltage, and D for interpolating and outputting an intermediate level analog voltage between the selected reference voltages. / A converter, and means for outputting the analog voltage as a gray scale display signal,
Since the D / A converter is constituted by a plurality of capacitors having the same capacitance value, an operational amplifier for amplifying a signal, and a switch circuit for controlling the transfer of electric charge between the plurality of capacitors, an integrated circuit pattern is increased. Can be reduced. Further, an increase in the number of reference voltage sources and analog switches can be suppressed. Furthermore, the book
The drive circuit of the liquid crystal display device according to the invention is characterized in that the D / A converter
Output voltage is positive for the highest voltage reference supply.
It is output in the direction of polarity, and
The D / A converter so that it is output in the negative polarity direction.
Since the inverter is configured, the reference voltage source and the number of circuit elements
Can be suppressed.

Further, the D / A converter may output an output voltage corresponding to a display gradation by repeating an operation of distributing charges to a plurality of capacitors having the same capacitance value. The increase can be suppressed.

[0065]

Further, there is provided means for selecting and switching a reference voltage source of the D / A converter from a plurality of reference voltage sources inputted from outside or generated internally according to the stored digital image data. Since it is provided, it is possible to suppress an increase in the number of circuit elements.

[0067]

[0068]

[0069]

[Brief description of the drawings]

FIG. 1 is a driving circuit according to an embodiment of the present invention.

FIG. 2 is a circuit example of a D / A converter used in the drive circuit of FIG.

FIG. 3 is another example of a D / A converter circuit used in the drive circuit of FIG. 1;

FIG. 4 is another example of a D / A converter circuit used in the drive circuit of FIG. 1;

FIG. 5 is a circuit example of an operational amplifier used in FIGS. 1 to 4;

FIG. 6 is a block diagram of a driving circuit according to an embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the D / A converter of FIG. 2;

FIG. 8 is a timing chart for explaining the operation of the D / A converter of FIG. 3;

FIG. 9 is a block diagram of a driving circuit according to a conventional example.

FIG. 10 is a block diagram of a drive circuit according to another example of the conventional example. .

FIG. 11 is a drive circuit according to a conventional example.

FIG. 12 is a circuit diagram of a D / A converter according to a conventional example.

[Explanation of symbols]

 Reference Signs List 101 sampling memory 102 hold memory 103 D / A converter selection control circuit 104 high-side reference power supply selection circuit 105 low-side reference power supply selection circuit 106 D / A converter 107 operational amplifier

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3 / 18,3 / 36 G02F 1/133 G09F 9/35 H03M 1/00-1/88

Claims (3)

(57) [Claims] A means for storing input digital image data; a reference voltage source externally input or generated internally; and a reference voltage source selected according to the stored digital image data. Means for selecting one of the reference voltages, means for selecting the next higher or lower reference voltage of the selected reference voltage, and output by interpolating an intermediate level analog voltage between the selected reference voltages. And a means for outputting the analog voltage as a gray scale display signal, wherein the D / A converter comprises a plurality of capacitors having equal capacitance values, an operational amplifier for amplifying a signal, and the plurality of capacitors. Liquid crystal composed of a switch circuit that controls the transfer of charge between
A drive circuit for a display device, wherein an output voltage of the D / A converter is a base voltage of a highest voltage.
For the quasi power supply, the output is in the positive polarity direction,
Output in the direction of negative polarity with respect to the voltage reference power supply
A driving circuit for a liquid crystal display device , wherein the D / A converter is configured . 2. The method according to claim 1, wherein the D / A converter has an equal capacitance value.
The operation of distributing the charge to multiple capacitors
Output voltage corresponding to the display gradation.
The driving of the liquid crystal display device according to claim 1, characterized in that:
circuit. 3. According to the stored digital image data.
Input the reference voltage source of the D / A converter from outside.
Multiple reference voltages supplied or internally generated
Characterized by having means for selecting and switching from among
The drive circuit for a liquid crystal display device according to claim 1, wherein