KR100771353B1 - Digital-to-analog converter circuit - Google Patents

Abstract

The present invention is to accurately perform digital analog conversion using the capacity ratio. The 0-bit data is supplied to the capacitor 430-0 through the charge control transistor 420-0, and the 1-bit data is supplied through the charge control transistor 420-1 to the capacitor 430-. 1), and the second bit of data is supplied to the capacitor 430-2 through the charge control transistor 420-2. The transistors of the charge control transistors 420-0, 420-1, and 420-2 are 1: corresponding to the capacitors 430-0, 430-1, and 430-2 in which the capacity ratio is 1: 2: 4. Set to 2: 4. Thereby, the capacitors 430-0, 430-1, and 430-2 can be charged under the same conditions.

Video lines, switches, horizontal transfer registers, amplifiers, capacitors, transistors, analog video data, horizontal scan lines

Description

Digital analog conversion circuit {DIGITAL-TO-ANALOG CONVERTER CIRCUIT}

1 is a diagram showing a configuration for supplying video data to a pixel circuit in a liquid crystal display device according to an embodiment;

2 is a diagram showing the configuration of a latch type level shift circuit (SRAM 16) and a latch circuit (SRAM 18) for latching an output of the SRAM 16. FIG.

3 is a diagram illustrating a configuration of higher bit conversion of the DAC 20. FIG.

4 is a diagram illustrating an example of the configuration of the lower bit conversion and the amplifier 22 of the DAC 20.

5A is a diagram for explaining the operation of the circuit of the amplifier 22. FIG.

5B is a diagram for explaining the operation of the circuit of the amplifier 22. FIG.

FIG. 6 is a diagram showing another circuit example for eliminating an output error of the buffer amplifier 452 in the amplifier 22. FIG.

FIG. 7 is a diagram showing another example of the configuration of the lower bits of the DAC 20. FIG.

8 is a diagram illustrating a configuration of a switching switch 24.

9 is a diagram showing waveforms of a WHITE signal and a BLACK signal;

10 is a diagram illustrating a configuration for precharging a data line.

11 is a diagram showing a schematic configuration of a configuration of a pixel circuit forming two capacitor lines.

12 is a view for explaining a voltage application state to the liquid crystal.

13 is a diagram illustrating waveforms of various signals.

14 is a timing chart for video data congestion.

Fig. 15 is a timing chart for analog video signal output.

<Explanation of symbols for main parts of the drawings>

10: video line

12: switch

14: horizontal transfer register

22: amplifier

24: switch

26: data line

[Patent Document 1] Japanese Patent Laid-Open No. 2003-29725

The present invention relates to a digital analog conversion circuit using the capacity ratio of a capacitor.

Background Art Conventionally, flat panel type display devices such as liquid crystal display devices have been widely used. In particular, a small-sized, light-weight display device is essential for a portable device. For example, a liquid crystal display device is mainly used in mobile phones and the like.

In this liquid crystal display, in order to also display a high-definition image, an active matrix type having a pixel circuit for each display pixel and capable of high-definition display is used.

Here, in the liquid crystal display device, display is performed by applying a data voltage corresponding to luminance to liquid crystal. Therefore, the data signal supplied to each pixel is an analog signal. On the other hand, the video signal supplied to the liquid crystal display device is often preferably a digital video signal. In this case, the liquid crystal display device supplies an analog data signal to each pixel after digital-to-analog conversion.

In a digital-to-analog conversion circuit, the power supply voltage is divided by resistance to generate a voltage corresponding to the value of digital data. However, as the number of bits of digital data increases, the number of stages of the resistance increases and the voltage value of one stage decreases, making it difficult to maintain the accuracy. On the other hand, the capacitance ratio of the capacitor is set according to the weight of each bit of digital data, and the voltage according to "1" and "0" of each bit is set in each capacitor, and the corresponding voltage is obtained by the amount of charge obtained thereby. A digital analog conversion circuit is known which uses an output analog voltage.

The digital-to-analog conversion circuit using this capacity ratio can easily obtain a relatively small voltage. Therefore, it is thought that it is suitable for conversion of digital data with many bits by combining the digital-analog conversion circuit by resistance division and the digital-analog conversion circuit using a capacitance ratio.

Such digital analog conversion of data signals is described in, for example, Patent Document 1 and the like.

Here, in the digital analog conversion circuit using the above-mentioned capacity ratio, it is necessary to accurately charge each capacitor in order to increase the accuracy of the conversion. However, in the display device, it is often difficult to process the video signals sequentially transmitted in order, and it is difficult to charge the capacitor sufficiently accurately.

According to the present invention, a plurality of capacitors each formed in correspondence with each bit of digital data and whose capacitance value is determined according to the weight of each bit are different from each other, the amount of charges summed up with the charges charged in the plurality of capacitors, Output means for outputting an analog voltage determined according to a capacitance value of a sum of a plurality of capacitors, and a charge control transistor formed in a path of the digital data to the plurality of capacitors to control supply of a voltage of each bit to a capacitor The size of the charge control transistor is set corresponding to the capacitance of the capacitor to be connected.

In addition, one end of the plurality of capacitors is connected to a corresponding charge control transistor, the other end is commonly connected to a power supply, and the output unit short-circuits one end of the plurality of capacitors and outputs the analog voltage therefrom. It is desirable to.

In addition, one end of the plurality of capacitors is connected to a corresponding charge control transistor, and the output unit sets the same voltage at both ends of the plurality of capacitors, and then turns on the charge control transistor. Therefore, it is preferable to output the analog voltage from the other ends of the plurality of capacitors.

<Example>

EMBODIMENT OF THE INVENTION Hereinafter, the Example of this invention is described based on drawing.

`` Overall Configuration ''

1 is a diagram illustrating a configuration for supplying video data to a pixel circuit in a liquid crystal display device according to an embodiment.

In this embodiment, the 6-bit video line 10 sequentially transmits 64 gradation digital luminance signals for each pixel in accordance with the pixel clock. In addition, it actually has three video lines of R (red), G (green), and B (blue), and video data of each color is supplied in parallel and supplied to pixels of corresponding colors. It is showing the bay.

The input line of the switch 12 formed corresponding to each column of the pixel is connected to the video line 10. The output of the horizontal transfer register 14 is connected to the control terminal of this switch 12, respectively. Here, the horizontal transfer register 14 sequentially transmits the horizontal start signal STH by a pixel clock synchronized with the timing of each pixel of the video data supplied to the video line, and corresponds to each column of the pixels. Has registers to In this description, since the display of one type of color of RGB is described, the display bits and the pixels are the same. In addition, the transfer clock supplied to the horizontal transfer register usually uses two clock cycles CKH and XCKH whose phases are inverted and have twice the period of the pixel clock.

That is, when the video data of the pixels in the first column is supplied to the video line 10, the horizontal start signal STH is received in the first of the horizontal transfer registers 14, and the corresponding switch 12 is turned on. Then, the horizontal start (STH) signal is sequentially transmitted to the horizontal transfer register 14 by the pixel clock, so that the switch corresponding to the pixel (for the video data for each pixel supplied to the video line 10) ( 12 is sequentially turned on. In addition, the switch 12 is configured by connecting a p-channel transistor TFT and an n-channel transistor TFT in parallel, each of which is simultaneously connected by a non-inverting output and one inverting output of one register of the horizontal transfer register 14. On and off.

The input terminal of the 6-bit SRAM 16 is connected to the output terminal of each switch 12, and the input terminal of the 6-bit SRAM 18 is connected to the output terminal of these SRAM 16, respectively. Therefore, the video data for each pixel sequentially supplied to the video line 10 is received in the corresponding SRAM 16 by the switch 12 being turned on in order. When video data for one row (one horizontal scan line) is received in each of the SRAMs 16, one row of video data is simultaneously transferred to the corresponding SRAMs 18, respectively. Repeat every time. Thus, in each horizontal scanning period, one row of video data is received in the SRAM 16, which is then transferred to the SRAM 18, and the transferred video data is held in the SRAM 18 in the next horizontal scanning period. And output from here. This operation is repeated.

The input terminal of the digital-to-analog converter (DAC) 20 is connected to the output terminal of the SRAM 18. The DAC 20 converts 6-bit video data supplied from the SRAM 18 into a 64 gradation analog video signal. In addition, in order to perform so-called AC driving which changes the direction of applying the voltage to the liquid crystal at a predetermined cycle, the DAC 20 has two kinds of polarities (the direction of applying the voltage to the liquid crystal based on the common electrode potential of the liquid crystal element as a reference). Outputs a video signal of two polarities). As described later, in the present embodiment, since the dot inversion method is used as the AC driving method, in the pixels adjacent to each other in the horizontal and vertical directions, the direction (polarity) of the voltage applied to the liquid crystal is inverted and one pixel is used. The so-called liquid crystal is reversed every so-called frame.

In addition, an input terminal of an amplifier (Amp) 22 is connected to an output terminal of each DAC 20, and an output terminal of the amplifier 22 is connected to a data line DL through a switching switch 24. This data line DL extends in a column (vertical scanning direction) so that the pixel circuits 100 in one column are connected to each other. In this example, since the source of the pixel TFT in the pixel circuit 100 is connected to the data line DL, it is also called a source line.

Therefore, the analog video signal output from the DAC 20 is supplied to the data line DL, and the pixel circuit 100 of the corresponding row is taken in, whereby display according to the analog video signal received in each pixel is performed.

`` SRAM Configuration ''

In this embodiment, each column has two SRAMs 16 and 18 for holding 6-bit digital video data. In addition, the video data is set to have a relatively small dynamic range, and as data input to the DAC 20, there is a demand for increasing the dynamic range. Thus, for example, the level shifted from 5V amplitude to 8V amplitude.

In this embodiment, the latch circuit and the level shifter are combined to form the SRAM 16, and the level shift is also performed in the SRAM 16.

2 shows a configuration of a latch level shift circuit (SRAM 16) and a latch circuit (SRAM 18) for latching the output of the SRAM 16 according to the present embodiment. Here, the video data is 6 bits of digital data, and only one bit is shown.

Digital video data of 5V amplitude is supplied to the switch 610. The switch 610 is controlled by a clock synchronized with the dot clock to receive video data supplied to the input terminal for each display pixel (dot). For example, when the corresponding switch 12 of the video line 10 in FIG. 1 is on, the switch 610 is turned on to receive video data. In addition, the switch 610 may be employed as the switch 12.

The first latch 620 is connected to the output terminal of the switch 610. The first latch 620 has a 5V amplitude and is composed of two inverters 622 and 624 of 5V operation in which input and output are connected to each other. In this example, since the output from the switch 610 is supplied to the input side of the inverter 622, the inverted signal is input to the inverter 624. Therefore, the state of the input of the inverter 622 is determined according to the state of the output of the switch 610, and the state of the pair of output sides of the inverter 622 is also determined.

Here, in this example, it is preferable to increase the capability of the inverter 622 as compared with the inverter 624. As a result, even when the input video data is inverted, the output of the inverter 622 can be easily inverted to latch this data.

The pair of outputs of the first latch 620 (polarity opposite) are input to the voltage shift type level shifter 630. The level shifter 630 has a configuration in which two series connections of three transistors arranged between 8 V VDD and 0 V VSS are arranged in parallel.

Between VDD and VSS, the p-channel TFT 632a, the p-channel TFT 634a, and the n-channel TFT 636a are connected in series, and the p-channel TFT 632b, the p-channel TFT 634b, and the n-channel TFT are provided. The serial connection of 636b is arrange | positioned. The output of the switch 610 latched by the latch circuit 620 is supplied to the gates of the TFTs 634a and 636a, and the latch circuits 620 are supplied to the gates of the TFTs 634b and TFT 636b. Inverted signal of the output of the switch 610 latched in the (). The gate of the TFT 632a is connected to the midpoint of the TFT 634b and the TFT 636b, and the gate of the TFT 632b is connected to the midpoint of the TFT 634a and the TFT 636a.

With such a configuration, depending on the output of the latch 620, the gate of the TFT 632a is the midpoint of the TFT 634b and the n-channel TFT 636b, and the gate of the TFT 632b is the TFT 634a and n. One of the midpoints of the channel TFT 636a is at the H level and the other is at the L level. For example, when the output of the switch 610 is H level ("1"), the midpoints of the TFT 634b and the n-channel TFT 636b are the H-level, the TFT 634a and the n-channel TFT 636a. The midpoint becomes L level.

Outputs from the midpoint of the TFT 634b and the n-channel TFT 636b and the midpoint of the TFT 634a and the n-channel TFT 636a are input to the second latch 640. The second latch 640 is configured by connecting an inverter 642 and an inverter 644, and an output of an intermediate point of the TFT 634b and the n-channel TFT 636b is input to an input of the inverter 642. The output of the midpoints of the TFT 634a and the TFT 636a is input to the input of the inverter 644, and the output of the inverter 642 (the input of the inverter 644) is the output of the second latch 640. It is.

Accordingly, the data input to the switch 610 is latched by the first latch 620, and the signal level-shifted by the level shifter 630 and the signal shifted by the level-shifted and inverted are 8 V into the second latch 640. It is latched as a signal. In addition, the first latch 620, the level shifter 630, and the second latch 640 constitute the SRAM 16. Therefore, at the output of the SRAM 16, a signal obtained by level shifting the 5V amplitude to the 8V amplitude is obtained. Thus, by forming the latch circuits on the input side and the output side of the level shifter 630, the latch operation and the level shift operation can be performed simultaneously. Therefore, power consumption can be made small compared with the case where these are performed separately.

The output of the second latch 640 is inverted by the inverter 650. In contrast to the configuration of FIG. 1, up to this inverter 650 corresponds to the SRAM 16, whereby the input video data is stored in accordance with the dot clock and is level shifted and output.

The output of the inverter 650 is supplied to the latch 670 via the switch 660. The switch 660 opens only a predetermined period after data for one horizontal scan line is received by the SRAM 16. The latch 670 is composed of an inverter 672 and an inverter 674 connected to each other. The output of the switch 660 is input to the inverter 672, and the output of the latch 670 is connected to the latch 670. It is an output. The output of the latch 670 is inverted and output from the inverter 680. Thus, latch 670 and inverter 680 constitute SRAM 18. That is, in the step where video data of each pixel is stored in each SRAM 16 in one horizontal scanning line, the switch 660 is opened, and the video data at this time is set in the SRAM 18. For example, in the horizontal retrace period, data of all the SRAMs 16 are collectively transferred to the SRAMs 18.

In this manner, according to the present embodiment, the SRAM 16 can also perform a level shift when storing data. For this reason, efficient operation can be achieved.

"Configuration of High Bit Conversion of DAC 20"

3 illustrates the configuration of higher bit conversion of the DAC 20. The reference voltage generator circuit 300 has two of the reference voltage amplifiers 300a and 300b. The reference voltage amplifiers 300a and 300b respectively divide the power supply voltages VCC and GND into ten resistors of resistors R0 to R9 to generate nine reference voltages of v0 to v8. The reference voltage amplifiers 300a and 300b alternately operate every one horizontal scanning period. Therefore, the nine reference voltages v0 to v8 are inverted in polarity every one horizontal period. That is, when the reference amplifier 300a is operating, when v8 is close to VCC and v0 is close to GND, and the reference amplifier 300b is operating, the reverse is reversed. In addition, switching of the reference amplifiers 300a and 300b for each horizontal period is performed by the signal FRP. For example, the reference amplifier 300a operates when the signal FRP is at H level, and the reference amplifier 300b operates when at the L level.

The data D5-D3 are input to four decoders of the upper H-side decoder 310, the upper L-side decoder 312, the lower H-side decoder 314, and the lower L-side decoder 316. Reference voltages v0 to v8 are also supplied to 316 respectively. The upper H side decoder 310 selects and outputs the reference voltages v8 to v1 according to eight types of data D5-D3 of 111 to 000, and the upper L side decoder 312 indicates that data D5-D3 is 111. According to eight types of ˜000, reference voltages v7 to v0 are selected and output. Therefore, the output VH of the upper H-side decoder 310 is a voltage one step higher than the output VL of the upper L-side decoder 312 (when v8 is the VCC side). On the other hand, the lower H-side decoder 314 selects and outputs the reference voltages v0 to v7 in accordance with eight types of data D5-D3 of 111 to 000, and the lower L-side decoder 316 outputs the data D5-D3. According to eight types of 111 to 000, the reference voltages v1 to v8 are selected and output. Therefore, the output VH of the lower H-side decoder 314 is a voltage one step lower than the output VL of the lower L-side decoder 316 (when v8 is the VCC side).

In this way, the upper decoders 310 and 312 output the output voltages VH and VL which are shifted by the voltage corresponding to the bit of D3. The lower decoders 314 and 316 are different from the upper decoders 310 and 312 in a direction in which VH and VL, which are output analog signals, are increased with respect to a change direction such as a direction in which the input digital data increases or decreases. The direction in which the direction of application becomes smaller is inverted), but the lower H-side decoder 314 and the lower L-side decoder 316 output voltages VH and VL different from each other by one bit of D3. Do.

When the outputs of the upper decoders 310 and 312 are supplied to the odd-numbered data lines DL, the outputs of the lower decoders 314 and 316 are supplied to the even-numbered data lines DL.

In this way, in the upper decoders 310 and 312 and the lower decoders 314 and 316, the supply of the reference voltage is reversed, so that the upper side and the lower side of the panel using one reference voltage generating circuit 300. Digital-to-analog conversion can be performed at both decoders. Therefore, by alternately supplying the outputs of the upper decoders 310 and 312 and the lower decoders 314 and 316 to the data lines DL, the polarity of the video signal can be inverted for each data line DL. Further, by using the reference voltage amplifiers 300a and 300b alternately for each horizontal line, the polarity of the video signal supplied to each data line DL can be changed for each horizontal scanning line. Thus, dot inversion driving in the liquid crystal display device can be achieved. In the case of performing such a drive, since the reference voltage generating circuit 300 can be set to one, the circuit can be simplified and the power consumption can be reduced.

Lower Bit Conversion of DAC 20 and Amplifier 22 Configuration

As described above, when VH and VL are obtained from the upper three bits D5-D3, eight kinds of voltages corresponding to D2-D0 are obtained for the voltages of the differences between VH and VL. In Fig. 4 a configuration for this is shown. D2 is inputted as it is into the gate of the TFT 410-2, and is inverted into the gate of the TFT 412-2. VH is supplied to one end of the TFT 410-2, and VL is supplied to one end of the TFT 412-2. The other end of the TFTs 410-2 and 412-2 is connected to one end of the capacitor 430-2 via the charge control TFT 420-2. The other end of the capacitor 430-2 is connected to ground.

Therefore, when D2 is at the H level ("1"), the TFT 410-2 is turned on and VH is selected. When the charge control TFT 420-2 is on, the capacitor 430-2 is charged to VH. On the other hand, when D2 is L level ("0"), the capacitor 430 is charged to VL.

Also in D1 and D0, the structure similar to D2 is provided basically. Accordingly, VH or VL is charged in the corresponding capacitors 430-1 and 430-0 according to the values of D1 and D0.

In addition, a charge control TFT 420-r is formed, and this charge control TFT 420-r charges the VL directly to the corresponding capacitor 430-r regardless of data. The charge control TFTs 420-r, 420-0, 420-1, and 420-2 are turned on and off by the signal Charge.

The capacitors 430-r, 430-0, 430-1, and 430-2 have capacitance values set such as C, C, 2C, and 4C. In addition, C is 0.5 pF, for example, and 4C will be 2 pF in this case.

In addition, the upper ends of the capacitors 430r, 430-0, 430-1, and 430-2 are connected by three coupling TFTs 440-1, 440-2, and 440-3, and the capacitors 430- The upper end of r) is an output end via the TFT 440-r.

The signal Combine is supplied to the gates of the coupling TFTs 440-1, 440-2, 440-3, and TFT440-r.

By such a circuit, when D2-D0 is all "0", the capacitors 430-2, 430-1, 430-0, 430-r are all charged by VL. Therefore, the output voltage becomes VL. Here, VL is a value selected by D5-D3 as described above, and is a voltage specified by D5-D0.

If D0 is &quot; 1 &quot;, the charge of (VH-VL) · C is extra charged, and the voltage 1 / 8C is added to VL to output VL + (VH-VL) / 8. When D2 is &quot; 1 &quot;, the charges of (VH-VL) and 4C are extra charged, and the voltage 1 / 8C is added to VL to output VL + 4 (VH-VL) / 8. And if all of D0, D1, and D2 are "1", VL + 7 (VH-VL) / 8 is output. Therefore, according to the value of D0-D3, the voltage in units of (VH-VL) is added to VL, and the voltage according to the value of D5-D0 is obtained at the output.

In addition, the voltage obtained at this output is a voltage between VCC and GND, and the polarity is inverted at the upper side and the lower side (odd and even columns) of the panel, and the polarity is inverted every one horizontal period.

Here, in the embodiment, the sizes of the charge control TFTs 420-r, 420-0, 420-1, and 420-2 are set to 1: 1: 2: 4. That is, the capacitors 430-r, 430-0, 430-1, and 430-2 charged by the charge control TFTs 420-r, 420-0, 420-1, and 420-2 have a capacity value of 1. The amount of current flowing through the charge control TFTs 420-r, 420-0, 420-1, and 420-2 also corresponds to this ratio. Therefore, by setting the sizes of the charge control TFTs 420-r, 420-0, 420-1, and 420-2 to 1: 1: 2: 4 as in this embodiment, the corresponding capacitors 430-r and 430 The amount of charge charges to -0, 430-1, and 430-2 can be accurately set to the capacitance value x voltage value, and the output voltage can be made accurate. In addition, the change in voltage due to the MOS capacitance of the transistor (charge control TFT) can be made equal.

"Configuration of amplifier 22"

The structural example 1 of the amplifier 22 is demonstrated based on FIG. This amplifier 22 has a structure for output correction. The output from the coupling TFT 440-r is input to the buffer amplifier 452 through the switch TFT 450 turned on and off by the signal φ01. On the other hand, one end of the correction capacitor 454 is connected to the input terminal of the buffer amplifier 452, and the other end of the correction capacitor 454 is connected to the ground GND through the voltage drop control capacitor 456.

In addition, the voltage VL is supplied to the input terminal of the buffer amplifier 452 through the TFT 460 turned on and off by the charging signal Charge. Further, at the midpoint of the capacitors 454 and 456, the voltage VL is supplied by the TFT 462 turned on and off by the charging signal Charge, and the switch TFT 450 by the TFT 470 turned on and off by the signal φ 03. ) Input side (output terminal of the DAC) is connected, and the output terminal of the buffer amplifier 452 is connected via the TFT 472.

The operation of such a circuit will be described based on FIGS. 5A and 5B. First, the TFTs 460 and 462 are turned on by the signal charge, so that the midpoints of the input terminal of the buffer amplifier 452 and the capacitors 454 and 456 are set to the voltage VL. In this state, the capacitors 430-r, 430-0, 430-1, and 430-2 are charged as described above, the amount of charge is determined, the charge is lowered, and then the Combine is raised, and the DAC The analog voltage Vin according to the input data appears at the output terminal of (20).

In step 1, the signal? 01 becomes H level while the Combine is H level, and the switch TFT 450 is turned on. As a result, the input terminal of the buffer amplifier 452 is set to the output voltage Vin of the DAC 20.

Next, in step 2, the TFT 472 is turned on by setting the signal? 02 to the H level. As a result, the midpoints of the capacitors 454 and 456 are set to the output voltage Vout of the buffer amplifier 452. In addition, the buffer amplifier 452 operates so that the output voltage matches the input voltage, but an error occurs due to its characteristics, and this embodiment compensates for this. If the error voltage in the buffer amplifier 452 is ΔV, the output voltage Vout = Vin + ΔV can be expressed.

In step 3, the signal? 02 is returned to the L level. As a result, the input terminal side (upper side) of the buffer amplifier 452 of the capacitor 454 is fixed at Vin, and the capacitor 456 side (lower side) is fixed at Vout, and the capacitor 454 is charged with ΔV.

In step 4, the switch TFT 450 is turned off with the signal? 01 at the L level. In this case, when the switch TFT 450 is turned off, the gate potential goes from the H level to the L level, and due to the gate capacitance Cgs of the switch TFT 450, the voltage at the input terminal of the buffer amplifier 452 is reduced. Slightly down Here, the capacitor 454 is charged by ΔV, and the capacitor 456 is charged by Vout-GND. Therefore, the midpoint voltages of these capacitors 454 and 456 and the input terminal voltage of the buffer amplifier 452 cannot move as much as that. When the voltage lowered at the input terminal of the buffer amplifier 452 by turning off the switch TFT 450 is a, the voltage at the input terminal of the buffer amplifier 452 becomes Vin-a. In addition, the voltage at the midpoint of the capacitors 454 and 456 is lower than a, but decreases according to a. When the decrease in the voltage at the midpoint of the capacitors 454 and 456 is a ', the voltage there is Vin + ΔV-a'.

In step 5, the signal? 03 is set to the H level, and the midpoint voltages of the capacitors 454 and 456 are set to Vin. As a result, the midpoint voltages of the capacitors 454 and 456 are changed by Vin − (Vin + ΔV − a ′). Therefore, the input voltage of the buffer amplifier 452 is also changed by the same amount, and becomes Vin-a + Vin-Vin-ΔV + a ', resulting in Vin-ΔV- (a-a'). Although depending on the setting of the capacitance values of the capacitors 454 and 456, a and a 'are originally close values, and it is easy to make them almost the same. Assuming a = a ', the input voltage of the buffer amplifier 452 is approximately Vin-ΔV. For this reason, when Vin is inputted, the output of the buffer amplifier 452 whose Vout = Vin + ΔV is lowered by ΔV, whereby Vout ≒ Vin, and the error is compensated for.

"Another structural example of the amplifier 22"

FIG. 6 shows another circuit example for solving the output error of the buffer amplifier 452 in the amplifier 22. As shown in FIG.

In this example, the output of the DAC 20 is supplied to the input terminal of the buffer amplifier 452 as it is, and the switch TFT 480 which connects the output and input of the buffer amplifier 452 is formed.

The switch TFT 480 is turned on by setting the signal φ to H level after outputting a corresponding voltage from the buffer amplifier 452 for a predetermined time with the signal Combine as H. Thereby, the voltage on the output side of the buffer amplifier 452 can be made close to the voltage on the input side, and the error in the output of the buffer amplifier 452 can be made small.

As shown in Fig. 6, a capacitor of the DAC 20 is connected to the input side of the buffer amplifier 452, which is an input unit capacitance. On the other hand, since the output of the buffer amplifier 452 is connected to the data line DL, the capacity for this data line DL exists as a load capacity. It is effective to turn on the switch TFT 480 after the end of sufficient charging with respect to the load capacity. And when (load capacitance) / (input capacitance) which is the ratio of load capacitance and input part capacitance is 1 or less, the effect by the ON of switch TFT 480 is large, and it is preferable. The gate capacitance CS of the switch TFT 480 is preferably smaller than the input portion capacitance and the load capacitance, and preferably 1/10 or less with respect to both capacitances.

"Other Configurations Regarding Lower Bits of the DAC 20"

In Fig. 7, another example of the configuration of the lower bits of the DAC 20 is shown. In this example, instead of the signal Combine, Pre-Charge is used.

In response to D2-D0, TFTs 410-2, 412-2, 410-1, 412-1, 410-0, 412-0 are formed, respectively, and either VH or VL is selected, respectively, and these are charge control. The transistors 420-2, 420-1, and 420-0 are supplied to one end (upper side) of the capacitors 430-2, 430-1, and 430-0. In addition, VL is directly supplied to the capacitor 430-r so that one end (upper side) is always set to VL.

The other end side (lower side) of the capacitors 430-2, 430-1, 430-0, and 430-r is connected in common and serves as an output of the DAC 20.

And serial connection of the TFTs 510-2 and 512-2 between both ends of the capacitor 430-2, serial connection of the TFTs 510-1 and 512-1 between both ends of the capacitor 430-1, A series connection of the TFTs 510-0 and 512-0 is connected between both ends of the capacitor 430-0, and a series connection of the TFTs 510-r and 512-r is disposed between both ends of the capacitor 430-r. have. Then, the serial connection of the TFTs 510-2 and 512-2, the serial connection of the TFTs 510-1 and 512-1, the serial connection of the TFTs 510-0 and 512-0, and the TFT 510-r VL is all supplied to the intermediate point of the series connection of 512-r), and the signal Pre-Charge is supplied to the gate of these TFT all.

In such a circuit, by first setting the signal Pre-Charge to H level, both ends of all capacitors 430-2, 430-1, 430-0, 430-r are set to VL.

Then, after setting the signal Pre-Charge to L level, the charge control TFTs 420-2, 420-1, and 420-0 are turned on, and the capacitors 430- corresponding to VH or VL according to the data D2-D0 are turned on. 2, 430-1, 430-0). As a result, the other ends of the capacitors 430-2, 430-1, and 430-0 supplied with the VH attempt to shift, but the amount of charge of each capacitor at that time is the capacitors 430-2, 430-1, and 430-0. Since it is proportional to the capacitance value of), similarly to the case described above, the voltage at the output terminal is a voltage shifted from the VL to the VH direction by a minute corresponding to the value determined by D2-D0.

Also in this configuration, the charge control TFTs 420-2, 420-1, 420-0 are transistor sizes corresponding to the capacity ratios of the capacitors 430-2, 430-1, 430-0.

`` Switch switch 24 ''

The structure of the switching switch 24 is shown in FIG. This switching switch 24 has the 1st switching part 24a and the 2nd switching part 24b, and these are the two standby signals of a WHITE signal and a BLACK signal, and are outputs of the DAC 20. One of the video signals for normal display of 64 gradations is selected and output.

First, the first switching unit 24a can switch with a mode signal indicating whether it is a normal mode or a standby mode (low power mode), and selects and outputs a video signal for normal display in the normal mode. .

On the other hand, in the standby mode, the standby signal is selected by the first switching unit 24a. The output of the second switching unit 24b is supplied to the input terminal of the standby signal of the first switching unit 24a. The second switching section 24b selects and outputs either a WHITE signal or a BLACK signal. Therefore, in the standby mode, either the WHITE signal or the BLACK signal selected by the second switching unit 24b is output through the first switching unit 24a.

Here, the second switching unit 24b is supplied with a signal of the MSB (the fifth bit of 0-5 bits) at the 6-bit output of the SRAM 18. This is because, in the standby mode, the display is a display such as a simple symbol, and two types of display, white and black, are used, and either white or black is determined by the fifth bit of the video data. For example, if black is 000000 and white is 111111, the determination can be made using any bit. However, the video data may not use all the range data, and may be determined as an appropriate bit. That is, for each pixel, whether the data of the pixel is white or black is determined by the appropriate 1 bit in the pixel data, and by this, either the WHITE signal or the BLACK signal is selected by the second switching unit 24b. In this example, a predetermined bit of the SRAM 18 is used as a switching control signal, and is supplied to the first switching unit 24a, and the first switching unit 24a is switched by 1 or 0 of the bit. .

In this way, in the normal display mode, the normal video signal from the DAC 20 is supplied to the data line DL, and in the standby mode, either the WHITE signal or the BLACK signal is supplied to the data line DL. .

In addition, even in a full-color display device having pixels of RGB colors, the display itself becomes white by supplying high luminance signals to all the pixels, and black display by supplying low luminance signals to all the pixels. In addition, since each color pixel of RGB can be turned on and off, eight colors of R, G, B, R + G, R + B, G + B, white, and black are also possible.

In the standby mode, a multi-gradation video signal for display is normally unnecessary. Therefore, in the present embodiment, by separately selecting the WHITE signal or BLACK signal prepared by digital video data, the operation of the DAC 20 and the amplifier 22 is stopped and consumed without using an analog video signal. Reduce power In addition, for the amplifier 22, it is preferable to turn off the power supply, and also for the DAC, it is preferable to turn off the power supply of the amplifier that generates the reference voltage. As described above, in the standby mode, processing of the analog signal becomes unnecessary, so that power saving can be achieved by completely stopping the operation of the analog circuit.

Here, in the liquid crystal, so-called AC driving is performed in which the direction of applying the voltage to the liquid crystal is reversed every predetermined period for the purpose of burning out or the like. Therefore, when using a normally black liquid crystal (black display when no voltage is applied), the BLACK signal is set to a constant voltage similar to the supply electrode voltage, and the WHITE signal is set to a voltage away from the common electrode every predetermined time. When a white liquid crystal is normally used (when no voltage is applied), the signal is reversed.

Here, in the case of normally white, as shown in Fig. 9, the WHITE signal is a signal of 1/2 VDD, and the BLACK signal alternately repeats VSS and VDD every one horizontal scan. It is applied to the pixel electrode of this liquid crystal element. In addition, the voltage VCOM of the common electrode is set to almost the same voltage as the WHITE signal. As a result, the polarity (whether the voltage is larger or smaller than VCOM) of the video signal supplied to the pixel of black display is reversed for each row of pixels. In the next frame, since the polarity of the video signal for the corresponding row is inverted, the direction of applying the voltage to the liquid crystal is inverted for each pixel for the pixel which continues one black display.

In particular, the dot inversion system which inverts the direction of the voltage applied to liquid crystal for every dot among the above-mentioned one line is preferable.

"Specific circuit configuration of the switch 24"

10 shows a specific circuit configuration of the switch 24. The BLACK signal LP_BLACK is supplied to one end (drain or source) of the TFT 210, and the other end (source or drain) of the n-channel TFT 210 is connected to one end (source) of the p-channel TFT 212. Or drain) is connected, and a WHITE signal WHITE is supplied to the other end (drain or source) of the TFT 210 of this X-channel. The fifth bit D5 of the video data is supplied to the gates of the TFTs 210 and 212. Therefore, the TFT 210 is turned on when D5 is "1", and the TFT 212 is turned on when D5 is "0".

One end of the n-channel TFT 214 is connected to the connection point of the TFT 210 and the TFT 212, and the other end of the TFT 214 is connected to the data line DL. The LP_ENB signal which becomes H level in the standby mode is supplied to the gate of the TFT 214. Thus, in the standby mode, the TFT 214 is turned on so that either the BLACK signal or the WHITE signal is supplied to the data line DL.

The 64 gradation analog video signal supplied from the DAC 20 through the amplifier 22 is supplied to one end of the n-channel TFT 216, and the other end of the TFT 216 is connected to the data line DL. have. The RGB_ENB signal set to H level in the normal display mode is supplied to the gate of the TFT 216. Therefore, in the normal display mode, the TFT 216 is turned on, and the 64 gradation video signal is supplied to the data line DL.

In this manner, either the WHITE signal or the BLACK signal is selected by the video data D5, and either the video signal or the WHITE signal or the BLACK signal is selected by the LP_ENB signal and the RGB_ENB signal and supplied to the data line DL. do.

`` Constitution of precharge ''

10 shows a configuration for precharging the data line DL. In other words, an n-channel TFT 230 is disposed between each data line DL, and adjacent data lines DL are connected by turning on the TFT 230. This TFT 230 is disposed between all data lines DL. Further, an n-channel TFT 232 is disposed between the line for supplying the WHITE signal and each data line DL, and the WHITE signal is supplied to the data line DL by turning on the TFT 232.

The DSG signal is supplied to the gates of the two TFTs 230 and the TFTs 232. Therefore, by setting the signal DSG to the H level, both of the TFTs 230 and 232 are turned on, adjacent data lines DL are connected, and a WHITE signal is supplied thereto.

Here, this WHITE signal is a signal of (1/2) VDD as shown in FIG. Therefore, in the horizontal retrace period, by setting the DSG signal to the H level, each data line DL can be precharged to (1/2) VDD. The precharge is performed before setting data in one horizontal scanning period such as the horizontal retrace period to the data line DL.

In particular, in the dot inversion method in which the polarity of data to be described later is inverted between adjacent pixels (dots), the voltage value of the video signal set in the adjacent data line DL is in the opposite direction on the basis of the common electrode voltage VCOM. It is. Thus, by turning on the TFT 230 and connecting adjacent data lines DL to each other, the voltage is close to the common electrode voltage VCOM. That is, in display such as naturalization, the luminance of adjacent pixels is often close, and therefore, by connecting the data lines DL which are set to the voltages for display of the adjacent pixels, a voltage close to VCOM without supplying power from the outside. Can be set. For example, in full screen black display, the data lines DL are alternately set to VSS and VDD, and by connecting them, efficient precharge can be performed.

In the present embodiment, the TFT 232 is formed and set to (1/2) VDD for each data line DL. As a result, the power (charge amount) required for writing the video signal to the data line DL afterwards can be reduced, and power saving can be achieved.

In the example of FIG. 10, the TFTs 230 and 232 are turned on and off by the DSG signal of one control line, and the TFTs 230 and 232 are turned on at the same timing. After turning on, it is also preferable to turn on the TFT 232. The voltage supplied by the TFT 232 is set to (1/2) VDD. However, another voltage may be used as long as the voltage is close to the common electrode voltage VCOM.

In the case where the TFT 230 is formed, the TFT 232 can be omitted. That is, by turning on the TFT 230, adjacent data lines DL can be connected via the TFT 230, and the same effect is obtained. In addition, only one of the TFT 230 and the TFT 232 may be formed.

`` Pixel Circuit and Dot Inversion ''

Here, a form in which two capacitor lines are formed for one row and the voltages of these two capacitor lines are inverted for each frame with opposite polarity is preferable. This configuration will be described below.

Fig. 11 shows a schematic configuration of the configuration of the pixel circuit which forms two capacitor lines. The pixel circuit 1 is arranged in a matrix throughout the display area. The matrix arrangement may be zigzag instead of a perfect lattice. In addition, the display may be monochrome or full color. In the case of full color, the pixels are usually three colors of RGB, but it is also preferable to add pixels of a specific color including a bag as necessary.

As shown in the figure, one pixel circuit 1 includes an n-channel pixel TFT 110 whose source is connected to the data line DL, and a liquid crystal element 112 connected to the drain of the pixel TFT 110. And a storage capacity 114. The gate line GL arranged for each horizontal scanning line is connected to the gate of the pixel TFT 110.

In the liquid crystal element 112, a pixel electrode formed separately for each pixel is connected to a drain of the pixel TFT 110, and a common electrode of all the pixels common to the pixel electrode is disposed with the liquid crystal sandwiched therebetween. Consists of. In addition, the common electrode is connected to the common electrode power supply VCOM.

In addition, the storage capacitor 114 has a portion in which the semiconductor layer constituting the drain of the pixel TFT 110 extends as one electrode, and a part of the capacitor line SC formed to face each other via the oxide film is an opposite electrode. . The portion serving as the electrode of the storage capacitor 114 may be separated from the portion of the pixel TFT 110 to be another semiconductor layer, and both may be connected by metal wiring.

Here, there are two capacitor lines SC, SC-A and SC-B, for one row (horizontal scan line), and in the horizontal scanning direction, the storage capacitance of each pixel circuit is set to SC-A and SC-B. It is connected alternately. In the pixel circuit shown in this figure, the storage capacitor 114 is connected to the capacitor line SC-A, and the storage capacitor 114 of the neighboring pixels is connected to the capacitor line SC-B.

The vertical driver 120 is connected to the gate line GL, and the vertical driver 120 sequentially selects one gate line GL every one horizontal time and sets it to H level. The vertical driver 120 has a shift register, receives a signal STV indicating the start of one vertical scanning period, sets the first stage of the shift register to H level, and then sets the H level to 1 by, for example, a clock signal. By shifting one by one, one gate line GL of each horizontal scanning line is sequentially selected to be at the H level. Here, for example, the H level of the gate line GL is the VDD potential, the L level is the VSS potential, and these power supply voltages VDD and VSS are supplied to the vertical driver 120, whereby the gate line which is the output of the vertical driver. H level and L level of GL are set.

The SC driver 122 outputs two voltage levels to two storage capacitor lines SC-A and SC-B.

Although not shown, a horizontal driver is also formed in the display device, for example, and the supply of the line sequence to the data line DL of the input video signal is controlled. In other words, in this example, the horizontal driver outputs a sampling clock for each pixel in accordance with the clock of the video signal for each pixel, and the sampling clock turns the switch on and off to provide a video signal for one horizontal scan line (data signal). Latch). Then, the data signal for each pixel of the latched one horizontal scanning line is output to the data line DL over one horizontal scanning period.

In reality, there are three types of video signals in RGB, and each pixel in the vertical direction is a pixel of any one of R, G, and B colors. Therefore, a data signal of any one color of RGB is set in the data line DL.

In the apparatus of this embodiment, the AC application method of the dot inversion method is adopted. That is, in each pixel (dot) in the horizontal scanning direction, the voltage applied to the pixel electrode of the liquid crystal element 112 is applied as a data signal whose polarity is opposite to the voltage VCOM of the common electrode.

The left side of Fig. 12 is a data signal having a first polarity, and a quadrilateral of triangle written in Vvideo represents a data signal (write voltage) corresponding to luminance. The data signal is a potential difference (dynamic range) of Vb from the black level to the white level, and the voltage applied to the pixel electrode after the voltage shift is white with the voltage farthest from VCOM and black near the black. . Therefore, in this example, the black level is VCOM-Vb / 2, and the back level is VCOM + Vb / 2. In the adjacent pixel, as shown on the right side of FIG. 12, the second polarity is opposite to the first polarity, and the black level is VCOM + Vb / 2 and the back level is VCOM-Vb / 2. .

As shown in FIG. 13, after the on period to the pixel TFT 110 ends and data writing is completed, the capacitor lines SC-A and SC-B are shifted by a predetermined voltage ΔVsc. In this example, a normally black vertical alignment (VA) type thing is used as the liquid crystal. The capacitor line SC-A is connected to the pixel on the left side of FIG. 12, and Vsc shifts the voltage in the high direction by ΔVsc. The capacitor line SC-B is connected to the pixel on the right side of FIG. 12, and Vsc shifts the voltage in the lower direction by ΔVsc.

Thereby, as shown in FIG. 13, the data signal applied to the pixel electrode is shifted by the voltage according to (DELTA) Vsc, and this is applied between VCOM. Here, ΔVsc is set to a voltage corresponding to the threshold voltage Vath at which the change in transmittance according to the applied voltage of the liquid crystal is started, and the display by the liquid crystal element 112 is enabled by the voltage after the shift. In addition, the dynamic range of the data signal is set so that the dynamic range after the shift becomes the potential difference between the black level in the display and the back level.

In Fig. 12, Va (W) is the shift amount of the data signal at the back level, Va (B) is the shift amount of the data signal at the black level, and these shift amounts are determined by ΔVsc. Vb is the potential difference (dynamic range) between the black level and the white level of the data signal, and Vb 'is the dynamic range after the shift.

`` All operations ''

The acquisition operation of the video data into the SRAMs 16 and 18 in FIG. 1 will be described based on the timing chart of FIG. 14. One horizontal scanning period consists of a data period in which video data is supplied to the video line 10 (FIG. 1), and a horizontal retrace period (blanking period). By the horizontal synchronization signal Hsync, synchronization with respect to the horizontal scanning period is obtained. Dot Clock Dotclock is a signal synchronized with one dot of video data, and the horizontal start signal STH is a horizontal transfer register 14 using XCKH (and CKH), which is a horizontal transfer clock of this frequency, as the horizontal transfer clock. (FIG. 1). In addition, by the enable signal ENB, the STH is transferred from the horizontal transfer register 14 only during the period in which video data is supplied.

STH is transmitted to the first stage of the horizontal transfer register 14 as shown by SR01 in FIG. 14, and then sequentially transferred in the same manner as in SR02 and SR03. In this example, the acquisition of the video data ends at 130. Here, the acquisition of video data into the SRAM 16 (FIG. 1) is performed by AND01a to AND130a. Here, AND01a is a signal that becomes H level in the second half of SR01 obtained by AND (logical product) of SR01 and SR01a (same signal as SR02), and corresponds to the first dot video data of the video data. Accordingly, the AND01a receives the first dot video data into the SRAM 16 of the first stage. By AND01a to AND130a, one row of video data is received in the corresponding SRAM 16. FIG.

In this example, the number of stages of the horizontal transfer register 14 is set to 133, and the SR 133 transfers one row of video data received by the SRAM 16 to the SRAM 18.

Next, the write operation from the DAC 20 to the pixel circuit 100 will be described based on the timing chart of FIG. 15.

First, when the blanking period ends, video data for one row is set in the SRAM 18 as described above. Thus, the DAC 20 performs digital analog conversion but must charge the capacitor 430 for the lower 3 bits. Therefore, the charge is set to H level to start charging. After charging is completed, charge is set to L level and signal Combine is set to H level. As a result, an analog video signal of 64 gradations is obtained at the output of the DAC 20.

In addition, in the period in which the analog signal is output from the DAC 20, the output correction processing of the amplifier 22 is performed as described above. Here, timings of the signals? 01 to? 03 used in the configuration of Fig. 4 are shown, but this is the same as that shown in Fig. 5A.

In addition, the signal phi supplied to the gate of the switch TFT 480 in FIG. 6 becomes H level at the same timing as φ3.

On the other hand, in the switch 24, the RGB video signal, which is the output of the amplifier 22, is supplied to the data line DL by combining RGB_ENB with the H level during the H level period. Accept that analog video signal. In addition, the RGB_ENB returns to the L level prior to Combine, thereby preventing the video signal on the data line DL from changing.

The gate line GL becomes H level in the data period, and in each pixel circuit 100, at the end of the period in which RGB_ENB is H level, the gate line GL becomes H level, and the data voltage in the pixel circuit 100 becomes high. It is confirmed.

On the other hand, in the blanking period, the signal DSG becomes H level, and each data line DL is precharged to (1/2) VDD. Further, in the blanking period, since the FRP is inverted, the polarity of the reference voltage in the DAC 20 is inverted, and the polarity of the analog video data is inverted.

According to the present invention, the transistor size of the charge control transistor is determined according to the capacity of the corresponding capacitor. For example, the transistor sizes are 1, 2, and 4 in the 1st, 2nd, and 3rd bits from the LSB side. This makes it possible to provide a sufficient charge (current) supply capability to the capacitor in each bit, and to perform more accurate digital-to-analog conversion. In addition, the change in voltage due to the MOS capacitance of the charge control transistor can be made equal.

Claims (3)

A plurality of capacitors formed corresponding to the respective bits of the digital data, the capacitance values of which are different from each other in the capacitance value determined according to the weight of each bit; Output means for outputting an amount of charge in which the charges charged in the plurality of capacitors are summed, and an analog voltage determined according to the capacitance value of the sum of the plurality of capacitors; Charge control transistors formed in the path of the digital data to the plurality of capacitors to control the supply of the voltage of each bit to the capacitor Has, The transistor size of the charge control transistor is set in correspondence with the capacitance value of the capacitor to be connected. The method of claim 1, One end of the plurality of capacitors is connected to a corresponding charge control transistor, and the other end is commonly connected to a power source. And said output means short-circuits one end side of said plurality of capacitors and outputs said analog voltage therefrom. The method of claim 1, The plurality of capacitors are connected at one end to corresponding charge control transistors, The output means sets the same voltage across the plurality of capacitors, and then turns on the charge control transistor, Thereby, the analog-to-analog converter circuit outputs the analog voltage from the other ends of the plurality of capacitors.

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