JP2008065244A - Driving circuit and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit capable of performing high-speed operation and suppressing increase of circuit scale and increase of power consumption, and to provide a display device comprising the driving circuit. <P>SOLUTION: A digital analog converter (DAC) 137 comprises a high gradation DAC and a low gradation DAC connected to output of the high gradation DAC, the high gradation DAC is separated into a positive polarity side DAC 1371RP and a negative polarity side DAC 1371RN, the low gradation DAC 1372 is shared by positive polarity and negative polarity, and neighboring output terminals have the same polarity. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a drive circuit as a data driver applicable to a projection type liquid crystal display device and the like, and an active matrix display device.

  In a projection display device such as a liquid crystal projector, light emitted from a light source is separated into red, green, and blue, and each color light is modulated by three light valves composed of liquid crystal display elements (hereinafter referred to as LCD). The modulated color light fluxes are synthesized again and enlarged and projected onto the projection surface.

  As a micro display (light valve) mounted on a liquid crystal projector or the like, an active matrix drive type LCD driven by a thin film transistor (hereinafter referred to as TFT) is generally used.

  Since the micro display used in the projection type liquid crystal display device has a pixel pitch as narrow as about 10 μm, the connection technique of the film film on which the panel and the data driver (multi-output driver IC (Driver IC)) for driving the panel are mounted. From this point of view, the line-sequential driving employed in the direct-view liquid crystal display device cannot be performed, and dot-sequential driving (block-sequential driving) has been performed.

Under such circumstances, along with the rapid progress of the narrow pitch connection technology in recent years, it has become possible to apply to line sequential driving and pseudo line sequential driving (signal line selection driving) in a micro display.
SID2005 Digest p. 1099 “10-bit-Source Driver with Resister-Resister-String Digital to Analog Converter” SID 2004 Digest p. 1568 “A Novel Offset Cancellation Circuit for TFT-LCD Driver”

  However, a data driver (multi-output driver IC) used in a direct-view type liquid crystal display panel generally has an H / V inversion with different polarities between adjacent pixels as shown in FIG. Since it corresponds to driving (dot inversion driving), the polarity of the output of the multi-output driver IC is inverted every adjacent.

On the other hand, in the micro display used in the projection type liquid crystal display device, as described above, since the pixel pitch is as narrow as about 10 μm, if the polarities are different between adjacent pixels, the electric field between the adjacent electrodes is not between the opposing electrodes. It is strongly affected and causes light leakage due to the reverse tilt domain.
For this reason, in general, the H-line inversion driving in which the polarity is inverted only for each scanning line as shown in FIG. 2 is mainstream, and the polarity of the output of the multi-output driver IC is inverted every adjacent. Absent.

  In recent years, in order to cope with further narrowing of pitch, commercialization of V inversion driving (field inversion driving) that does not invert the polarity for each scanning line as shown in FIG. 3 has been performed. The polarity of the output of the multi-output driver IC is not inverted every adjacent.

  Thus, the multi-output driver IC mounted on the film applied to the direct-view type liquid crystal display device and the multi-output driver IC mounted on the film applied to the projection type liquid crystal display device have the polarities of adjacent outputs. There is a difference between inversion and non-inversion.

  For this reason, the former multi-output driver IC in which the polarity of the adjacent output is inverted is a digital analog converter (DAC) + analog buffer circuit (output circuit) dedicated to positive output and a DAC + analog buffer circuit (output) dedicated to negative output Circuit) and shared between adjacent ones, and the output can be selected by a changeover switch.

  On the other hand, in the latter multi-output driver IC in which the polarity of the adjacent output is not inverted, it is necessary to provide a positive DAC + negative DAC + analog buffer circuit for each output. As a result, there is a problem that high-speed operation cannot be performed.

  In addition, with the spread of liquid crystal televisions in recent years, there has been an increasing demand for video display devices for multi-gradation, multi-pixel & high frame rate. Therefore, it is desired to achieve both of high gradation and multi-gradation.

Here, a configuration example of a DAC and an output circuit (analog buffer circuit) as a related technique will be described.
Here, detailed description in the functional block is omitted.

  FIG. 4 is a diagram showing a configuration example of a 6-bit low-gradation resistor string DAC (RDAC) corresponding to H / V inversion driving and an output circuit.

The circuit of FIG. 4 includes a positive reference voltage generation circuit 1P formed by a resistance ladder, a negative reference transmission voltage generation circuit 1N formed by a resistance ladder, a positive polarity DAC 2P, a negative polarity DAC 2N, and a positive polarity side. It has an output circuit 3P and a negative polarity side output circuit 3N.
In the circuit of FIG. 4, when the number of gradations of RDAC is 6 bits for each of positive and negative and the total number of outputs Vout is 400, in order to output all the Vouts, C = (1 + 64) as the parasitic capacitance of the switch × 400/2 × Cp = 13000 × Cp.

  FIG. 5 is a diagram showing a configuration example of a DAC of about 10 bits and an output circuit in which a multi-gradation part corresponding to H / V inversion driving is an RDAC and a low gradation part is a CDAC.

In FIG. 5, the same components as those in FIG. 4 are denoted by the same reference numerals. The positive polarity side DAC2P has a multi-gradation part 21P made of RDAC and a low gradation part 22P made of a capacitor DAC (CDAC). Similarly, the negative polarity side DAC2N has a multi-gradation part 21N made of RDAC and a low gradation part 22N made of CDAC.
A multi-gradation DAC combining the RDAC and CDAC as shown in the circuit of FIG. 5 increases the number of gradations. However, compared to the RDAC-only circuit shown in FIG. 4, it is necessary to output two adjacent outputs of the RDAC to the CDAC. Therefore, the switch load that can be seen from the reference voltage generation circuit appears to be doubled and cannot operate at high speed.
Incidentally, in the circuit of FIG. 5, when the number of gradations of RDAC is 6 bits each positive and negative, the number of gradations of CDAC is 4 bits positive and negative, and the total number of outputs Vout is 400, in order to output all Vouts The parasitic capacitance of the switch is C = ((2 + 64) × 400 + (1 + 16) × 400) × Cp = 33200 × Cp.

  FIG. 6 shows a configuration example of a DAC of about 10 bits and an output circuit in which a multi-gradation part is RDAC and a low gradation part is CDAC corresponding to a micro display that performs H-line inversion driving and V inversion driving (field inversion driving). FIG.

In the circuit of FIG. 6, switches 23P and 23N are provided in the output portions of the low gradation portions 22P and 22N made of CDAC, and the output circuit 3 including the voltage follower 31 is made one.
In the circuit of FIG. 6, since the polarities to be output in the adjoining are the same, as shown in FIG. 5, the positive polarity circuit and the negative polarity circuit cannot be shared, the circuit scale per output increases, and the chip area increases. Not only that, the load of the reference generation circuit is required for the number of output terminals, and when the number of terminals is the same, the load is doubled, so that high speed driving cannot be performed.
It should be noted that the switches used in the circuits of FIGS. 4 to 6 are not complementary CMOS, and all the positive polarity switches can be constituted by PMOS, and all the negative polarity switches can be constituted by NMOS.

On the other hand, an offset voltage is generated in the output circuit (analog buffer) due to a manufacturing problem.
In the liquid crystal display device, if the average absolute potential with respect to the positive polarity and the negative polarity VCOM potential is the same, unevenness is not caused. However, in normal H / V inversion driving, the positive polarity analog buffer and the negative polarity analog buffer are different. Therefore, the offset voltage differs between the positive polarity and the negative polarity, resulting in display unevenness.
On the other hand, in the field inversion driving, since the positive polarity and the negative polarity are written in the same analog buffer, there is an advantage that the absolute potential due to the offset voltage variation is averaged and display unevenness does not occur.

Further, Non-Patent Document 1 that discloses a technique related to a multi-gradation DAC is known.
Non-Patent Document 1 discloses an example in which the high gradation part is RDAC and the low gradation part is RDAC.
However, in this method, it is necessary to reduce the RDAC resistance of the high gradation portion relative to the RDAC resistance of the low gradation portion. However, if the resistance of the low gradation portion is reduced in order to increase the DAC speed, the resistance of the high gradation portion is reduced. Therefore, power consumption increases.

Further, Non-Patent Document 2 that discloses a technique related to an offset voltage of an output circuit (analog buffer) is known.
Non-Patent Document 2 discloses an example relating to offset cancellation of an output circuit (analog buffer) in a driver IC used for normal H / V inversion driving.
In this technique, when adjacent output circuits are shared, offset voltage variation becomes a display problem, so that not only offset cancellation is required, but also the circuit scale increases and the cost increases.

  An object of the present invention is to provide a drive circuit and a display device that can operate at high speed and can suppress an increase in circuit scale and power consumption.

  In order to achieve the above object, a first aspect of the present invention is a drive circuit that includes a digital-analog converter (DAC) that converts digital data into analog data, and outputs the converted data to a drive target. A high gradation DAC, and a low gradation DAC connected to the output of the high gradation DAC. The high gradation DAC is separated into a positive polarity DAC and a negative polarity DAC, and the low gradation DAC is positively connected. And negative polarity, and adjacent output terminals have the same polarity.

  A second aspect of the present invention includes a display unit in which pixels are arranged in a matrix and a driving circuit that drives the display unit, and the driving circuit converts digital data into analog data. A converter (DAC), and outputs conversion data to the display unit. The DAC includes a high gradation unit DAC and a low gradation DAC connected to the output of the high gradation DAC. The high gradation DAC Separated into a positive polarity side DAC and a negative polarity side DAC, the low gradation DAC is shared by the positive polarity and the negative polarity, and adjacent output terminals have the same polarity.

  According to the present invention, adjacent output terminals have the same polarity, and a high gradation part functions as a multi-gradation DAC composed of an RDAC and a low gradation part as a CDAC, and outputs of positive and negative RDACs are possible. Input to low gradation DAC.

  According to the present invention, there is an advantage that high-speed operation can be realized and an increase in circuit scale and power consumption can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 7 is a schematic diagram illustrating a configuration example of an active matrix display device according to an embodiment of the present invention.
Here, for example, a case where the present invention is applied to an active matrix type liquid crystal display device using a liquid crystal cell as an electro-optical element of each pixel will be described.

  As shown in FIG. 7, the liquid crystal display device 10 includes an effective display unit 11 in which a plurality of pixels including liquid crystal cells are arranged in a matrix on a transparent insulating substrate, for example, a glass substrate 1, and the effective display unit in FIG. 11, a data driver (horizontal drive circuit: H driver) 12 arranged on the upper side of FIG. 11, and a scanning driver (vertical drive circuit: V driver) 13 arranged on the side of the effective display unit 11 in FIG. A power supply circuit 14 and a display controller 15 are integrated.

In the effective display unit 11, a plurality of pixels including liquid crystal cells are arranged in a matrix.
In the effective display section 11, the data driver 12 and the data lines and vertical scanning lines driven by the scanning driver 13 are wired in a matrix.

FIG. 8 is a diagram illustrating an example of a specific configuration of the effective display unit 11.
Here, for simplification of the drawing, the case of a pixel array of 3 rows (n−1 rows to n + 1 rows) and 4 columns (m−2 columns to m + 1 columns) is shown as an example.
8, vertical scanning lines..., 111n-1, 111n, 111n + 1,... And data lines..., 112m-2, 112m-1, 112m, 112m + 1,. The unit pixel 113 is arranged at the intersection of these.

  The unit pixel 113 includes a thin film transistor TFT, which is a pixel transistor, a liquid crystal cell LC, and a storage capacitor Cs. Here, the liquid crystal cell LC means a capacitance generated between a pixel electrode (one electrode) formed by a thin film transistor TFT and a counter electrode (the other electrode) formed opposite thereto.

The thin film transistor TFT has a gate electrode connected to the vertical scanning lines..., 111n-1, 111n, 111n + 1,..., And a source electrode connected to the data lines ..., 112m-2, 112m-1, 112m, 112m + 1,. .
In the liquid crystal cell LC, the pixel electrode is connected to the drain electrode of the thin film transistor TFT, and the counter electrode is connected to the common line 114. The storage capacitor Cs is connected between the drain electrode of the thin film transistor TFT and the common line 114.
A predetermined AC voltage is applied to the common line 114 as a common voltage Vcom by a VCOM circuit 115 formed integrally with the driving circuit or the like on the glass substrate 11.

One end of each of the vertical scanning lines... 111n-1, 111n, 111n + 1,... Is connected to each output end of the corresponding row of the scanning driver 14 shown in FIG.
The scan driver 13 includes a shift register, for example, and generates vertical selection pulses sequentially in synchronization with a vertical transfer clock VCK (not shown) to generate vertical scan lines..., 111n−1, 111n, 111n + 1,. A vertical scan is performed by giving.

  In the display unit 11, for example, one end of each of the data lines..., 112m-1, 112m + 1,... Is connected to each output end of the data driver 12 shown in FIG.

  The data driver 12 stores digital data (for example, R data, B data, and G data) by the display controller 15 in the sampling latch circuit, and performs conversion processing to analog data, for example, three times during one horizontal period (H). The three data are selected in a time division manner within the horizontal period and output to the corresponding data line.

  FIG. 9 is a block diagram illustrating a configuration example of the data driver according to the present embodiment.

  As shown in FIG. 9, the data driver 13 includes a shift register circuit 131 that sequentially outputs a shift pulse (sampling pulse) from each transfer stage in synchronization with a horizontal transfer clock, an input latch circuit 132 that latches display data, A sampling memory (latch) circuit that sequentially samples and latches digital image data latched in the input latch circuit 132 by a sampling pulse supplied from the shift register circuit 131, and data of the sampling memory circuit 133 in synchronization with the latch signal SL. In response to the hold memory circuit 134 that latches, the level shift circuit 135 that shifts the level of the data held in the hold memory circuit 134, the reference voltage generation circuit 136 such as a resistance ladder, and the reference voltage generated by the reference voltage generation circuit 136 Lebe The digital image data subjected to shifting action has a digital / analog converter (DAC) 137 for converting an analog image signal, and an output circuit (analog buffer) 138 for outputting an analog image data to the data line 111, a.

  A configuration example of a driver including the reference voltage generation circuit 136, the DAC 137, and the output circuit 138, which are characteristic components of the present embodiment, will be described in detail later.

  The power supply circuit 14 includes a DC-DC converter. For example, a liquid crystal voltage is supplied from the outside, and the voltage is boosted to the internal panel voltage VDD in synchronization with the master clock MCK, the horizontal synchronization signal Hsync, and the like. Supply to the circuit.

  The display controller 15 includes a timing generator and the like, and in synchronization with the master clock MCK, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync, the horizontal start pulse HST, the horizontal clock pulse HCK (HCKX), A vertical start pulse VST and a vertical clock VCK (VCKX) used as a clock for the scan driver 13 are generated, a horizontal start pulse HST and a horizontal clock pulse HCK (HCKX) are supplied to the data driver 12, and a vertical start pulse VST and a vertical clock are supplied. VCK (VCKX) is supplied to the scan driver 13.

  Here, first to sixth configuration examples of the driver unit including the reference voltage generation circuit 136, the DAC 137, and the output circuit 138 of the data driver according to the present embodiment will be described.

In the driver section of the data driver (multi-output driver IC) 12 of the liquid crystal display device 10, basically, the adjacent output terminals have the same polarity, the high gradation part is composed of RDAC, and the low gradation part is composed of CDAC. In the gradation DAC, the RDAC is composed of a positive polarity and a negative polarity, and the CDAC is shared.
In addition, a positive / negative switching switch is provided at the input node to the CDAC, a switch that outputs the RDAC by a two-stage switch, and can precharge the input node to the CDAC is provided. .
With such a configuration, a multi-tone high-speed DAC can be realized in a liquid crystal display device that is driven with the same polarity, such as field inversion driving.

<First configuration example>
FIG. 10 is a circuit diagram showing a first configuration example of the driver unit including the reference voltage generation circuit 136, the DAC 137, and the output circuit 138 of the data driver according to the present embodiment.

The reference voltage generation circuit 136 is separated into a positive polarity side reference voltage generation circuit 136P and a negative polarity side reference voltage generation circuit 136N.
Similarly, the DAC 137 is a multi-gradation DAC in which a high gradation part is composed of an RDAC and a low gradation part is composed of a CDAC. Sharing.
The output circuit 138 includes one voltage follower 1381 that outputs the output data of the CDAC 1371.

The reference voltage generation circuit 136P has a resistance ladder 1361P.
The resistor ladder 1361P includes a plurality of resistors R1H to RnH that are connected in cascade between a supply terminal for the maximum reference voltage VHB and a supply terminal for the minimum reference voltage VHA. A plurality of reference voltages VHA, VR1H, VR2H, VR3H,..., VRnH, VHB whose values sequentially change from the nodes REF1H to REFn + 1H between the two resistors connected in series and the two supply terminals through the resistor RH. And output to the RDAC 1371P.

The reference voltage generation circuit 136N has a resistance ladder 1361N.
The resistor ladder 1361N includes a plurality of resistors R1L to RnL connected in cascade between a supply terminal for the maximum reference voltage VLB and a supply terminal for the minimum reference voltage VLA. A plurality of reference voltages VLA, VR1L, VR2L, VR3L,..., VRnL, VLB whose values sequentially change are output from nodes REF1L to REFn + 1L between the two resistors connected in series and the two supply terminals.

The RDAC 1371RP includes a switch SWHP that selectively processes the maximum reference voltage VHB, a switch SWLP that selectively processes the minimum reference voltage VHA, and a switch that selectively processes the reference voltage divided by the resistance in parallel. SW1H1, SW1H2 to SWnH1, SWnH2. C indicates the capacitance across the switch.
The first system switches SW1H1 to SWnH1 and the second system switches SW1H2 to SWnH2 have separate output lines.

The RDAC 1371 RN includes a switch SWHN that selectively processes the maximum reference voltage VLB, a switch SWLN that selectively processes the minimum reference voltage VLA, and a switch that selectively processes the resistance-divided reference voltage in parallel. SW1L1, SW1L2 to SWnL1, SWnL2. C indicates the capacitance across the switch.
The first system switches SW1H1 to SWnH1 and the second system switches SW1H2 to SWnH2 have separate output lines.

  In the RDAC 1371RP and the RDAC 1371RN, the first system and the second system are connected to each other.

  The CDAC 1372 is connected in parallel to the capacitors C1 to Cn and the capacitors C1 to Cn, and receives the output of the first system and the second system of the RDAC 1371RP and the RDAC 1371RN and selectively processes the switches SW1 and SW2 groups. And a switch SW3.

As described above, in the first configuration example of FIG. 10, the high-gradation portion RADC is separated into positive polarity and negative polarity, and the low gradation portion CDAC is shared with positive polarity and negative polarity.
At this time, the switch needs to be a complementary CMOS. However, since the CDAC capacity can be shared between the positive polarity and the negative polarity, the entire circuit scale can be reduced.
In addition, by using a CMOS switch, it is possible to reduce feedthrough that occurs when the switch is closed, so that the output accuracy can be improved.

  Incidentally, in the circuit of FIG. 10, when the number of gradations of RDAC is 6 bits each positive and negative, the number of gradations of CDAC is 4 bits positive and negative, and the total number of outputs Vout is 400, in order to output all Vouts The parasitic capacitance of the switch is C = ((2 + 64 + 64) × 400 + (1 + 16) × 400) × Cp = 58800 × Cp.

<Second configuration example>
FIG. 11 is a circuit diagram illustrating a second configuration example of the driver unit including the reference voltage generation circuit 136, the DAC 137, and the output circuit 138 of the data driver according to the present embodiment.

In the second configuration example, in addition to the configuration of the first configuration example, switches SW11 to SW14 for separating the positive polarity RDAC 1371RP and the negative polarity RDAC 1371RN of the high gradation portion are provided in front of the CDAC 1371 of the low gradation portion. Although the switch resistance of the RDAC portion increases, the parasitic capacitance of the switch can be greatly reduced, so that it can operate at high speed.
The reason why the parasitic capacitance can be reduced is that when the positive polarity is operating, the parasitic capacitance of the switch associated with the negative polarity RDAC, and when the negative polarity is operating, the parasitic capacitance of the switch associated with the positive polarity RDAC is This is to make it invisible.

<Third configuration example>
FIG. 12 is a circuit diagram showing a third configuration example of the driver unit including the reference voltage generation circuit 136, the DAC 137, and the output circuit 138 of the data driver according to the present embodiment.

In the third configuration example, in addition to the configuration of the first configuration example, the gradation selection switches SW21 to SW24 of the high gradation portion RDAC having positive polarity and negative polarity are further provided for selecting the high gradation portion and the low gradation portion. Separated for selection, in two stages.
As a result, the selection switches for all the gradations that have been hung up to the prior art are reduced to half or less, so that it is possible to drive at high speed.

  Incidentally, in the circuit of FIG. 12, when the number of gradations of RDAC is separated every 3 bits by 6 bits each of positive and negative, and the number of gradations of CDAC is 4 bits, the total number of outputs Vout is 400. In order to output Vout, the parasitic capacitance of the switch is C = ((2 + 8 + 1 + 8 + 8) × 400 + (1 + 16) × 400) × Cp = 17600 × Cp.

<Fourth configuration example>
FIG. 13 is a circuit diagram showing a fourth configuration example of the driver unit including the reference voltage generation circuit 136, the DAC 137, and the output circuit 138 of the data driver according to the present embodiment.

The fourth configuration example has a configuration in which the second configuration example and the third configuration example are combined.
In this way, a further high-speed operation is possible by combining the second configuration example and the third configuration example.

  Incidentally, in the circuit of FIG. 13, when the number of gradations of RDAC is separated every 3 bits by 6 bits each of positive and negative, and the number of gradations of CDAC is 4 bits, the total number of outputs Vout is 400. In order to output Vout, the parasitic capacitance of the switch is C = ((2 + 8 + 1 + 8 + 4) × 400 + (1 + 16) × 400) × Cp = 16000 × Cp.

<Fifth configuration example>
FIG. 14 is a circuit diagram showing a fifth configuration example of the driver unit including the reference voltage generation circuit 136, the DAC 137, and the output circuit 138 of the data driver according to the present embodiment.

  In the fourth configuration, in addition to the configuration of the first configuration example, by providing the switches SW31 to SW34 that precharge to the intermediate potential of the polarity that outputs the input node to the CDAC in the low gradation portion, the output accuracy is maximized. As the output accuracy of the intermediate potential increases, the settling time can be shortened. The switches SW31 and SW32 selectively supply a positive intermediate potential, and the switches SW33 and SW34 selectively supply a negative intermediate potential.

  Incidentally, in the circuit of FIG. 14, when the number of gradations of RDAC is 6 bits each positive and negative, the number of gradations of CDAC is 4 bits positive and negative, and the total number of outputs Vout is 400, all the Vouts are output. The parasitic capacitance of the switch is C = ((2 + 64 + 64 + 2) × 400 + (1 + 16) × 400) × Cp = 59600 × Cp.

<Sixth configuration example>
FIG. 15 is a circuit diagram illustrating a sixth configuration example of the driver unit including the reference voltage generation circuit 136, the DAC 137, and the output circuit 138 of the data driver according to the present embodiment.

The fifth configuration example has a configuration in which the second configuration example and the third configuration example are combined.
In this way, a further high-speed operation is possible by combining the second configuration example and the third configuration example.

  Incidentally, in the circuit of FIG. 15, when the number of gradations of RDAC is separated every 3 bits by 6 bits each of positive and negative, and the number of gradations of CDAC is 4 bits positive and negative, the total number of outputs Vout is 400. In order to output Vout, the parasitic capacitance of the switch is C = ((2 + 8 + 1 + 8 + 4 + 2) × 400 + (1 + 16) × 400) × Cp = 16800 × Cp.

Further, in the above configuration example, the precharge is performed to the intermediate potential of the output polarity, but it is not necessary to precharge every time, and the precharge may be performed only when the polarity is inverted.
Further, when the output is inverted in polarity, it may be precharged to the center potential of the video signal including the positive polarity and the negative polarity even if it is not the intermediate potential of the output polarity. In this case, since there is one precharge signal, there are advantages in that the number of precharge switches is reduced and the circuit scale is reduced.

FIG. 16 is a diagram illustrating a state when a desired switch of the positive polarity side RDAC 1371RP in the sixth configuration example according to the present embodiment is turned on and the switch SW1 of the CDAC 1372 is turned on.
FIG. 17 is a timing chart of the circuit of FIG.
FIG. 16 shows a state in which the switches of RDAC 1371RP are A1 (SW11, SW12) and the switches SWnH1 and SWnH2 at predetermined stages are turned on.
Here, the switches of RDAC 1371RP and RDAC 1371RN are represented as A1 to A3, and the switches of CDAC 1372 are represented as B1, B2, and B3.
Further, the switches SW31 and SW32 are represented as CW1, and the switches SW33 and SW34 are represented as CW2.

In this example, as can be seen from FIG. 17, precharging is performed only when the polarity of the output is inverted, and a positive output and a negative output can be obtained with high response and high speed.
In the apparatus, a multi-gradation and high-speed DAC can be realized, and it is possible to cope with a future increase in the number of pixels and a frame rate.

  As described above, according to the present embodiment, in the driver unit of the data driver (multi-output driver IC) 12 of the liquid crystal display device 10, the adjacent output terminals basically have the same polarity and the high gradation portion is RDAC and multi-gradation DAC in which low gradation part is composed of CDAC, RDAC is composed of positive polarity and negative polarity, CDAC is shared, and further, positive polarity and negative polarity at input node to CDAC The following effects can be obtained because the switch is provided, which outputs the RDAC with a two-stage switch and can precharge the input node to the CDAC.

  That is, by using this method, it is possible to realize a high-speed DAC with multiple gradations in a liquid crystal display device that is driven with the same polarity as in field inversion driving, and in the future, the number of pixels and the frame rate will be increased Can be supported.

  Further, it is assumed that adjacent output terminals of a data driver (multi-output driver IC) such as H-line inversion driving and field inversion driving have the same polarity. In the third and fourth configuration examples, adjacent output terminals are used. The effect can be expected even with different polarities, and it can be applied not only to driving with polarity such as COM inversion driving but also to multi-output driver ICs of image display devices such as organic EL that do not perform polarity inversion driving. It is possible.

  Further, in the present embodiment, 10 bits have been described as an example, but it is possible to cope with further multi-gradation such that the RDAC is 8 bits and the CDAC is 4 bits, for example, a total of 12 bits.

  In the above embodiment, the case where the present invention is applied to an active matrix liquid crystal display device has been described as an example. However, the present invention is not limited to this, and an electroluminescence (EL) element is used as an electro-optical element of each pixel. The present invention can be similarly applied to other active matrix display devices such as EL display devices.

  Furthermore, the active matrix type display device represented by the active matrix type liquid crystal display device according to the above embodiment is used as a display for OA devices such as personal computers and word processors, television receivers, etc. It is suitable for use as a display unit of a portable terminal such as a mobile phone or a PDA that is being reduced in size and size.

It is a figure which shows notionally H / V inversion drive (dot inversion drive). It is a figure which shows H line inversion drive notionally. It is a figure which shows a field inversion drive notionally. FIG. 5 is a diagram illustrating a configuration example of a 6-bit low-gradation resistor string DAC (RDAC) corresponding to H / V inversion driving and an output circuit. FIG. 5 is a diagram illustrating a configuration example of a DAC of about 10-bit bits in which a multi-gradation part corresponding to H / V inversion driving is an RDAC and a low gradation part is a CDAC and an output circuit. FIG. 5 is a diagram showing a configuration example of a 10-bit DAC and an output circuit in which a multi-gradation part corresponding to a micro display that performs H-line inversion driving and V inversion driving (field inversion driving) is an RDAC with a multi-gradation part and a CDAC with a low gradation part. is there. It is the schematic which shows the structural example of the active matrix type display apparatus which concerns on embodiment of this invention. It is a figure which shows an example of the specific structure of an effective display part. It is a block diagram which shows the structural example of the data driver which concerns on this embodiment. FIG. 3 is a circuit diagram illustrating a first configuration example of a driver unit including a reference voltage generation circuit, a DAC, and an output circuit of a data driver according to the present embodiment. It is a circuit diagram which shows the 2nd structural example of the driver part which consists of the reference voltage generation circuit of the data driver which concerns on this embodiment, DAC, and an output circuit. It is a circuit diagram which shows the 3rd structural example of the driver part which consists of the reference voltage generation circuit of the data driver which concerns on this embodiment, DAC, and an output circuit. It is a circuit diagram which shows the 4th structural example of the driver part which consists of the reference voltage generation circuit, DAC, and output circuit of the data driver which concern on this embodiment. It is a circuit diagram which shows the 5th structural example of the driver part which consists of the reference voltage generation circuit of the data driver which concerns on this embodiment, DAC, and an output circuit. It is a circuit diagram which shows the 6th structural example of the driver part which consists of the reference voltage generation circuit of the data driver which concerns on this embodiment, DAC, and an output circuit. It is a figure which shows a state when the desired switch of positive polarity side RDAC in the 6th structural example which concerns on this embodiment is turned ON, and switch SW1 of CDAC is turned ON. It is a timing chart of the circuit of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display device, 11 ... Effective display part, 12 ... Data driver, 13 ... Scan driver, 14 ... Power supply circuit, 15 ... Display controller, 131 ... Shift register Circuit 132... Input latch circuit 133 133 sampling memory (latch) circuit 134 hold memory circuit 135 level shift circuit 136 reference voltage generating circuit 137 Digital / analog conversion circuit (DAC), 138... Output circuit (analog buffer), 136P... Positive polarity side reference voltage generation circuit, 136N... Negative polarity side reference voltage generation circuit, 1371RP. Side RDAC, 1371 RN: negative polarity RDAC, 1372: CDAC.

Claims (13)

A drive circuit that includes a digital-analog converter (DAC) that converts digital data into analog data, and that outputs the converted data to a drive target,
The DAC is
Including a high gradation DAC and a low gradation DAC connected to the output of the high gradation DAC;
The high gradation DAC is separated into a positive polarity side DAC and a negative polarity side DAC,
The low gradation DAC is shared by the positive polarity and the negative polarity,
Drive circuit where adjacent output terminals have the same polarity. The high gradation DAC is formed by a resistance tring DAC (RDAC),
The drive circuit according to claim 1, wherein the low gradation DAC is formed by a capacitor DAC (CDAC). The drive circuit according to claim 2, further comprising a switch that separates the positive polarity RDAC and the negative polarity RDAC at an input portion of the CDAC. The drive circuit according to claim 2, wherein the gradation selection switch of the RDAC is selected in a plurality of stages. The drive circuit according to claim 3, wherein the gradation selection switch of the RDAC is selected in a plurality of stages. 4. The drive circuit according to claim 3, further comprising means for precharging the input node of the CDAC. 5. The drive circuit according to claim 4, further comprising means for precharging the input node of the CDAC. 6. The drive circuit according to claim 5, further comprising means for precharging the input node of the CDAC. A display unit in which pixels are arranged in a matrix;
A drive circuit for driving the display unit,
The drive circuit is
Including a digital-analog converter (DAC) for converting digital data into analog data, and outputting the converted data to the display unit;
The DAC is
Including a high gradation DAC and a low gradation DAC connected to the output of the high gradation DAC;
The high gradation DAC is separated into a positive polarity side DAC and a negative polarity side DAC,
The low gradation DAC is shared by the positive polarity and the negative polarity,
A display device in which adjacent output terminals have the same polarity. The high gradation DAC is formed by a resistor string DAC (RDAC),
The display device according to claim 9, wherein the low gradation DAC is formed by a capacitor DAC (CDAC). The display device according to claim 10, further comprising: a switch that separates a positive polarity RDAC and a negative polarity RDAC at an input portion of the CDAC. The display device according to claim 11, wherein the gradation selection switch of the RDAC is selected in a plurality of stages. The display device according to claim 12, further comprising means for precharging the input node of the CDAC.

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