JP2007052087A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device which can materialize the power saving in a stand-by mode or else in the device. <P>SOLUTION: In normal mode, a multitone analog video signal is output to a data line. On the other hand, in stan-by mode, either white display data WHITE or black display data BLACK is selected by a specific bit of video image signal. Thereby, operation of an analog signal processing circuit is stopped, white and black display can be performed and, consequently, the power saving can be materialized. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to the efficiency of standby such as monochrome display in a display device such as a liquid crystal display device.

  Conventionally, flat panel type display devices such as liquid crystal display devices have been widely used. In particular, a small and light display device is indispensable for a portable device, and a liquid crystal display device is mainly used in, for example, a mobile phone.

  In this liquid crystal display device, in order to display a high-definition image, an active matrix type having a pixel circuit for each display pixel and capable of high-definition display is used.

  In addition, there is a request for making a battery life as long as possible in a mobile phone or the like, but there is also a request for performing a minimum display such as a time display even in a non-use state such as a telephone function such as a standby state. Therefore, there are many cases where only the time and the radio wave state are displayed as a standby mode when the telephone function or the like is not used.

  As for the liquid crystal display device, there are many proposals, for example, described in Patent Document 1, and this Patent Document 1 also describes AC drive for preventing liquid crystal burn-in.

JP 2003-255399 A

  However, there is a great demand for portable devices to further reduce power consumption and extend battery life.

  In a display device that performs display using an analog data signal obtained by digital-analog conversion of a digital video signal, the gradation of the digital video signal is based on the digital video signal in a standby mode. A mode changeover switch for selecting and outputting the analog data signal indicating the display luminance of the gradation obtained by selecting the data signal for standby less than the number and converting the digital video signal into digital analog in the normal display mode; And in the standby mode, display is performed without using the analog data signal.

  Further, the standby data signal is only two of white display data and black display data determined according to the value of the digital video signal, and one of them is a specific 1-bit of the digital video signal. It is preferable to further include a monochrome switching switch that is selected according to the value.

  A digital-analog converter for digital-analog conversion of the digital video signal; and an amplifier for amplifying the output of the digital-analog converter, and supplying the output of the amplifier as the analog data signal to the mode switch. In the standby mode, it is preferable to stop the operations of the digital-analog converter and the amplifier.

  Further, the display device includes a plurality of pixels arranged in a matrix, a data line is provided corresponding to each pixel column, a selection line is provided corresponding to each pixel row, and each pixel includes: A switching element that is turned on / off by the selection signal of the selection line and takes in the data line signal, a capacitor that holds a voltage corresponding to the signal of the data line when the switching element is on, and a voltage held in the capacitor are applied A liquid crystal element, and the digital-to-analog converter outputs a digital-to-analog signal in which the polarity of the digital video signal for each pixel in the row direction is sequentially inverted with respect to a reference voltage, and the standby data signal is It is preferable to include a voltage in which the power supply voltage and the ground voltage are alternately selected for each horizontal scanning period.

  Thus, according to the present invention, the standby data signal can be selected by the mode switch. When this standby data signal is used, there is no need to convert the digital video signal into an analog signal. Therefore, operations of processing circuits such as digital-analog conversion and analog signal amplification can be stopped, and power saving can be achieved.

  In particular, if black and white binary display is performed in the standby mode, the display can be determined by specific one bit of the digital video signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

"overall structure"
FIG. 1 is a diagram illustrating a configuration for supplying video data to a pixel circuit in a liquid crystal display device according to an embodiment.

  In this embodiment, the 6-bit video line 10 sequentially transfers 64-gradation digital luminance signals for each pixel according to the pixel clock. Actually, there are three video lines of R (red), G (green), and B (blue), and video data of each color is supplied in parallel and supplied to the corresponding color pixels. In the figure, only one color is shown.

  The video line 10 is connected to an input terminal of a switch 12 provided corresponding to each column of pixels. The control terminal of the switch 12 is connected to the output of the horizontal transfer register 14. Here, the horizontal transfer register 14 sequentially transfers a horizontal start signal (STH) with a pixel clock synchronized with the timing of each pixel of video data supplied to the video line, and corresponds to each column of pixels. Has a register. In this description, the display bits and the pixels are the same in order to describe the display of one type of RGB color. Also, the transfer clock supplied to the horizontal transfer register often uses two clocks (CKH, XCKH) having a cycle twice that of the normal pixel clock and having the phases inverted.

  That is, when the video data of the pixels in the first column is supplied to the video line 10, the horizontal start signal STH is taken into the first one of the horizontal transfer register 14, and the corresponding switch 12 is turned on. Then, the horizontal start (STH) signal is sequentially transferred in the horizontal transfer register 14 by the pixel clock, so that the switch 12 corresponding to the pixel is sequentially turned on for the video data for each pixel supplied to the video line 10. Is done. Note that the switch 12 is configured by connecting a p-channel transistor (TFT) and an n-channel transistor (TFT) in parallel, and each is simultaneously turned on / off by a non-inverted output and an inverted output of one register of the horizontal transfer register 14.

  An input terminal of a 6-bit SRAM 16 is connected to the output terminal of each switch 12, and an input terminal of a 6-bit SRAM 18 is connected to the output terminal of each SRAM 16. Therefore, the video data for each pixel sequentially supplied to the video line 10 is taken into the corresponding SRAM 16 when the switch 12 is sequentially turned on. When video data for one row (one horizontal scanning line) is taken into each SRAM 16, the video data for one row is simultaneously transferred to the corresponding SRAM 18, and this is repeated for each horizontal scanning period. . Accordingly, in each horizontal scanning period, video data for one row is taken into the SRAM 16 and then transferred to the SRAM 18, and the transferred video data is held in the SRAM 18 in the next horizontal scanning period and output therefrom. become. Then, this operation is repeated.

  An input end of a digital-analog converter (DAC) 20 is connected to the output end of the SRAM 18. The DAC 20 converts 6-bit video data supplied from the SRAM 18 into an analog video signal having 64 gradations. Note that the DAC 20 performs so-called AC driving in which the voltage application direction to the liquid crystal is changed at a predetermined cycle, so that the voltage application direction to the liquid crystal is opposite with respect to two types of polarities (the common electrode potential of the liquid crystal element is used as a reference). Output video signals of one polarity). As will be described later, in this embodiment, since the dot inversion method is used as the AC driving method, the direction (polarity) of the voltage applied to the liquid crystal is inverted in the adjacent pixels in the horizontal and vertical directions. For the liquid crystal of one pixel, it is inverted every frame.

  Further, an input terminal of an amplifier (Amp) 22 is connected to an output terminal of each DAC 10, and an output terminal of the amplifier 22 is connected to the data line DL via the changeover switch 24. The data line DL extends in a column (vertical scanning direction), and a corresponding one column of pixel circuits 100 is connected thereto. In this example, since the source of the pixel TFT in the pixel circuit 100 is connected to the data line DL, it is also called a source line.

  Therefore, the analog video signal output from the DAC 20 is supplied to the data line DL, and the pixel circuit 100 in the corresponding row captures the display, so that display according to the analog video signal captured in each pixel is performed.

“Configuration of SRAM”
In this embodiment, each column has two SRAMs 16 and 18 that hold 6-bit digital video data. Further, the dynamic range of video data is set to be relatively small, and there is a demand for increasing the dynamic range as data to be input to the DAC 20. Therefore, for example, the level shift is performed from 5V amplitude to 8V amplitude.

  In the present embodiment, the SRAM 16 is configured by combining a latch circuit and a level shifter, and level shift is also performed in the SRAM 16.

  FIG. 2 shows a configuration of a latch type level shift circuit (SRAM 16) according to the present embodiment and a latch circuit (SRAM 18) that latches the output of the SRAM 16. Here, the video data is 6-bit digital data, and only one bit is shown.

  Digital video data with 5 V amplitude is supplied to the switch 610. The switch 610 is controlled by a clock synchronized with a dot clock, and takes in video data supplied to an input terminal for each display pixel (dot). For example, when the corresponding switch 12 of the video line 10 in FIG. 1 is on, the switch 610 is turned on to capture video data. Note that the switch 610 may be employed as the switch 12.

  A first latch 620 is connected to the output terminal of the switch 610. The first latch 620 is composed of two inverters 622 and 624 having a 5V amplitude and 5 V operation in which the input and output are connected to each other. In this example, since the output from the switch 610 is supplied to the input side of the inverter 622, an inverted signal is input to the inverter 624. Therefore, the state of the input of the inverter 622 is determined by the state of the output of the switch 610, and the state of the pair of output sides of the inverter 622 is also determined.

  Here, in this example, it is preferable that the capacity of the inverter 622 is larger than that of the inverter 624. Thereby, even when the input video data is inverted, the output of the inverter 622 can be easily inverted and the data can be latched.

  A pair of outputs (opposite polarities) of the first latch 620 are input to the voltage driven level shifter 630. The level shifter 630 has a configuration in which two series connections of three transistors arranged between 8V VDD and 0V VSS are arranged in parallel.

  Between VDD and VSS, a series connection of a p-channel TFT 632a, a p-channel TFT 634a, and an n-channel TFT 636a and a series connection of a p-channel TFT 632b, a p-channel TFT 634b, and an n-channel TFT 636b are arranged. The output of the switch 610 latched by the latch circuit 620 is supplied to the gates of the TFTs 634a and 636a, and the inverted signal of the output of the switch 610 latched by the latch circuit 620 is supplied to the gates of the TFTs 634b and 636b. The The gate of the TFT 632a is connected to an intermediate point between the TFTs 634b and 636b, and the gate of the TFT 632b is connected to an intermediate point between the TFTs 634a and 636a.

  With such a configuration, depending on the output of the latch 620, the gate of the TFT 632a is an intermediate point between the TFT 634b and the n-channel TFT 636b, the gate of the TFT 632b is either an intermediate point between the TFT 634a or the n-channel TFT 636a, and the other is Becomes L level. For example, when the output of the switch 610 is at H level (“1”), the intermediate point between the TFT 634b and the n-channel TFT 636b is H level, and the intermediate point between the TFT 634a and the n-channel TFT 636a is L level.

  Outputs from the intermediate point of the TFT 634 b and the n-channel TFT 636 b and the intermediate point of the TFT 634 a and the n-channel TFT 636 a are input to the second latch 640. The second latch 640 is configured by connecting an inverter 642 and an inverter 644, and an output of an intermediate point between the TFT 634 b and the n-channel TFT 636 b is input to the input of the inverter 642, and an intermediate point of the TFT 634 a and the TFT 636 a is input to the inverter 644. The output of the inverter 642 (the input of the inverter 644) is the output of the second latch 640.

  Accordingly, the data input to the switch 610 is latched by the first latch 620, and the signal level-shifted by the level shifter 630 and the level-shifted and inverted signal are latched by the second latch 640 as an 8V signal. The first latch 620, the level shifter 630, and the second latch 640 constitute the SRAM 16. Accordingly, a signal obtained by level shifting the 5V amplitude to the 8V amplitude is obtained at the output of the SRAM 16. As described above, by providing the latch circuits on the input side and the output side of the level shifter 630, the latch operation and the level shift operation can be performed simultaneously. Therefore, power consumption can be reduced as compared with the case where these are performed separately.

  The output of the second latch 640 is inverted by the inverter 650. In contrast to the configuration of FIG. 1, up to the inverter 650 corresponds to the SRAM 16, whereby the input video data is stored in accordance with the dot clock and level-shifted and output. .

  The output of the inverter 650 is supplied to the latch 670 via the switch 660. The switch 660 opens for a predetermined period after data for one horizontal scanning line is taken into the SRAM 16. The latch 670 includes an inverter 672 and an inverter 674 whose inputs and outputs are connected to each other. The output of the switch 660 is input to the inverter 672, and the output is the output of the latch 670. The output of the latch 670 is inverted by the inverter 680 and output. Therefore, the latch 670 and the inverter 680 constitute the SRAM 18. That is, at the stage where the video data of each pixel is stored in each SRAM 16 in one horizontal scanning line, the switch 660 is opened, and the video data at this time is set in the SRAM 18. For example, all the data in the SRAM 16 is transferred to the RAM 18 at a time during the horizontal blanking period.

  Thus, according to the present embodiment, the SRAM 16 can also perform level shift when storing data. For this reason, efficient operation can be achieved.

"Configuration of DAC20 upper bit conversion"
FIG. 3 shows the configuration of the upper bit conversion of the DAC 20. The reference voltage generation circuit 300 includes two reference voltage amplifiers 300a and 300b. The reference voltage amplifiers 300a and 300b both divide the power supply voltage VCC and GND by ten resistors R0 to R9 to generate nine reference voltages v0 to v8. The reference voltage amplifiers 300a and 300b operate alternately every horizontal scanning period. Accordingly, the polarities of the nine reference voltages v0 to v8 are inverted every horizontal period. That is, when the reference amplifier 300a is operating, v8 is close to VCC and v0 is close to GND, and vice versa when the reference amplifier 300b is operating. Further, switching of the reference amplifiers 300a and 300b for each horizontal period is performed by a signal FRP. For example, the reference amplifier 300a operates when the signal FRP is at the H level, and the reference amplifier 300b operates when the signal FRP is at the L level.

  The data D5-D3 is input to four decoders of an upper H side decoder 310, an upper L side decoder 312, a lower H side decoder 314, and a lower L side decoder 316. These decoders 310 to 316 also receive reference voltages v0 to v8. Each is supplied. The upper H-side decoder 310 selects and outputs the reference voltages v8 to v1 according to the eight types of data D5-D3 of 111-000, and the upper L-side decoder 312 has the data D5-D3 of 111-000. Reference voltages v7 to v0 are selected and output according to the eight types. Therefore, the output VH of the upper H-side decoder 310 is a voltage one step higher than the output VL of the upper L-side decoder 312 (when v8 is on the VCC side). On the other hand, the lower H-side decoder 314 selects and outputs the reference voltages v0 to v7 according to the eight types of data D5-D3 of 111-000, and the lower L-side decoder 316 receives the data D5-D3 of 111-1000. Reference voltages v1 to v8 are selected and output according to eight types of 000. Accordingly, the output VH of the lower H-side decoder 314 is a voltage one step lower than the output VL of the lower L-side decoder 316 (when v8 is on the VCC side).

  As described above, the upper decoders 310 and 312 output the output voltages VH and VL that are shifted by the voltage corresponding to the bit D3. The lower decoders 314 and 316 increase the analog signals VH and VL that are output with respect to the change direction of the polarity (the direction in which the input digital data increases or decreases) with respect to the upper decoders 310 and 312. The direction in which the direction is smaller or the direction in which the direction is smaller is reversed, but the lower H-side decoder 314 and the lower L-side decoder 316 output the same voltage VH and VL that differ by one bit of D3. .

  When the outputs of the upper decoders 310 and 312 are supplied to the odd-numbered data lines DL, the outputs of the lower decoders 314 and 316 are supplied to the even-numbered data lines DL.

  As described above, the upper decoders 310 and 312 and the lower decoders 314 and 316 reverse the supply of the reference voltage, so that the upper side and the lower side of the panel can be used by using one reference voltage generation circuit 300. Digital-to-analog conversion in both decoders can be performed. Therefore, by alternately supplying the outputs of the upper decoders 310 and 312 and the lower decoders 314 and 316 to the data lines DL, the polarity of the video signal can be inverted for each data line DL. Further, by alternately using the reference voltage amplifiers 300a and 300b for each horizontal line, the polarity of the video signal supplied to each data line DL can be changed for each horizontal scanning line. Therefore, dot inversion driving in the liquid crystal display device can be achieved. When such driving is performed, the reference voltage generation circuit 300 can be made one, so that the circuit can be simplified and power consumption can be reduced.

“Lower bit conversion of DAC 20 and amplifier 22 configuration”
As described above, when VH and VL are obtained from the upper 3 bits (D5 to D3), eight types of voltages corresponding to D2 to D0 are obtained for the voltage difference between VH and VL. FIG. 4 shows a configuration for this purpose. D2 is input as it is to the gate of the TFT 410-2 and is inverted and input to the gate of the TFT 412-2. The TFT 410-2 is supplied with VH at one end, and VL is supplied with one end of the TFT 412-2. The other ends of the TFTs 410-2 and 412-2 are connected to one end of the capacitor 430-2 via the charge control TFT 420-2. The other end of the capacitor 430-2 is connected to the ground.

  Accordingly, when D2 is at the H level (“1”), the TFT 410-2 is turned on and VH is selected. When the charge control TFT 420-2 is on, the capacitor 430-2 is charged to VH. On the other hand, if D2 is at L level (“0”), capacitor 430 is charged to VL.

  D1 and D0 are basically provided with the same configuration as D2. Accordingly, VH or VL is charged in the corresponding capacitors 430-1 and 430-0 according to the values of D1 and D0.

  Further, a charge control TFT 420-r is provided, and the charge control TFT 420-r directly charges the corresponding capacitor 430-r regardless of data. The charge control TFTs 420-r, 420-0, 420-1, and 420-2 are turned on / off by a signal Charge.

  The capacitors 430-r, 430-0, 430-1, and 430-2 are set such that their capacitance values are C, C, 2C, and 4C. Note that C is, for example, 0.5 pF, and in this case, 4C is 2 pF.

  Further, the upper ends of the capacitors 430r, 430-0, 430-1, and 430-2 are connected by three coupling TFTs 440-1, 440-2, and 440-3, and the upper end of the capacitor 430-r is connected to the TFT 440. Output terminal via -r.

  A signal Combine is supplied to the gates of the coupling TFTs 440-1, 440-2, 440-3 and the TFT 440-r.

  With such a circuit, if D2-D0 is all “0”, capacitors 430-2, 430-1, 430-0, and 430-r are all charged to VL. Therefore, the output voltage becomes VL. Here, VL is a value selected by D5-D3 as described above, and is a voltage specified by D5-D0.

  If D0 is “1”, the charge of (VH−VL) · C is charged extra, and the voltage obtained by adding 1 / 8C is added to VL to output VL + (VH−VL) / 8. The If D2 is “1”, the charge of (VH−VL) · 4C is charged excessively, and a voltage obtained by adding 1 / 8C is added to VL to output VL + 4 (VH−VL) / 8. If all of D0, D1, and D2 are “1”, VL + 7 (VH−VL) / 8 is output. Therefore, a voltage in units of (VH−VL) is added to VL according to the value of D0−D3, and a voltage according to the value of D5−D0 is obtained at the output.

  The voltage obtained at this output is a voltage between VCC and GND, and the polarity is inverted between the upper side and the lower side of the panel (odd and even columns), and the polarity is changed every horizontal period. Inverted.

  Here, in this embodiment, the size of the charge control TFTs 420-r, 420-0, 420-1, and 420-2 is set to 1: 1: 2: 4. That is, the capacitance values of the capacitors 430-r, 430-0, 430-1, and 430-2 charged by the charge control TFTs 420-r, 420-0, 420-1, and 420-2 are 1: 1: 2: 4, and the amount of current flowing through the charge control TFTs 420-r, 420-0, 420-1, and 420-2 also corresponds to this ratio. Accordingly, by setting the size of the charge control TFTs 420-r, 420-0, 420-1, and 420-2 to 1: 1: 2: 4 as in the present embodiment, the corresponding capacitors 430-r and 430- The charge amount to 0, 430-1, and 430-2 can be accurately set to the capacitance value × voltage value, and the output voltage can be made accurate. Further, the voltage change due to the MOS capacitance of the transistor (charge control TFT) can be made the same.

"Configuration of amplifier 22"
A configuration example 1 of the amplifier 22 will be described with reference to FIG. The amplifier 22 has a configuration for output correction. The output from the coupling TFT 440-r is input to the buffer amplifier 452 via the switch TFT 450 that is turned on / off by the signal φ01. On the other hand, one end of a correction capacitor 454 is connected to the input terminal of the buffer amplifier 452, and the other end of the correction capacitor 454 is connected to the ground GND via a voltage drop control capacitor 456.

  Further, the voltage VL is supplied to the input terminal of the buffer amplifier 452 via the TFT 460 that is turned on / off by the charging signal Charge. Further, the voltage VL is supplied to the middle point of the capacitors 454 and 456 by the TFT 462 that is turned on / off by the charging signal Charge, and the input side (the output terminal of the DAC) of the switch TFT 450 is connected by the TFT 470 that is turned on / off by the signal φ03. Furthermore, the output terminal of the buffer amplifier 452 is connected via a TFT 472.

  The operation of such a circuit will be described with reference to FIGS. 5A and 5B. First, when the TFTs 460 and 462 are turned on by the signal Charge, the input terminal of the buffer amplifier 452 and the midpoints of the capacitors 454 and 456 are set to the voltage VL. Further, in this state, the capacitors 430-r, 430-0, 430-1, and 430-2 are charged as described above to determine the charge amount, Charge falls, then Combine rises, An analog voltage Vin corresponding to the input data appears at the output terminal.

  Then, in step 1, the signal φ01 becomes H level with the Combine being at H level, and the switch TFT 450 is turned on. As a result, the input terminal of the buffer amplifier 452 is set to the output voltage Vin of the DAC 20.

  Next, in step 2, the signal φ02 is set to H level to turn on the TFT 472. As a result, the midpoint of the capacitors 454 and 456 is set to the output voltage Vout of the buffer amplifier 452. Although the buffer amplifier 452 operates so that the output voltage matches the input voltage, an error occurs due to the characteristics thereof, and this embodiment compensates for this. Here, if the error voltage in the buffer amplifier 452 is ΔV, it can be expressed as output voltage Vout = Vin + ΔV.

  In step 3, the signal φ02 is returned to the L level. As a result, the input end side (upper side) of the buffer amplifier 452 of the capacitor 454 is fixed to Vin, the capacitor 456 side (lower side) is fixed to Vout, and the capacitor 454 is charged with ΔV.

  In step 4, the signal φ01 is set to L level, and the switch TFT 450 is turned off. Here, when the switch TFT 450 is turned off, the gate potential is changed from the H level to the L level, so that the voltage at the input terminal of the buffer amplifier 452 slightly decreases due to the gate capacitance (Cgs) of the switch TFT 450. Here, the capacitor 454 is charged by ΔV, and the capacitor 456 is charged by Vout−GND. Therefore, the midpoint voltage of these capacitors 454 and 456 and the input terminal voltage of the buffer amplifier 452 cannot move so much. Assuming that the voltage dropped at the input terminal of the buffer amplifier 452 by turning off the switch TFT 450 is a, the voltage at the input terminal of the buffer amplifier 452 is Vin-a. Further, the voltage at the midpoint of the capacitors 454 and 456 is a voltage lower than a, but decreases according to a. If the lowering of the voltage at the middle point of the capacitors 454 and 456 is a ′, the voltage is Vin + ΔV−a ′.

  In step 5, the signal φ03 is set to the H level, and the midpoint voltage of the capacitors 454 and 456 is set to Vin. As a result, the midpoint voltage of the capacitors 454 and 456 changes by Vin− (Vin + ΔV−a ′). Accordingly, the input voltage of the buffer amplifier 452 also changes by the same amount to Vin−a + Vin−Vin−ΔV + a ′ and Vin−ΔV− (a−a ′). Although it depends on the setting of the capacitance values of the capacitors 454 and 456, a and a 'are originally close values and can be easily made substantially the same. Assuming that a = a ′, the input voltage of the buffer amplifier 452 is approximately Vin−ΔV. For this reason, when Vin is inputted, the output of the buffer amplifier 452 which has been Vout = Vin + ΔV becomes Vout≈Vin by the input being lowered by ΔV, and the error is compensated.

“Another configuration example of the amplifier 22”
FIG. 6 shows another circuit example for eliminating the output error of the buffer amplifier 452 in the amplifier 22.

  In this example, the output of the DAC 20 is supplied to the input terminal of the buffer amplifier 452 as it is, and a switch TFT 480 for connecting the output and input of the buffer amplifier 452 is provided.

  The switch TFT 480 is turned on by setting the signal Combine to H and outputting the corresponding voltage from the buffer amplifier 452 for a predetermined time, and then setting the signal φ to H level. As a result, the voltage on the output side of the buffer amplifier 452 can be brought close to the voltage on the input side, and an error in the output of the buffer amplifier 452 can be reduced.

  As shown in FIG. 6, the capacitor of the DAC 20 is connected to the input side of the buffer amplifier 452, and this is an input section capacitance. On the other hand, since the output of the buffer amplifier 452 is connected to the data line DL, the capacity of the data line DL exists as a load capacity. It is effective to turn on the switch TFT 480 after sufficient charging for the load capacity is completed. When the ratio (load capacity) / (input capacity), which is the ratio between the load capacity and the input section capacity, is 1 or less, the effect of turning on the switch TFT 480 is large, which is preferable. Further, the gate capacitance CS of the switch TFT 480 is preferably smaller than the input portion capacitance and the load capacitance, and is preferably 1/10 or less of both capacitances.

“Other configuration of lower bits of DAC 20”
FIG. 7 shows another configuration example of the lower bits of the DAC 20. In this example, Pre-Charge is used instead of the signal Combine.

  Corresponding to D2-D0, TFTs 410-2, 412-2, 410-1, 412-1, 410-0, 412-0 are respectively provided and either VH or VL is selected, and these are charge control transistors. It is supplied to one end side (upper side) of capacitors 430-2, 430-1, and 430-0 through 420-2, 420-1, and 420-0. Further, VL is directly supplied to the capacitor 430-r, and one end side (upper side) is always set to VL.

  The other ends (lower sides) of the capacitors 430-2, 430-1, 430-0, and 430-r are connected in common and serve as the output of the DAC 20.

  The TFTs 510-2 and 512-2 are connected in series between both ends of the capacitor 430-2, the TFTs 510-1 and 512-1 are connected in series between both ends of the capacitor 430-1, and between both ends of the capacitor 430-0. Is a series connection of TFTs 510-0 and 512-0, and a series connection of TFTs 510-r and 512-r is arranged between both ends of the capacitor 430-r. At the intermediate point between the series connection of TFTs 510-2 and 512-2, the series connection of TFTs 510-1 and 512-1, the series connection of TFTs 510-0 and 512-0, and the series connection of TFTs 510-r and 512-r , VL is supplied, and the signal Pre-Charge is supplied to the gates of these TFTs.

  In such a circuit, first, the signal Pre-Charge is set to the H level, so that both ends of all the capacitors 430-2, 430-1, 430-0, and 430-r are set to VL.

  Then, after setting the signal Pre-Charge to the L level, the charge control TFTs 420-2, 420-1, 420-0 are turned on, and the capacitors 430-2, 430 corresponding to VH or VL corresponding to the data D2-D0 are turned on. -1, 430-0 is supplied to one end side. As a result, the other ends of the capacitors 430-2, 430-1, and 430-0 supplied with VH try to shift, and the charge amount of each capacitor at that time is the capacitors 430-2, 430-1, and 430-. Since it is proportional to the capacitance value of 0, as in the case described above, the voltage at the output terminal is a voltage shifted from VL to VH by an amount corresponding to a value determined by D2-D0.

  In this configuration as well, the charge control TFTs 420-2, 420-1, and 420-0 have transistor sizes corresponding to the capacitance ratio of the capacitors 430-2, 430-1, and 430-0.

"Changeover switch 24"
The configuration of the changeover switch 24 is shown in FIG. The changeover switch 24 has a first changeover unit 24a and a second changeover unit 24b, which are used for normal display of 64 gradations, which are two standby signals of the WHITE signal and the BLACK signal, and the output of the DAC 20. Select and output one of the video signals.

  First, the first switching unit 24a is switched by a mode signal indicating either the normal mode or the standby mode (low power mode), and selects and outputs a normal display video signal in the normal mode.

  On the other hand, in the standby mode, the first switching unit 24a selects a standby signal. The output of the second switching unit 24 b is supplied to the input terminal of the standby signal of the first switching unit 24. The second switching unit 24b selects and outputs either the WHITE signal or the BLACK signal. Therefore, in the standby mode, either the WHITE signal or the BLACK signal selected by the second switching unit 24b is output via the first switching unit 24a.

  Here, the MSB (the fifth bit of 0-5 bits) signal in the 6-bit output of the SRAM 12 is supplied to the second switching unit 24b. In the standby mode, the display is a simple symbol or the like, and two types of display, white and black, are used. Either the white or black is determined by the fifth bit of the video data. This is because that. For example, if black is 000000 and white is 111111, the determination can be made by any bit. However, depending on the video data, the data of the entire range may not be used, and the determination may be made by an appropriate bit. That is, for each pixel, whether the data of the pixel is white or black is determined by appropriate 1 bit in the pixel data, and either the WHITE signal or the BLACK signal is selected by the second switching unit 24b. In this example, a predetermined bit of the SRAM 12 is supplied to the first switching unit 24a as a switching control signal, and the second switching unit 24a is switched by 1 or 0 of the bit.

  Thus, in the normal display mode, the normal video signal from the DAC 20 is supplied to the data line DL, and in the standby mode, either the WHITE signal or the BLACK signal is supplied to the data line DL. The

  Even in a full-color display device having RGB pixels, the display itself becomes white by supplying high luminance signals to all the pixels, and black display is achieved by supplying low luminance signals to all the pixels. Become. In addition, since each color pixel of RGB can be turned on / off, eight-color display of R, G, B, R + G, R + B, G + B, white and black is also possible.

  In the standby mode, a multi-gradation video signal for normal display is not necessary. Therefore, in this embodiment, by selecting a separately prepared WHITE signal or BLACK signal based on digital video data, the analog video signal is not used, and the operation of the DAC 20 and the amplifier 22 is stopped to reduce power consumption. Reduce. Note that the amplifier 22 is preferably turned off, and the DAC is also preferably turned off for the amplifier that generates the reference voltage. In this manner, in the standby mode, analog signal processing is not required, so that power saving can be achieved by completely stopping the operation of the analog circuit.

  Here, in the liquid crystal, so-called AC driving is performed to reverse the voltage application direction to the liquid crystal every predetermined period for the purpose of preventing burn-in. Therefore, when using normally black (black display when no voltage is applied) liquid crystal, the BLACK signal is a constant voltage similar to the supply electrode voltage, and the WHITE signal is separated from the common electrode every predetermined period. When using a normally white (white display when no voltage is applied) liquid crystal is used, the opposite signal is obtained.

  Here, in the case of normally white, as shown in FIG. 9, the WHITE signal is a signal of 1/2 VDD, and the BLACK signal is a signal that alternates between VSS and VDD every horizontal scan, and this voltage is Applied to the pixel electrode of the liquid crystal element. Note that the common electrode voltage VCOM is set to substantially the same voltage as the WHITE signal. As a result, the polarity of the video signal supplied to the black display pixel for each row of pixels (whether the voltage is higher or lower than VCOM) is inverted. In the next frame, since the polarity of the video signal for the corresponding row is inverted, the voltage application direction with respect to the liquid crystal is inverted every frame for each pixel that continues to display black.

  In particular, the dot inversion method that inverts the direction of the voltage applied to the liquid crystal for each dot in the above-described one row is preferable.

“Specific Circuit Configuration of Switch 24”
FIG. 10 shows a specific circuit configuration of the switch 24. The BLACK signal (LP_BLACK) is supplied to one end (drain or source) of the TFT 210, and the other end (source or drain) of the n-channel TFT 210 is connected to one end (source or drain) of the p-channel TFT 212. The other end (drain or source) of the p-channel TFT 210 is supplied with a WHITE signal (WHITE). The fifth bit (D5) of the video data is supplied to the gates of the TFTs 210 and 212. Accordingly, the TFT 210 is turned on when D5 is “1”, and the TFT 212 is turned on when D5 is “0”.

  A connection point between the TFT 210 and the TFT 212 is connected to one end of an n-channel TFT 214 and the other end of the TFT 214 is connected to the data line DL. The LP_ENB signal that is at the H level in the standby mode is supplied to the gate of the TFT 214. Accordingly, in the standby mode, the TFT 214 is turned on, and either the BLACK signal or the WHITE signal is supplied to the data line DL.

  A 64-gradation analog video signal supplied from the DAC 20 via the amplifier 22 is supplied to one end of an n-channel TFT 216, and the other end of the TFT 216 is connected to the data line DL. An RGB_ENB signal that is set to H level in the normal display mode is supplied to the gate of the TFT 216. Therefore, in the normal display mode, the TFT 216 is turned on, and a 64-gradation video signal is supplied to the data line DL.

  As described above, either the WHITE signal or the BLACK signal is selected by the video data D5, and either the video signal or the WHITE signal or the BLACK signal is selected by the LP_ENB signal and the RGB_ENB signal, and supplied to the data line DL. Is done.

"Precharge Configuration"
Further, FIG. 10 shows a configuration for precharging the data line DL. That is, an n-channel TFT 230 is arranged between the data lines DL, and adjacent data lines DL are connected by turning on the TFT 230. The TFT 230 is disposed between all data lines DL. An n-channel TFT 232 is disposed between the line supplying the WHITE signal and each data line DL. By turning on the TFT 232, the WHITE signal is supplied to the data line DL.

  The DSG signal is supplied to the gates of the two TFTs 230 and 232. Accordingly, by setting the signal DSG to the H level, both the TFTs 230 and 232 are turned on, the adjacent data lines DL are connected to each other, and the WHITE signal is supplied thereto.

  Here, the WHITE signal is a (1/2) VDD signal as shown in FIG. Therefore, each data line DL can be precharged to (1/2) VDD by setting the DSG signal to H level in the horizontal blanking period. Note that precharging is performed before data in one horizontal scanning period such as a horizontal blanking period is set in the data line DL.

  In particular, in the case of a dot inversion method in which the polarity of data to be described later is inverted between adjacent pixels (dots), the voltage value of the video signal set in the adjacent data line DL is in the opposite direction with the common electrode voltage VCOM as a boundary. ing. Therefore, by turning on the TFT 230 and connecting the adjacent data lines DL, the voltage becomes close to the common electrode voltage VCOM. That is, in the display of natural images and the like, the brightness of adjacent pixels is often close, and therefore, by connecting the data lines DL set to the display voltage of the adjacent pixels, there is no need to supply power from the outside. , Can be set to a voltage close to VCOM. For example, in the entire black display, the data lines DL are alternately set to VSS and VDD, and efficient precharging can be performed by connecting them.

  Further, in the present embodiment, a TFT 232 is provided, and each data line DL is set to (1/2) VDD. As a result, the power (charge amount) required for writing a video signal to the data line DL thereafter can be reduced, and power can be saved.

  In the example of FIG. 10, the TFTs 230 and 232 are turned on / off by the DSG signal of one control line and the TFTs 230 and 232 are turned on at the same timing. However, after the TFT 230 is turned on with the control lines separately, the TFT 232 is turned on. It is also suitable to do. The voltage supplied by the TFT 232 is (1/2) VDD, but may be any other voltage as long as it is close to the common electrode voltage VCOM.

  Further, when the TFT 230 is provided, the TFT 232 can be omitted. That is, by turning on the TFT 230, adjacent data lines DL can be connected to each other through the TFT 230, and the same effect can be obtained. Further, only one of the TFT 230 and the TFT 232 can be provided.

"Pixel circuit and dot inversion"
Here, it is preferable to provide two capacitor lines for one row and invert the voltages of the two capacitor lines for each frame with opposite polarities. This configuration will be described below.

  FIG. 11 shows a schematic configuration of a pixel circuit provided with two capacitor lines. The pixel circuit 1 is arranged in a matrix over the entire display area. The matrix arrangement may be a zigzag shape instead of a perfect lattice shape. The display may be monochrome or full color, and in the case of full color, the normal pixels are three colors of RGB, but it is also preferable to add pixels of a specific color including white as necessary.

  As shown in the drawing, one pixel circuit 1 has an n-channel pixel TFT 110 whose source is connected to the data line DL, a liquid crystal element 112 and a storage capacitor 114 connected to the drain of the pixel TFT 110. . A gate line GL arranged for each horizontal scanning line is connected to the gate of the pixel TFT 110.

  The liquid crystal element 112 is configured such that a pixel electrode individually provided for each pixel is connected to the drain of the pixel TFT 110, and a common electrode common to all the pixels is disposed opposite to the pixel electrode with the liquid crystal interposed therebetween. The common electrode is connected to the common electrode power source VCOM.

  In the storage capacitor 114, the extended portion of the semiconductor layer constituting the drain of the pixel TFT 110 is directly used as one electrode, and a part of the capacitor line SC formed so as to face the oxide film is a counter electrode. Note that the portion that becomes the electrode of the storage capacitor 114 may be separated from the portion of the pixel TFT 110 as another semiconductor layer, and both may be connected by metal wiring.

  Here, there are two capacitance lines SC, SC-A and SC-B, for one row (horizontal scanning line), and the storage capacitance of each pixel circuit is SC-A and SC-B in the horizontal scanning direction. Are connected alternately. In the pixel circuit shown in this figure, the storage capacitor 114 is connected to the capacitor line SC-A, and the storage capacitor 114 of the adjacent pixel is connected to the capacitor line SC-B.

  A vertical driver 120 is connected to the gate line GL, and the vertical driver 120 sequentially selects the gate lines GL one by one for each horizontal period and sets them to the H level. The vertical driver 120 has a shift register, receives a signal STV indicating the start of one vertical scanning period, sets the first stage of the shift register to the H level, and then shifts the H level one by one by a clock signal, for example. Thus, the gate lines GL of each horizontal scanning line are sequentially selected one by one and set to the H level. Here, for example, the H level of the gate line GL is the VDD potential, the L level is the VSS potential, and these power supply voltages VDD and VSS are supplied to the vertical driver 120, thereby the gate line GL as the output of the vertical driver. H level and L level are set.

  The SC driver 122 outputs two voltage levels to the two storage capacitor lines SC-A and SC-B.

  Although not shown, the display device is also provided with, for example, a horizontal driver, and controls line-sequential supply of the input video signal to the data line DL. That is, in this example, the horizontal driver outputs a sampling clock for each pixel in accordance with the clock of the video signal for each pixel, and the video signal (data signal) for one horizontal scanning line is turned on / off by this sampling clock. Latch. Then, a data signal for each pixel of one latched horizontal scanning line is output to the data line DL over one horizontal scanning period.

  Actually, there are three types of video signals, RGB, and each pixel in the vertical direction is one of the same color pixels of R, G, and B. Therefore, a data signal of any one of RGB is set in the data line DL.

  In the apparatus of this embodiment, a dot inversion AC application method is employed. That is, in each pixel (dot) in the horizontal scanning direction, a voltage applied to the pixel electrode of the liquid crystal element 112 is applied as a data signal having a polarity opposite to the voltage VCOM of the common electrode.

  The left side of FIG. 12 shows a data signal having the first polarity, and the hypotenuse of the triangle written as Vvideo indicates a data signal (write voltage) corresponding to the luminance. The data signal has a potential difference (dynamic range) of Vb from the black level to the white level, and the voltage applied to the pixel electrode after the voltage shift is white when the voltage is separated from VCOM, and is black when the voltage is close. It has become. Therefore, in this example, the black level is VCOM−Vb / 2 and the white level is VCOM + Vb / 2. In the adjacent pixels, as shown on the right side of FIG. 12, the second polarity is opposite to the first polarity, the black level is VCOM + Vb / 2, and the white level is VCOM−Vb / 2. ing.

  Then, as shown in FIG. 13, after the ON period to the pixel TFT 110 ends and data writing ends, the capacitance lines SC-A and SC-B shift by a predetermined voltage ΔVsc. In this example, a normally black vertical alignment (VA) type liquid crystal is used as the liquid crystal. For the pixel on the left side of FIG. 12, the capacitor line SC-A is connected, and Vsc is shifted in the higher voltage direction by ΔVsc. For the pixel on the right side of FIG. 12, the capacitor line SC-B is connected, and Vsc is shifted in the direction of decreasing the voltage by ΔVsc.

  As a result, as shown in FIG. 13, the data signal applied to the pixel electrode is shifted by a voltage corresponding to ΔVsc, and this is applied to VCOM. Here, ΔVsc is set to a voltage corresponding to the threshold voltage Vath at which the change in transmittance according to the applied voltage of the liquid crystal starts, and display by the liquid crystal element 112 is possible by the voltage after the shift. Become. The dynamic range of the data signal is set so that the shifted dynamic range is a potential difference from the black level to the white level in the display.

  In FIG. 12, Va (W) is the shift amount of the white level data signal, and Va (B) is the shift amount of the black level data signal, and these shift amounts are determined by ΔVsc. Vb is the potential difference (dynamic range) between the black level and the white level of the data signal, and Vb 'is the dynamic range after the shift.

"Overall operation"
The operation of taking video data in FIG. 1 into the SRAMs 16 and 18 will be described based on the timing chart of FIG. One horizontal scanning period includes a data period in which video data is supplied to the video line 10 (FIG. 1) and a horizontal blanking period (blanking period). The horizontal scanning period is synchronized by the horizontal synchronization signal Hsync. The dot clock Dotclock is a signal synchronized with one dot of video data, and the horizontal transfer clock XCKH (and CKH), which is a horizontal transfer clock having a half frequency, is used as the horizontal transfer clock, and the horizontal start signal STH is used as the horizontal transfer register. 14 (FIG. 1). Note that the STH transfer is performed in the horizontal transfer register 14 only during a period in which the video data is supplied by the enable signal ENB.

  STH is transferred to the first stage of the horizontal transfer register 14 as indicated by SR01 in FIG. 14, and thereafter sequentially transferred in the form of SR02 and SR03. In this example, the video data capturing is completed at 130 levels. Here, the video data is taken into the SRAM 16 (FIG. 1) by AND01a to AND130a. Here, AND01a is a signal that becomes H level in the latter half of SR01 obtained by AND (logical product) of SR01 and SR01a (the same signal as SR02), and corresponds to the video data of the first dot of the video data. Yes. Therefore, the first dot video data is taken into the first-stage SRAM 16 by the AND01a. One row of video data is taken into the corresponding SRAM 16 by AND01a to AND130a.

  In this example, the number of stages of the horizontal transfer register 14 is set to 133, and one line of video data captured in the SRAM 16 is transferred to the SRAM 18 by the SR 133.

  Next, the writing operation from the DAC 20 to the pixel circuit 100 will be described based on the timing chart of FIG.

  First, when the blanking period ends, one line of video data is set in the SRAM 18 as described above. Therefore, the DAC 22 performs digital-analog conversion, but the capacitor 430 must be charged for the lower 3 bits. Accordingly, the signal Charge is set to the H level and charging is started. After the charging is completed, Charge is set to L level and signal Combine is set to H level. Thereby, an analog video signal of 64 gradations is obtained at the output of the DAC 20.

  Note that the output correction processing of the amplifier 22 is performed as described above during the period in which the analog signal is output from the DAC 20. Here, the timing of the signals φ01 to φ03 used in the configuration of FIG. 4 is shown, which is the same as that shown in FIG. 5A.

  Further, the signal φ supplied to the gate of the switch TFT 480 in FIG. 6 becomes the H level at the same timing as the above φ3.

  On the other hand, in the switch 24, RGB_ENB is set to the H level during the period in which the Combine is at the H level, the analog video signal output from the amplifier 24 is supplied to the data line DL, and the pixel circuit 100 in the corresponding row outputs the analog video signal. take in. Note that RGB_ENB is prevented from changing the video signal on the data line DL by returning to the L level before the Combine.

  The gate line GL becomes H level in the data period, and in each pixel circuit 100, the gate line GL becomes H level in the end of the period in which RGB_ENB is H level, and the data voltage in the pixel circuit 100 is determined.

  On the other hand, in the blanking period, the signal DSG becomes H level, and each data line DL is precharged to (1/2) VDD. In addition, since FRP is inverted during the blanking period, the polarity of the reference voltage in the DAC 20 is inverted, and the polarity of the analog video data is inverted.

It is a figure which shows the structure for supplying the video data in the liquid crystal display device which concerns on embodiment to a pixel circuit. 2 is a diagram showing a configuration of a latch type level shift circuit (SRAM 16) and a latch circuit (SRAM 18) that latches an output of the SRAM 16. FIG. The configuration of the upper bit conversion of the DAC 20 is shown. 3 is a diagram illustrating a configuration example of lower-order bit conversion of DAC 20 and amplifier 22. FIG. 4 is a diagram for explaining the operation of a circuit of an amplifier 22. FIG. 4 is a diagram for explaining the operation of a circuit of an amplifier 22. FIG. FIG. 10 is a diagram illustrating another circuit example for eliminating an output error of the buffer amplifier 452 in the amplifier 22. It is a figure which shows the other structural example about the low-order bit of DAC20. 3 is a diagram showing a configuration of a changeover switch 24. FIG. It is a figure which shows the waveform of a WHITE signal and a BLACK signal. It is a figure which shows the structure for the precharge of a data line. It is a figure which shows schematic structure of a structure of the pixel circuit which provides two capacity | capacitance lines. It is a figure for demonstrating the voltage application state with respect to a liquid crystal. It is a figure which shows the waveform of various signals. It is a timing chart about video data taking-in. It is a timing chart about an analog video signal output.

Explanation of symbols

  10 video lines, 12 switches, 14 horizontal transfer registers, 22 amplifiers, 24 switches, 26 data lines.

Claims (4)

In a display device that performs display using an analog data signal obtained by digital-analog conversion of a digital video signal,
In standby mode, based on the digital video signal, a standby data signal smaller than the number of gradations of the digital video signal is selected, and in the normal display mode, the digital video signal is obtained by digital-analog conversion. A mode changeover switch for selecting and outputting the analog data signal indicating the display luminance of gradation;
In a standby mode, a display device that performs display without using the analog data signal. The display device according to claim 1,
The standby data signal is only two of white display data and black display data determined according to the value of the digital video signal,
A display device, further comprising a monochrome switching switch for selecting one of them according to a specific 1-bit value in the digital video signal. The display device according to claim 1 or 2,
A digital-to-analog converter for converting the digital video signal into digital-to-analog;
An amplifier that amplifies the output of this digital-analog converter;
Including
Supplying the output of the amplifier to the mode switch as the analog data signal;
In the standby mode, the digital analog converter and the amplifier are stopped. The display device according to claim 3,
The display device has a plurality of pixels arranged in a matrix,
A data line is provided corresponding to each pixel column, and a selection line is provided corresponding to each pixel row.
Each pixel has a switching element that is turned on / off by a selection signal of a selection line and captures a data line signal, a capacitor that holds a voltage according to the data line signal when the switching element is on, and is held in this capacitor A liquid crystal element to which a voltage is applied, and
The digital-to-analog converter outputs a digital-to-analog-converted signal by sequentially inverting the polarity with respect to the reference voltage for the digital video signal for each pixel in the row direction,
The display device, wherein the standby data signal includes a voltage obtained by alternately selecting a power supply voltage and a ground voltage every horizontal scanning period.