JP2007219091A - Driving circuit, electrooptical device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit capable of increasing the number of gradations without causing an increase in layout area nor deterioration in picture quality, and to provide an electrooptical device and electronic equipment. <P>SOLUTION: The driving circuit drives source lines that the electrooptical device has according to (p+q)-bit gradation data, and includes a reference voltage generating circuit which generates 2<SP>(p+q)</SP>kinds of reference voltages, 2<SP>p</SP>gradation voltage signal lines each supplied with one of the 2<SP>(p+q)</SP>kinds of reference voltages, 2<SP>p</SP>reference voltage switching circuits each for outputting one of adjacent voltages among 2<SP>q</SP>kinds of reference voltages to each gradation voltage signal line, an impedance converting circuit which drives a source line based upon one of 2<SP>p</SP>gradation voltage signal lines selected corresponding to data of high-order (p) bits of the gradation data, and a bypass circuit which is provided in parallel to the impedance converting circuit to bypass the impedance converting circuit. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a drive circuit, an electro-optical device, and an electronic apparatus.

  Conventionally, as a liquid crystal panel (electro-optical device) used in an electronic device such as a mobile phone, an active matrix using a simple matrix type liquid crystal panel and a switching element such as a thin film transistor (hereinafter referred to as TFT). A liquid crystal panel of the type is known.

  The simple matrix method has an advantage that the power consumption can be easily reduced as compared with the active matrix method, but has a disadvantage that it is difficult to increase the number of colors and display a moving image. On the other hand, the active matrix method has an advantage that it is suitable for multi-color and moving image display, but has a disadvantage that it is difficult to reduce power consumption.

  In recent years, in portable electronic devices such as mobile phones, there has been a growing demand for multicolor and moving image display in order to provide high-quality images. For this reason, an active matrix type liquid crystal panel has been used instead of the simple matrix type liquid crystal panel used so far.

In general, a drive signal for performing image display is subjected to gamma correction according to the gradation characteristics of the display device. Taking a liquid crystal device as an example, a gradation voltage corrected so as to realize an optimum transmittance of a pixel is output based on gradation data for performing gradation display by gamma correction. Then, the source line is driven based on this gradation voltage.
JP-A-7-306660

  However, in recent years, there has been an increasing demand for higher image quality of display images, and there is an increasing demand for multi-gradation for a drive circuit that drives a source line of an electro-optical device. In this case, it is necessary to supply more types of gradation voltages to the output buffers that drive the source lines of the plurality of source lines of the electro-optical device.

Generally, when a driving circuit is integrated on a semiconductor substrate, a configuration in which a plurality of output buffers are arranged along the long side direction of the semiconductor substrate is employed. Therefore, the gradation voltage signal line group is also arranged so as to extend in the long side direction of the semiconductor substrate. Therefore, when the number of gradation voltage signal lines is increased, the layout area in the short side direction of the semiconductor substrate intersecting the long side direction of the semiconductor substrate is increased. For example, if the number of bits of gradation data for each dot is 6, the number of gradation voltage signal lines is 64 (= 2 ⁶ ), but if the number of bits of gradation data is 8, the gradation voltage signal The number of lines becomes 256 (= 2 ⁸ ), and the layout area of the grayscale voltage signal line group increases 4 times (= 2 ^8-6 ) times.

  On the other hand, in Patent Document 1, in order to reduce the number of gradation voltage signal lines, a staircase voltage is generated, and a desired voltage is sampled from a plurality of voltages set in a staircase pattern to thereby obtain a pulse width. A technique for expressing a halftone by generating a modulation signal is disclosed. However, the gradation expression is limited to the pulse width modulation method, and there is a problem that it is difficult to improve the image quality when a larger number of gradations are required.

  In addition, it is difficult to set all the levels of a plurality of voltages set in a staircase shape with high accuracy, and even if the level can be set with high accuracy, the circuit scale becomes complicated. In particular, as the number of gradations increases and the voltage difference between the gradations decreases, it is difficult to generate a stepped voltage in which the level of each voltage is set with high accuracy as disclosed in Patent Document 1. Become.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to drive a circuit that can increase the number of gradations without deteriorating the image quality without increasing the layout area. To provide an electro-optical device and an electronic apparatus.

In order to solve the above problems, the present invention
(P + q) (p and q are natural numbers) A driving circuit for driving a source line of an electro-optical device based on gradation data of bits,
2 a reference voltage generation circuit for generating ^{(p + q)} types of reference voltages;
2 ^p gradation voltage signal lines in which any one of the 2 ^{(p + q)} types of reference voltages is supplied to each gradation voltage signal line;
The gradation voltage signal lines of the 2 ^p the gradation voltage signal line, and 2 ^p number of reference voltage switching circuit for outputting either a voltage of 2 ^q reference voltages of adjacent,
An impedance conversion circuit for driving the source line based on any reference voltage of the 2 ^p gradation voltage signal lines selected corresponding to the upper p-bit data of the gradation data;
A bypass circuit provided in parallel with the impedance conversion circuit, for bypassing the input and output of the impedance conversion circuit;
The impedance conversion circuit drives the source line based on the reference voltage output by each reference voltage switching circuit when the low-order q-bit data of the gradation data is the first value,
Thereafter, the output of the impedance conversion circuit is set to a high impedance state and the bypass circuit is set to a conductive state, and is selected by each reference voltage switching circuit corresponding to the lower q bits of the gradation data. The present invention relates to a drive circuit that supplies a reference voltage to the source line.

In the driving circuit according to the present invention,
A voltage selection circuit that selects any of the reference voltages of the 2 ^p gradation voltage signal lines based on upper p-bit data of the gradation data;
The impedance conversion circuit is
The source line can be driven based on the voltage selected by the voltage selection circuit.

In the driving circuit according to the present invention,
The bypass circuit is
Each bypass switch may include a 2 ^q pieces of bypass switch arranged in parallel with the impedance conversion circuit.

In the driving circuit according to the present invention,
Each bypass switch of the 2 ^q-number of the bypass switch,
In a period assigned to each bypass switch within a given driving period, the low-order q-bit data of the gradation data may be used to set the conductive state or the non-conductive state.

In the driving circuit according to the present invention,
The first value is
It may be a value when each bit data of the lower q bits of the gradation data is 0.

According to any one of the above-described inventions, the source line can be driven based on 2 ^{(p + q)} types of reference voltages using 2 ^p gradation voltage signal lines. Even so, it is possible to suppress an increase in the length in the short side direction of the chip in which the drive circuit is integrated, and to reduce the cost of the drive circuit.

  First, after the source line is driven by the impedance conversion circuit, the output of the impedance conversion circuit is set to a high impedance state so that the reference voltage from the reference voltage generation circuit is supplied to the source line as it is. The voltage level to be applied to the line can be set at high speed and with low consumption. In addition, each voltage level can be set with high accuracy.

Furthermore, compared with the case where a plurality of reference voltages are generated by resistance-dividing between the high-potential-side power supply voltage and the low-potential-side power supply voltage, each reference voltage deviation of 2 ^{(p + q)} types of reference voltages is 2 it can be suppressed between the voltage of the voltage and the lowest voltage of the highest potential of ^q reference voltages, consisting of 2 ^{(p + q)} type of each reference voltage of the reference voltage can be generated with high accuracy.

In the driving circuit according to the present invention,
The impedance conversion circuit is
A class B push-pull operational amplifier can be included.

  According to the present invention, by employing a so-called class B push-pull operational amplifier, the configuration can be simplified and the power consumption can be reduced.

The present invention also provides
A plurality of scan lines;
Multiple source lines,
A plurality of pixels;
A scanning line driving circuit for scanning the plurality of scanning lines;
The present invention relates to an electro-optical device including any one of the drive circuits described above that drives the plurality of source lines.

  According to the present invention, it is possible to provide an electro-optical device including a drive circuit that can increase the number of gradations without causing an increase in layout area and without degrading image quality.

  The present invention also relates to an electronic apparatus including the electro-optical device described above.

  According to the present invention, it is possible to provide an electronic apparatus to which an electro-optical device including a drive circuit that can increase the number of gradations without causing an increase in layout area and without degrading image quality.

The present invention also provides
(P + q) (p and q are natural numbers) A driving method for driving a source line included in an electro-optical device based on gradation data of bits,
The gradation voltage signal lines 2 ^p the gradation voltage signal line, and outputs one of the voltages of 2 ^{(p + q)} Type 2 ^q kinds of adjoining reference voltage of the reference voltage,
Driving the source line by an impedance conversion circuit based on a reference voltage of any one of the 2 ^p gradation voltage signal lines selected corresponding to upper p-bit data of the gradation data;
A voltage corresponding to (p + q) -bit gradation data among the 2 ^q kinds of reference voltages is output to each gradation voltage signal line of the 2 ^p gradation voltage signal lines,
The output of the impedance conversion circuit is set to a high impedance state, and the reference voltage of any one of the 2 ^p gradation voltage signal lines selected corresponding to the upper p-bit data of the gradation data is set as the reference voltage. This is related to the driving method supplied to the source line.

In the driving method according to the present invention,
The impedance conversion circuit is
Of the 2 ^q kinds of reference voltages, the source line can be driven based on a reference voltage corresponding to 0 in the lower q-bit data of the gradation data.

In the driving method according to the present invention,
Each period of 2 ^q-number of periods allocated within a given driving period, the reference voltages of the 2 ^q reference voltages can be output to the gradation voltage signal line.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Liquid Crystal Display Device FIG. 1 shows an outline of the configuration of an active matrix liquid crystal display device according to this embodiment. Here, an active matrix type liquid crystal display device will be described, but a drive circuit as a source driver in this embodiment can also be applied to a simple matrix type liquid crystal display device.

  The liquid crystal display device 10 includes a liquid crystal display (LCD) panel (display panel in a broad sense, electro-optical device in a broader sense) 20. The LCD panel 20 is formed on a glass substrate, for example. On this glass substrate, a plurality of gate lines (scanning lines) GL1 to GLM (M is an integer of 2 or more) arranged in the Y direction and extending in the X direction, and a source line arranged in the X direction and extending in the Y direction, respectively. (Data lines) SL1 to SLN (N is an integer of 2 or more) are arranged. The pixel region corresponds to the intersection position of the gate line GLm (1 ≦ m ≦ M, m is an integer, the same applies hereinafter) and the source line SLn (1 ≦ n ≦ N, n is an integer, the same applies hereinafter). (Pixel) is provided, and a thin film transistor (hereinafter abbreviated as TFT) 22 mn is disposed in the pixel region.

  The gate of the TFT 22mn is connected to the gate line GLn. The source of the TFT 22mn is connected to the source line SLn. The drain of the TFT 22mn is connected to the pixel electrode 26mn. Liquid crystal is sealed between the pixel electrode 26mn and the counter electrode 28mn facing the pixel electrode 26mn, thereby forming a liquid crystal capacitor (liquid crystal element in a broad sense) 24mn. The transmittance of the pixel changes according to the applied voltage between the pixel electrode 26mn and the counter electrode 28mn. The counter electrode voltage Vcom is supplied to the counter electrode 28mn.

  Such an LCD panel 20 includes, for example, a first substrate on which pixel electrodes and TFTs are formed and a second substrate on which counter electrodes are formed, and a liquid crystal as an electro-optical material is interposed between the two substrates. It is formed by enclosing.

  The liquid crystal display device 10 includes a source driver 30 (display driver in a broad sense, drive circuit in a broader sense) 30. The source driver 30 drives the source lines SL1 to SLN of the LCD panel 20 based on the gradation data.

  The liquid crystal display device 10 can include a gate driver (scan driver in a broad sense) 32. The gate driver 32 scans the gate lines GL1 to GLM of the LCD panel 20 within one vertical scanning period.

  The liquid crystal display device 10 can include a power supply circuit 100. The power supply circuit 100 generates voltages necessary for driving the source lines and supplies them to the source driver 30. The power supply circuit 100 generates, for example, power supply voltages VDDH and VSSH necessary for driving a source line of the source driver 30 and a voltage of a logic unit of the source driver 30.

  The power supply circuit 100 generates a voltage necessary for scanning the gate line and supplies it to the gate driver 32.

  Further, the power supply circuit 100 generates a counter electrode voltage Vcom. In accordance with the timing of the polarity inversion signal POL generated by the source driver 30, the power supply circuit 100 generates a common electrode voltage Vcom that periodically repeats the high potential side voltage VCOMH and the low potential side voltage VCOML on the LCD panel 20. Output to electrode.

  The liquid crystal display device 10 can include a display controller 38. The display controller 38 controls the source driver 30, the gate driver 32, and the power supply circuit 100 according to contents set by a host such as a central processing unit (hereinafter abbreviated as CPU) (not shown). For example, the display controller 38 sets an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the source driver 30 and the gate driver 32.

  In FIG. 1, the liquid crystal display device 10 is configured to include the power supply circuit 100 or the display controller 38, but at least one of these may be provided outside the liquid crystal display device 10. Good. Alternatively, the liquid crystal display device 10 may be configured to include a host.

  The source driver 30 may incorporate at least one of the gate driver 32 and the power supply circuit 100.

  Furthermore, some or all of the source driver 30, the gate driver 32, the display controller 38, and the power supply circuit 100 may be formed on the LCD panel 20. For example, in FIG. 2, a source driver 30 and a gate driver 32 are formed on the LCD panel 20. As described above, the LCD panel 20 includes a plurality of source lines, a plurality of gate lines, a plurality of switching elements connected to the gate lines of the plurality of gate lines, and a plurality of source lines. And a display driver for driving the source line. A plurality of pixels are formed in the pixel formation region 80 of the LCD panel 20.

2. Gate Driver FIG. 3 shows a configuration example of the gate driver 32 of FIG.

  The gate driver 32 includes a shift register 40, a level shifter 42, and an output buffer 44.

  The shift register 40 includes a plurality of flip-flops provided corresponding to the gate lines and sequentially connected. When the shift register 40 holds the start pulse signal STV in the flip-flop in synchronization with the clock signal CPV, the shift register 40 sequentially shifts the start pulse signal STV to the adjacent flip-flop in synchronization with the clock signal CPV. The clock signal CPV input here is a horizontal synchronizing signal, and the start pulse signal STV is a vertical synchronizing signal.

  The level shifter 42 shifts the voltage level from the shift register 40 to a voltage level corresponding to the liquid crystal element of the LCD panel 20 and the transistor capability of the TFT. As this voltage level, for example, a high voltage level of 20 V to 50 V is required.

  The output buffer 44 buffers the scanning voltage shifted by the level shifter 42 and outputs it to the gate line to drive the gate line.

3. Source driver (drive circuit)
FIG. 4 shows a block diagram of a configuration example of the source driver 30 of FIG. 1 or FIG.

  The source driver 30 includes an I / O buffer 50, a display memory 52, a line latch (grayscale data latch in a broad sense) 54, a grayscale voltage generation circuit 56, a DAC (Digital / Analog Converter) 58, and a drive unit 60. .

  For example, the gradation data D is input to the source driver 30 from the display controller 38. The gradation data D is input in synchronization with the dot clock signal DCLK and buffered in the I / O buffer 50. The dot clock signal DCLK is supplied from the display controller 38.

  The I / O buffer 50 is accessed by the display controller 38 or a host (not shown). The gradation data buffered in the I / O buffer 50 is written in the display memory 52. The gradation data read from the display memory 52 is output to the display controller 38 and the like after being buffered by the I / O buffer 50.

  The display memory (gradation data memory) 52 includes a plurality of memory cells provided corresponding to the output lines in which the memory cells are connected to the source lines. Each memory cell is specified by a row address and a column address. Each memory cell for one scan line is specified by a line address.

  The address control circuit 62 generates a row address, a column address, and a line address for specifying a memory cell in the display memory 52. The address control circuit 62 generates a row address and a column address when writing gradation data into the display memory 52. That is, the gradation data buffered in the I / O buffer 50 is written into the memory cell of the display memory 52 specified by the row address and the column address.

  The row address decoder 64 decodes the row address and selects a memory cell of the display memory 52 corresponding to the row address. The column address decoder 66 decodes the column address and selects a memory cell of the display memory 52 corresponding to the column address.

  When the gradation data is read from the display memory 52 and output to the line latch 54, the address control circuit 62 generates a line address. That is, the line address decoder 68 decodes the line address and selects a memory cell of the display memory 52 corresponding to the line address. Then, gradation data for one horizontal scan read from the memory cell specified by the line address is output to the line latch 54.

  The address control circuit 62 generates a row address and a column address when reading the gradation data from the display memory 52 and outputting it to the I / O buffer 50. That is, the gradation data held in the memory cell of the display memory 52 specified by the row address and the column address is read to the I / O buffer 50. The gradation data read to the I / O buffer 50 is extracted by the display controller 38 or a host (not shown).

  Therefore, in FIG. 4, the row address decoder 64, the column address decoder 66, and the address control circuit 62 function as a write control circuit that performs writing control of gradation data to the display memory 52. On the other hand, in FIG. 4, the line address decoder 68, the column address decoder 66, and the address control circuit 62 function as a readout control circuit that performs readout control of gradation data from the display memory 52.

  The line latch (gradation data latch) 54 latches the gradation data for one horizontal scan read from the display memory 52 at the change timing of the horizontal synchronization signal HSYNC. The line latch 54 includes a plurality of registers in which each register holds gradation data for one dot. The gradation data for one dot read from the display memory 52 is taken into each of the plurality of registers of the line latch 54.

A gradation voltage generation circuit (reference voltage generation circuit in a broad sense) 56 generates a plurality of gradation voltages in which each gradation voltage (reference voltage) corresponds to each gradation data. More specifically, the gradation voltage generation circuit 56 generates a plurality of gradation voltages corresponding to each gradation data, based on the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH. . More specifically, the gradation voltage generation circuit 56 generates 2 ^{(p + q)} types of gradation voltages based on gradation data of (p + q) (p and q are natural numbers) bits. Such a gradation voltage generation circuit 56 includes 2 ^p kinds of gradation voltages at the same time among the voltages of a plurality of divided nodes of the resistance circuit to which the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH are supplied at both ends. As output.

  The DAC 58 generates a gradation voltage corresponding to the gradation data output from the line latch 54 (more specifically, the upper p-bit data of the gradation data) for each output line that is the output of the drive unit 60. . More specifically, the DAC 58 outputs grayscale data (more specifically, one output line of the drive unit 60 output from the line latch 54 from a plurality of grayscale voltages generated by the grayscale voltage generation circuit 56. Specifically, the gradation voltage corresponding to the upper p-bit data) is selected, and the selected gradation voltage is output.

The DAC 58 includes voltage selection circuits DEC _{1 to} DEC _N provided for each output line. Each voltage selection circuit outputs one gradation voltage corresponding to the gradation data from among the plurality of gradation voltages from the gradation voltage generation circuit 56.

The driving unit 60 drives a plurality of output lines whose output lines are connected to the source lines of the LCD panel 20. More specifically, the drive unit 60 drives each output line based on the gradation voltage output for each output line by the voltage selection circuit of the DAC 58. The drive unit 60 includes output circuits OUT _{1 to} OUT _N provided for each output line. Each output circuit drives the source line based on the gradation voltage from each voltage selection circuit. Each output circuit can be constituted by an operational amplifier or the like connected in a voltage follower.

  FIG. 5 shows an example of a layout image when the source driver is integrated on the semiconductor substrate. The X direction and Y direction in FIG. 5 are the same as those in FIG.

  The X direction, which is the arrangement direction of the source lines SL1 to SLN extending in the Y direction, is mounted on the LCD panel 20 so that each part of the source driver 30 is the long side direction of the chip 90 integrated on the semiconductor substrate. . Therefore, the Y direction becomes the short side direction of the chip 90.

In such a chip 90, each of the output circuits OUT _{1 to} OUT _N of the drive unit 60 of FIG. 4 is placed in a region near the end of the chip 90 where the chip 90 is connected to the source lines SL1 to SLN. It will be arranged along the direction. The gradation voltage signal line group 92 for transmitting the gradation voltage is provided in the long side direction of the chip 90 in order to supply the gradation voltage corresponding to the gradation data to each of the output circuits OUT _{1 to} OUT _N. It is arranged to extend.

At this time, in order to increase the length of the grayscale voltage signal line group and disperse the load capacitance, the grayscale voltage generation circuit 56 is provided in the central portion of the chip 90, and the length of the chip 90 extends from the central portion of the chip 90. The grayscale voltage signal line groups 92 ₁ and 92 ₂ are arranged so as to extend in opposite directions along the side direction. Then, in order to shorten the length of the word line of the display memory 52 which extends in the longitudinal direction of the chip 90 (bit line), by dividing the display memory 52, two display memory block 52 _1, 52 ₂ chip 90 A logic unit 94 is provided at the center of the circuit. The logic unit 94 includes at least one of the address control circuit 62, the column address decoder 66, the row address decoder 64, and the line address decoder 68 of FIG.

  Here, a configuration example of the gradation voltage generating circuit, the DAC, and the driving unit integrated in the chip 90 illustrated in FIG. 5 will be described.

  FIG. 6 shows a configuration example of the gradation voltage generating circuit, the DAC, and the driving unit in the comparative example of the present embodiment. In FIG. 6, it is assumed that the gradation data is 6 bits. 6 shows a portion for driving the source lines SL1 to SLn in the source lines SL1 to SLN in FIG. 5, the portion for driving the source lines SL (n + 1) to SLN is also arranged in the central portion of the chip 90. This is the same except that the direction in which the grayscale voltage signal line extends with respect to the grayscale voltage generation circuit is opposite to that in FIG.

  The grayscale voltage generation circuit 300 in the comparative example includes a resistance circuit 310. This gradation voltage generation circuit 300 is disposed in the gradation voltage generation circuit 56 of FIG. A high potential side power supply voltage VDDH and a low potential side power supply voltage VSSH are supplied to both ends of the resistor circuit 310. The resistance circuit 310 has a plurality of divided nodes for outputting a voltage obtained by resistance-dividing the voltages at both ends, and outputs the voltage of each divided node as a gradation voltage. By changing the resistance-divided voltage, it can be output as a gamma-corrected gradation voltage. The gradation voltage generation circuit 300 outputs each gradation voltage of the gradation voltages V0 to V63 to each gradation voltage signal line of the gradation voltage signal lines GVL0 to GVL63.

Gradation voltage signal line group comprising a gray scale voltage signal line GVL0~GVL63 is commonly connected to the voltage select circuit _DEC 1 _{~DEC n.} The voltage selection circuits DEC _{1 to} DEC _N have the same configuration. Each voltage selection circuit receives 6-bit gradation data D0 to D5 and inverted data XD0 to XD5 of each bit from the line latch. Then, one of the gradation voltages V0 to V63 is output to each output circuit corresponding to the gradation data D0 to D5 and the inverted data XD0 to XD5. The voltage selection circuit DEC _j (1 ≦ j ≦ n, j is an integer) receives the gradation data from the line latch and supplies the gradation voltage to the output circuit OUT _j . Therefore, the grayscale voltage signal line group extends in the X direction (see FIG. 5), which is the arrangement direction of the source lines.

FIG. 7 and FIG. 8 are explanatory diagrams of configuration examples of the voltage selection circuit DEC ₁ .

In Figure 7, the voltage selection circuit DEC _1, shows an example constituted by a so-called ROM (Read Only Memory). In this case, as shown in FIG. 8, a transistor Qa-b is provided at the intersection of the gradation voltage signal line GVLi to which the gradation voltage Vi is supplied and the 1-bit data line Da of the gradation data. It is done.

  Actually, the transistor Q (a + 1) -b is also provided at the intersection of the gradation voltage signal line GVLi and the 1-bit data line Da + 1 of the gradation data. Then, as shown in FIG. 8, the channel region of the transistor Q (a + 1) -b is formed by ion implantation so that the channel region is always in a conductive state. Therefore, the transistor Qa-b operates as a so-called switch element, and the transistor Q (a + 1) -b is a normally-on switch element.

  Thereby, the ROM data can be changed only by so-called mask exchange, and the layout area can be reduced.

Thus, any one of the gradation voltages V0 to V63 selected by the voltage selection circuit DEC _j based on the gradation data D0 to D5 and its inverted data XD0 to XD5 is supplied to the output circuit OUT _j . Is done. 6, the output circuit OUT _j includes a voltage-follower-connected operational amplifier, drive signal impedance conversion by the operational amplifier is adapted to be supplied to the source line SL _j.

  Incidentally, when the number of gradations increases in the comparative example as shown in FIG. 6, the number of gradation voltage signal lines also increases. For example, when the gradation data is increased from 6 bits to 8 bits, the number of gradation voltage signal lines increases from 64 to 256. That is, in FIG. 6, there is a problem that the layout area is increased by the increase in the wiring area of the gradation voltage signal line increased four times, and the length of the chip 90 in the short side direction becomes long.

  Therefore, in the present embodiment, by adopting the following configuration, even when the number of gradations is increased, an increase in layout area can be suppressed and cost reduction of the source driver can be realized. It is like that.

  FIG. 9 shows a configuration example of the gradation voltage generation circuit 56, the DAC 58, and the drive unit 60 in the present embodiment. In FIG. 9, the same parts as those in FIG. 4 or FIG. 9 shows a portion for driving the source lines SL1 to SLn in the source lines SL1 to SLN in FIG. 5, the portion for driving the source lines SL (n + 1) to SLN is also arranged in the central portion of the chip 90. This is the same except that the direction in which the grayscale voltage signal line extends with reference to the grayscale voltage generation circuit is the opposite direction to that of FIG.

In the comparative example shown in FIG. 6, ²⁶ kinds of gradation voltages corresponding to 6-bit gradation data are generated, and each gradation voltage is supplied to each of the ²⁶ gradation voltage signal lines via each gradation voltage signal line. It was supplied to the selection circuit _DEC 1 _{~DEC n.} On the other hand, in this embodiment, 2 ^{(p + q)} types of gradation voltages corresponding to (p + q) (p, q are natural numbers) bit gradation data are generated, and each gradation voltage is set to 2 ^p gradations. The voltage selection circuits DEC _{1 to} DEC _N (voltage selection circuits DEC _{1 to} DEC _{n in} FIG. 9) can be supplied via the respective gradation voltage signal lines of the voltage signal lines. That is, when the 6, q and 2 p, 8 (= p + q ) despite the grayscale data bits, each floor of each gradation voltage of 2 ^eight gradation voltage 2 ^six gradation voltage signal line The voltage selection circuits DEC _{1 to} DEC _n are supplied via the regulated voltage signal line.

  In FIG. 9, the gradation voltage generation circuit (reference voltage generation circuit) 56 includes a resistance circuit 57. This gradation voltage generation circuit 56 is arranged in the portion of the gradation voltage generation circuit 56 of FIG. A high potential side power supply voltage VDDH and a low potential side power supply voltage VSSH are supplied to both ends of the resistance circuit 57. The resistance circuit 57 has a plurality of divided nodes for outputting a voltage obtained by resistance-dividing the voltages at both ends, and outputs the voltage of each divided node as a gradation voltage (reference voltage). By changing the resistance-divided voltage, it can be output as a gamma-corrected gradation voltage.

In such a configuration, when the number of bits of the gradation data is (p + q), the gradation voltage generation circuit 56 can generate each gradation voltage of 2 ^{(p + q)} kinds of gradation voltages at each divided node. it can. Gray-scale voltage generating circuit 56 further includes a first through gradation voltage switching circuit of the ^{2 p} (reference voltage switching circuit of the first to ^{2 p) VSEL-1~VSEL-2} p. The first to gradation voltage switching circuit of the gradation voltage switching circuit ^{VSEL-1~VSEL-2 p} of the ^{2 p} is the gradation voltage signal line, ² adjacent ^q types of one of the voltage of gray voltages To switch the output. That is, each gradation voltage switching circuit is provided for every 2 ^q divided nodes. Each division nodes, the resistor circuit 57 is generated, 2 ^q types of gray scale voltages adjacent to each other are outputted.

The gradation voltage switching circuit, based on the grayscale voltage switching control signal, and outputs either of the two voltages of ^q divided nodes each gradation voltage signal line. Thus, in Figure 9, each gradation voltage switching circuit, the resistance circuit 57 is generated, is provided for each 2 ^two divided nodes 2 ^two gray scale voltages adjacent to each other are outputted. Alternatively, each gradation voltage switching circuit is provided corresponding to each gradation voltage signal line of 2 ^p gradation voltage signal lines.

Such gradation voltage switching circuit, based on the grayscale voltage switching control signal, outputs one of the voltages of the two ^two-division nodes each gradation voltage signal line. Therefore, the number of gradation voltage signal lines is two ^six, the same as the comparative example shown in FIG. For example, the first gradation voltage switching circuit VSEL-1 is provided corresponding to four divided nodes to which the adjacent gradation voltages V0 to V3 are output, and based on the gradation voltage switching control signal, Any one of the gradation voltages V0 to V3 is output to the gradation voltage signal line GVL0. The second gradation voltage switching circuit VSEL-2 is provided corresponding to four divided nodes from which the adjacent gradation voltages V4 to V7 are output, and based on the gradation voltage switching control signal, Any one of the gradation voltages is output to the gradation voltage signal line GVL1.

Gradation voltage signal line group comprising a gray scale voltage signal line GVL0~GVL63 is commonly connected to the voltage select circuit _DEC 1 _{~DEC n.} The voltage selection circuits DEC _{1 to} DEC _N have the configuration described with reference to FIGS. 6-bit gradation data D0 to D5 and inverted data XD0 to XD5 are input to the voltage selection circuit shown in FIG. On the other hand, the upper 6 bits of gradation data D2 to D7 and the inverted data XD2 to XD7 thereof are input to the voltage selection circuit shown in FIG.

  Each voltage selection circuit outputs the voltage of one of the gradation voltage signal lines GVL0 to GVL63 corresponding to the upper 6 bits of gradation data D2 to D7 and the inverted data XD2 to XD7. Output to each output circuit.

  FIG. 10 is a block diagram showing a configuration example of the first gradation voltage switching circuit VSEL-1 in FIG.

  The first grayscale voltage switching circuit VSEL-1 grayscales any one of the grayscale voltages V0 to V3, which are the voltages of the divided nodes of the resistor circuit 57, based on the grayscale voltage switching control signals XDACON0 to XDACON3. Output to the voltage signal line GVL0.

  The first grayscale voltage switching circuit VSEL-1 has one end connected to the grayscale voltage signal line GVL0 and the other end divided to output grayscale voltages V0 to V3 among the plurality of divided nodes of the resistor circuit 57. Switch elements GSW0 to GSW3 connected to the.

  The switch element GSW0 is on / off controlled by a gradation voltage switching control signal XDACON0. The switch element GSW1 is on / off controlled by a gradation voltage switching control signal XDACON1. The switch element GSW2 is on / off controlled by a gradation voltage switching control signal XDACON2. The switch element GSW3 is ON / OFF controlled by a gradation voltage switching control signal XDACON3.

In Figure 10, but showing the first structure of the gradation voltage switching circuit VSEL-1, configuration of the gradation voltage switching circuit VSEL2～VSEL2 ^p of second to ^{2 p} also first gradation voltage switching circuit VSEL- The configuration is the same as that of FIG. Then, the gradation voltage switching circuit VSEL2～VSEL2 ^p of second to ^{2 p} is also controlled by the gradation voltage switching control signal XDACON0～XDACON3.

  Such gradation voltage switching control signals XDACON0 to XDACON3 are generated in a control circuit (not shown) of the source driver 30.

  FIG. 11 is an explanatory diagram of the gradation voltage switching control signals XDACON0 to XDACON3.

  In the present embodiment, a DAC driving period in which the gradation voltage selected by the DAC 58 bypasses the impedance conversion circuit and is supplied to the source lines SL1 to SLN as it is is provided within the driving period of the source driver 30.

  Each of the gradation voltage switching control signals XDACON0 to XDACON3 sets the switch element to be controlled to the conductive state when it is at the L level, and sets the switch element to be controlled to the non-conductive state when it is at the H level. . Then, within the DAC drive period, the gradation voltage switching control signal is controlled to be L level during the period assigned to the gradation voltage switching control signals XDACON0 to XDACON3.

In FIG. 9, the voltage of the gradation voltage signal line selected by the voltage selection circuit is supplied to the output circuit. In FIG. 9, the output circuit includes an impedance conversion circuit for driving the source line, and is one of 2 ^p grayscale voltage signal lines selected corresponding to the upper p-bit data of the grayscale data. The source line is driven based on the gradation voltage. Such an impedance conversion circuit is realized by an operational amplifier connected to a voltage follower. Since the configuration of the operational amplifier connected to the voltage follower is known, the description thereof is omitted.

The output circuit of this embodiment includes a bypass circuit that is provided in parallel with an operational amplifier as an impedance conversion circuit and bypasses the input and output of the operational amplifier. In other words, the output circuit _OUT 1 to OUT output circuit of _{N OUT k (1 ≦ k ≦} N, k is an integer), an operational amplifier OP _k which is voltage follower connected to operate as an impedance conversion circuit, of the operational amplifier OP _k and a bypass circuit BPS _k for bypassing an input and an output. For example, the output circuit OUT ₁ includes a voltage follower-connected operational amplifier OP ₁ that operates as an impedance conversion circuit, and a bypass circuit BPS ₁ for bypassing the input and output of the operational amplifier OP ₁ .

  In each bypass circuit, the conduction state between the input and output of the operational amplifier constituting the impedance conversion circuit is based on the lower-order q (q = 2 in FIG. 9) bit data of the gradation data and the gradation voltage switching control signal. The non-conducting state switching control is performed.

  In such a configuration, the voltage follower connection is made based on the gradation voltage output by each gradation voltage switching circuit when the low-order q-bit data of the gradation data is 0 (predetermined value, first value). The operational amplifier (impedance conversion circuit) drives the source line. After that, the operation of the operational amplifier is stopped, the output is set to the high impedance state, and the bypass circuit is set to the conductive state, and is selected by the gradation voltage switching circuit corresponding to the lower q bit data of the gradation data. Is supplied to the source line as it is.

FIG. 12 shows a configuration example of the output circuit OUT ₁ .

The bypass circuit BPS ₁ includes 2 ^q bypass switches in which each bypass switch is provided in parallel with an operational amplifier OP ₁ (in a broad sense, an operational amplifier circuit and an impedance conversion circuit). Therefore, when q is 2, the bypass circuit BPS ₁ includes four bypass switches BSW1 to BSW4.

The bypass circuit BPS ₁ is controlled based on bypass control signals DACcnt0 to DACcnt3. Bypass switch BSW1 constituting such bypass circuit BPS ₁ is on-off controlled by the bypass control signal DACcnt0. Similarly, the bypass switch BSW2 is ON / OFF controlled by a bypass control signal DACcnt1. Similarly, the bypass switch BSW3 is on / off controlled by a bypass control signal DACcnt2. Similarly, the bypass switch BSW4 is ON / OFF controlled by a bypass control signal DACcnt3.

  Such bypass control signals DACcnt0 to DACcnt3 are generated based on the lower-order q-bit data of the gradation data and the gradation voltage switching control signal.

  FIG. 13 is an explanatory diagram of the bypass control signals DACcnt0 to DACcnt3.

  FIG. 13 shows an example in which q is 2 as shown in FIG. The circuit shown in FIG. 13 is built in a control circuit (not shown) of the source driver 30.

  The bypass control signal DACcnt0 is generated based on the lower two bits of data D0 and D1 of the gradation data and the gradation voltage switching control signal XDACON0. More specifically, the bypass control signal DACcnt0 is at the H level when, for example, both the lower 2 bits of the gradation data D0 and D1 are “0” and the gradation voltage switching control signal XDACON0 is at the L level. Is generated as follows.

  The bypass control signal DACcnt1 is generated based on the lower two bits of data D0 and D1 of the gradation data and the gradation voltage switching control signal XDACON1. More specifically, the bypass control signal DACcnt1 is, for example, H2 when the low-order 2 bits data D0 of the gradation data is “1” and D1 is “0” and the gradation voltage switching control signal XDACON1 is at the L level. Generated to be level.

  The bypass control signal DACcnt2 is generated based on the lower two bits of data D0 and D1 of the gradation data and the gradation voltage switching control signal XDACON2. More specifically, the bypass control signal DACcnt0 is, for example, H2 when the lower 2 bits of data D0 are “1”, D1 is “1”, and the gradation voltage switching control signal XDACON2 is at L level. Generated to be level.

  The bypass control signal DACcnt3 is generated based on the lower two bits of data D0 and D1 of the gradation data and the gradation voltage switching control signal XDACON3. More specifically, the bypass control signal DACcnt0 is at the H level when, for example, both the lower 2 bits of the gradation data D0 and D1 are “1” and the gradation voltage switching control signal XDACON3 is at the L level. Is generated as follows.

In FIG. 13, the bypass control signals DACcnt0 to DACcnt3 are masked by the operational amplifier control signal so that the output of the operational amplifier of the output circuit does not change during the OP amplifier drive period set to the high impedance state but changes only during the DAC drive period. To be controlled. In Figure 13, the mask control by the operational amplifier control signal OPC ₁ for controlling the operation of the operational amplifier OP ₁ of the output circuit OUT _1.

  The bypass switch BSW1 of FIG. 12 is set to a conductive state when the bypass control signal DACcnt0 is at the H level, and is set to a nonconductive state when the bypass control signal DACcnt0 is at the L level.

  The bypass switch BSW2 is set to a conductive state when the bypass control signal DACcnt1 is at an H level, and is set to a non-conductive state when the bypass control signal DACcnt1 is at an L level.

  The bypass switch BSW3 is set to a conductive state when the bypass control signal DACcnt2 is at an H level, and is set to a non-conductive state when the bypass control signal DACcnt2 is at an L level.

  The bypass switch BSW4 is set to a conductive state when the bypass control signal DACcnt3 is at an H level, and is set to a non-conductive state when the bypass control signal DACcnt3 is at an L level.

  Therefore, only one of the bypass control signals DACcnt0 to DACcnt3 is set to the H level in the DAC driving period provided within one normal driving period of the source line. Further, in the low power consumption mode, by fixing the gradation voltage switching control signals XDACON0 to XDACON3 to the H level, the bypass control signals DACcnt0 to DACcnt3 can be set to the L level, and unnecessary power consumption can be avoided. .

The configuration of the bypass circuit BPS ₁ is not limited to that shown in FIG. Further, the bypass control signals DACcnt0 to DACcnt3 are not limited to those generated by the circuit shown in FIG.

FIG. 12 shows a configuration example of the output circuit OUT ₁ , but the same applies to the output circuits OUT _{2 to} OUT _N.

  FIG. 14 schematically shows an example of a change in the gradation voltage signal line GVL0.

  FIG. 14 shows an example of the voltage change of the gradation voltage signal line GVL0 when the lower two bits of data D0 and D1 of the gradation data are “0” and “1”. That is, in the DAC drive period, only the bypass control signal DACcnt1 changes to H level, and the bypass control signals DACcnt0, DACcnt2, and DACcnt3 remain at L level.

  In the DAC driving period, as shown in FIG. 11, each of the gradation voltage switching control signals XDACON0 to XDACON3 is sequentially turned on. Accordingly, the first grayscale voltage switching circuit VSEL-1 sequentially switches the grayscale voltages V0 to V3, which are the voltages of the divided nodes of the resistance circuit 57, and outputs them to the grayscale voltage signal line GVL0. Similarly, for the other gradation voltage signal lines GVL1 to GVL63 excluding the gradation voltage signal line GVL0 in the gradation voltage signal line group, four adjacent gradation voltages are sequentially switched and output.

The voltage selection circuits DEC _{1 to} DEC _N are selected from the upper 6 (= p) of the 8 (= p + q) -bit gradation data among the gradation voltage signal lines GVL 0 to GVL 63 whose voltage level changes in the DAC driving period. ) One gradation voltage signal line corresponding to bit gradation data is selected, and the voltage of the gradation voltage signal line is output to the output circuit.

For example, it is assumed that 8-bit gradation data D0 to D7 corresponding to the output circuit OUT ₁ is “10000000”. In this case, corresponding to the upper 6 bits of data D2~D7 of grayscale data, the voltage of the gradation voltage signal line GVL0 is outputted to the output circuit OUT _1. Since the bypass control signal DACcnt1 changes to H level, the output circuit OUT _1, so that the voltage supply of the source line SL1 is performed using a gray-scale voltage V1.

FIG. 15 shows a timing chart of an operation example of the output circuit OUT ₁ .

Output circuit OUT ₁ is in one horizontal scanning period defined by the horizontal synchronization signal HSYNC, it is possible to drive the source line SL1 based upon the 8-bit grayscale data. One horizontal scanning period includes an OP amplifier driving period and a DAC driving period provided after the OP amplifier driving period.

  First, in the OP amplifier driving period, only the gradation voltage switching control signal XDACON0 among the gradation voltage switching control signals XDACON0 to XDACON3 is set to the L level, and the gradation voltage switching control signals XDACON1 to XDACON3 remain at the H level. . That is, forcibly, when the lower 2 (= q) bit data of the gradation data is “00” (first value), a predetermined gradation voltage (gradation voltage switching circuit VSEL1) is generated by each gradation voltage switching circuit. In this case, the gradation voltage V0 is output, and in the case of the gradation voltage switching circuit VSEL2, the gradation voltage V4) is output. Generation of such a gradation voltage switching control signal is performed in a control circuit (not shown) of the source driver 30.

  As shown in FIG. 13, the bypass control signals DACcnt0 to DACcnt3 remain at the L level.

Therefore, in the OP amplifier driving period, the operational amplifier OP ₁ of the output circuit OUT ₁ has the first gradation when the lower 2 (= q) bit data of the gradation data is “00” (first value). The source line SL1 can be driven based on the gradation voltage V0 output by the voltage switching circuit VSEL-1.

Thereafter, in the DAC drive period, the operational amplifier control signals OPC _{1 to} OPC _N (in FIG. 15, the operational amplifier control signal OPC ₁ ) that controls the operation of the operational amplifiers OP _{1 to} OP _N are set to the L level. Then, each of the gradation voltage switching control signals XDACON0 to XDACON3 sequentially changes to the L level.

Here, when the output circuit OUT ₁ lower two bits of data D0, D1 of the gradation data corresponding to the "00", the DAC drive period, only the bypass control signal DACcnt0 changes to H level. Thus, OP in amplifier drive period, the voltage level of the source line SL1 that has reached approximately the voltage level of the gray scale voltages V0 by the operational amplifier OP ₁ is, in DAC drive period, the original gradation voltage V0 through the bypass switch BSW1 The voltage level can be adjusted with high accuracy.

Further, when the output circuit OUT ₁ lower two bits of data D0, D1 of the gradation data corresponding to the "01", the DAC drive period, only the bypass control signal DACcnt2 changes to H level. Thus, OP in amplifier drive period, the voltage level of the source line SL1 that has reached approximately the voltage level of the gray scale voltages V0 by the operational amplifier OP ₁ is, in DAC drive period, the original gradation voltage V2 through the bypass switch BSW1 The voltage level can be adjusted with high accuracy.

Thus, it is possible to correct the output error caused by manufacturing variations or the like of the operational amplifier OP _1.

As described above, each output circuit can drive a source line based on 2 ^{(p + q)} types of gradation voltages using 2 ^p gradation voltage signal lines. Therefore, even when the number of gradations is increased, the length of the chip in the short side direction can be suppressed, and the cost of the source driver can be reduced.

  First, after the source line is driven by an operational amplifier with a large current consumption, the operation of the operational amplifier is stopped and the gradation voltage from the gradation voltage generation circuit 56 is supplied to the source line as it is. The voltage level to be applied to the source line can be set at high speed and with low consumption. In addition, each voltage level can be set with high accuracy.

  Therefore, even when an operational amplifier is used as an impedance conversion circuit that charges a source line at high speed or discharges charge from the source line at high speed, so-called class AB push-pull operation is performed. It is not necessary to employ an amplifier, and by adopting a so-called class B push-pull operation operational amplifier, the configuration can be simplified and the power consumption can be reduced.

Further, in consideration of the case where the gradation voltages of 2 ^{(p + q)} types of gradation voltages supplied to the gradation voltage signal line group are generated with high accuracy, the accuracy of each of the 2 ^{(p + q)} types of gradation voltages is high. A configuration for generating a voltage is required. In contrast, the in the present embodiment, 2 ^q kinds of gradation voltages gradation voltage switching circuit outputs the gradation voltage signal line is shifted between the high-potential-side power supply voltage VDDH and the low potential-side power supply voltage VSSH Instead, there is a shift between the highest potential and the lowest potential of the ^2q kinds of gradation voltages. For example, the gradation voltages V0 to V3 output from the first gradation voltage switching circuit VSEL-1 can be accurately generated by the resistor circuit 57, so that the gradation voltages V1 and V2 are shifted. However, the potential does not become higher than the gradation voltage V0 or lower than the gradation voltage V3. Therefore, according to the configuration of the present embodiment, each gradation voltage of 2 ^{(p + q)} types of gradation voltages can be generated with high accuracy.

4). Electronic Device FIG. 16 shows a block diagram of a configuration example of an electronic device in the present embodiment. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device. In FIG. 16, the same parts as those in FIG. 1 or FIG.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies image data captured by the CCD camera to the display controller 38 in the YUV format.

  Mobile phone 900 includes LCD panel 20. The LCD panel 20 is driven by a source driver 30 and a gate driver 32. The LCD panel 20 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels.

  The display controller 38 is connected to the source driver 30 and the gate driver 32, and supplies gradation data in RGB format to the source driver 30.

  The power supply circuit 100 is connected to the source driver 30 and the gate driver 32 and supplies a driving power supply voltage to each driver. Further, the counter electrode voltage Vcom is supplied to the counter electrode of the LCD panel 20.

  The host 940 is connected to the display controller 38. The host 940 controls the display controller 38. The host 940 can supply the gradation data received via the antenna 960 to the display controller 38 after demodulating the modulation / demodulation unit 950. The display controller 38 displays on the LCD panel 20 by the source driver 30 and the gate driver 32 based on the gradation data.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the LCD panel 20 based on operation information from the operation input unit 970.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

1 is a diagram illustrating an outline of a configuration of a liquid crystal display device according to an embodiment. The figure which shows the outline | summary of the other structure of the liquid crystal display device in this embodiment. The block diagram of the structural example of the gate driver of FIG. FIG. 2 is a block diagram of a configuration example of a source driver in FIG. 1. The figure which shows an example of the layout image when a source driver is integrated on the semiconductor substrate. The figure of the structural example of the gradation voltage generation circuit, DAC, and drive part in the comparative example of this embodiment. Explanatory drawing of the structural example of a voltage selection circuit. FIG. 8 is an explanatory diagram of a configuration example of the voltage selection circuit of FIG. 7. The figure of the structural example of the gradation voltage generation circuit in this embodiment, DAC, and a drive part. FIG. 10 is a block diagram of a configuration example of the first gradation voltage switching circuit VSEL-1 in FIG. 9; Explanatory drawing of a gradation voltage switching control signal. The figure which shows the structural example of an output circuit. Explanatory drawing of a bypass control signal. The figure which shows an example of the change of a gradation voltage signal line typically. The timing diagram of the operation example of an output circuit. 1 is a block diagram of a configuration example of an electronic device according to an embodiment.

Explanation of symbols

10 liquid crystal display device, 20 LCD panel, 30 source driver,
32 gate drivers, 38 display controllers, 40 shift registers,
42 level shifter, 44 output buffer, 50 I / O buffer,
52 display memory, 54 line latch, 56 gradation voltage generation circuit,
57 resistor circuit, 58 DAC, 60 drive unit, 62 address control circuit,
64 row address decoder, 66 column address decoder,
68 line address decoder, 100 power supply circuit,
BPS _{1 to} BPS _n bypass circuit, BSW _{1 to} BSW 3 bypass switch,
D0 to D7 gradation data, DACcnt0 to DACcnt3 bypass control signal,
DEC _{1 to} DEC _N voltage selection circuit, GL _{1 to} GLM gate line,
GSW0 to GSW3 switch elements, GVL0 to GVL63 gradation voltage signal lines,
OUT _{1 to} OUT _N output circuit, SL _{1 to} SLN source lines,
V0 to V63 gradation voltage, VDDH high potential side power supply voltage,
VSEL-1 to VSEL-2 ^p first to second ^p gradation voltage switching circuits;
VSSH low potential side power supply voltage,
XDACON0 to XDACON3 Gradation voltage switching control signal

Claims (11)

(P + q) (p and q are natural numbers) A driving circuit for driving a source line of an electro-optical device based on gradation data of bits,
2 a reference voltage generation circuit for generating ^{(p + q)} types of reference voltages;
2 ^p gradation voltage signal lines to which any one of the 2 ^{(p + q)} types of reference voltages is supplied to each gradation voltage signal line;
The gradation voltage signal lines of the 2 ^p the gradation voltage signal line, and 2 ^p number of reference voltage switching circuit for outputting either a voltage of 2 ^q reference voltages of adjacent,
An impedance conversion circuit for driving the source line based on any reference voltage of the 2 ^p gradation voltage signal lines selected corresponding to the upper p-bit data of the gradation data;
A bypass circuit provided in parallel with the impedance conversion circuit, for bypassing an input and an output of the impedance conversion circuit;
The impedance conversion circuit drives the source line based on a reference voltage output by each reference voltage switching circuit when the lower q-bit data of the gradation data is a first value,
Thereafter, the output of the impedance conversion circuit is set to a high impedance state and the bypass circuit is set to a conductive state, and is selected by each reference voltage switching circuit corresponding to the lower q bits of the gradation data. A driving circuit which supplies a reference voltage to the source line. In claim 1,
A voltage selection circuit that selects any reference voltage of the 2 ^p grayscale voltage signal lines based on upper p-bit data of the grayscale data;
The impedance conversion circuit is
A drive circuit that drives the source line based on a voltage selected by the voltage selection circuit. In claim 1 or 2,
The bypass circuit is
Driving circuits each bypass switch, characterized in that it comprises a 2 ^q pieces of bypass switch arranged in parallel with the impedance conversion circuit. In claim 3,
Each bypass switch of the 2 ^q-number of the bypass switch,
A drive circuit characterized in that a conduction state or a non-conduction state is set using data of lower q bits of the gradation data during a period assigned to each bypass switch within a given drive period. In any one of Claims 1 thru | or 4,
The first value is
A driving circuit having a value when each bit data of lower q bits of the gradation data is 0. In any one of Claims 1 thru | or 5,
The impedance conversion circuit is
A drive circuit comprising an operational amplifier for class B push-pull operation. A plurality of scan lines;
Multiple source lines,
A plurality of pixels;
A scanning line driving circuit for scanning the plurality of scanning lines;
An electro-optical device comprising: the driving circuit according to claim 1 that drives the plurality of source lines.   An electronic apparatus comprising the electro-optical device according to claim 7. (P + q) (p and q are natural numbers) A driving method for driving a source line included in an electro-optical device based on gradation data of bits,
The gradation voltage signal lines 2 ^p the gradation voltage signal line, and outputs one of the voltages of 2 ^{(p + q)} Type 2 ^q kinds of adjoining reference voltage of the reference voltage,
Driving the source line by an impedance conversion circuit based on a reference voltage of any one of the 2 ^p gradation voltage signal lines selected corresponding to upper p-bit data of the gradation data;
A voltage corresponding to (p + q) -bit gradation data among the 2 ^q kinds of reference voltages is output to each gradation voltage signal line of the 2 ^p gradation voltage signal lines,
The output of the impedance conversion circuit is set to a high impedance state, and the reference voltage of any one of the 2 ^p gradation voltage signal lines selected corresponding to the upper p-bit data of the gradation data is set as the reference voltage. A driving method characterized by supplying to a source line. In claim 9,
The impedance conversion circuit is
A driving method, wherein a source line is driven based on a reference voltage corresponding to 0 in the lower q-bit data of gradation data among the 2 ^q kinds of reference voltages. In claim 9 or 10,
In each period of a given 2 ^q pieces of period assigned in the drive period, the driving method characterized by outputting a respective reference voltages of the 2 ^q reference voltages in each gray scale voltage signal line.

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