JP2008065301A - Drive circuit, electro-optical device, electronic apparatus, and driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit, an electro-optical device, an electronic apparatus, and a driving method, capable of reducing a lay-out area without lowering accuracy of gradation voltage and reducing the number of gradations. <P>SOLUTION: The drive circuit for driving source lines of the electro-optical device based on j-bits (j: an integer not less than 2) gradation data includes: a gradation voltage generating circuit for supplying 2<SP>k</SP>kinds of gradation voltages which are selected from among 2j kinds of gradation voltages and have continuity of gradation values to each of 2<SP>(j-k)</SP>(0<k<j, k: an integer) pieces of gradation signal lines during one selected period in a time-division manner; a voltage selecting circuit which selects one gradation signal line from among the gradation signal lines based on high order (j - k)-bits data of the gradation data; an output buffer for driving the source lines based on the gradation voltages of the gradation signal lines selected by the voltage selecting circuit; and a switch element for by-passing the input and output of the output buffer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a drive circuit, an electro-optical device, an electronic apparatus, and a drive method.

  Conventionally, as a liquid crystal panel (electro-optical device) used in an electronic device such as a mobile phone, an active matrix using a simple matrix type liquid crystal panel and a switching element such as a thin film transistor (hereinafter referred to as TFT). A liquid crystal panel of the type is known.

  The simple matrix method has an advantage that the power consumption can be easily reduced as compared with the active matrix method, but has a disadvantage that it is difficult to increase the number of colors and display a moving image. On the other hand, the active matrix method has an advantage that it is suitable for multi-color and moving image display, but has a disadvantage that it is difficult to reduce power consumption.

  In recent years, in portable electronic devices such as mobile phones, there has been a growing demand for multicolor and moving image display in order to provide high-quality images. For this reason, an active matrix type liquid crystal panel has been used instead of the simple matrix type liquid crystal panel used so far.

In general, a drive signal for performing image display is subjected to gamma correction according to the gradation characteristics of the display device. Taking a liquid crystal device as an example, a gradation voltage corrected so as to realize an optimum transmittance of a pixel is output based on gradation data for performing gradation display by gamma correction. Then, the source line is driven based on this gradation voltage.
JP-A-7-306660

  However, in recent years, there has been an increasing demand for higher image quality of display images, and there is an increasing demand for multi-gradation for a drive circuit that drives a source line of an electro-optical device. In this case, it is necessary to supply more types of gradation voltages to the output buffers that drive the source lines of the plurality of source lines of the electro-optical device.

Generally, when a driving circuit is integrated on a semiconductor substrate, a configuration in which a plurality of output buffers are arranged along the long side direction of the semiconductor substrate is employed. Therefore, the gradation signal line group to which the gradation voltage is supplied is also arranged so as to extend in the long side direction of the semiconductor substrate. Therefore, when the number of gradation signal lines is increased, the layout area in the short side direction of the semiconductor substrate intersecting the long side direction of the semiconductor substrate is increased. For example, if the number of bits of gradation data for each dot is 6, the number of gradation signal lines is 64 (= 2 ⁶ ), but if the number of bits of gradation data is 8, The number becomes 256 (= 2 ⁸ ), and the layout area of the gradation signal line group increases 4 (= 2 ^8-6 ) times.

  On the other hand, in Patent Document 1, in order to reduce the number of grayscale signal lines, a stepped voltage is generated, and a desired voltage is sampled from a plurality of voltages set in a stepped manner to perform pulse width modulation. A technique for generating a signal and expressing a halftone is disclosed. However, the gradation expression is limited to the pulse width modulation method, and there is a problem that it is difficult to improve the image quality when a larger number of gradations are required.

  In addition, it is difficult to set all the levels of a plurality of voltages set in a staircase shape with high accuracy, and even if the level can be set with high accuracy, the circuit scale becomes complicated. In particular, as the number of gradations increases and the voltage difference between the gradations decreases, it becomes more difficult to set the level of each voltage as disclosed in Patent Document 1 with high accuracy.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to drive a circuit that can reduce the layout area without reducing the number of gradations without reducing the accuracy of the gradation voltage. An electro-optical device, an electronic apparatus, and a driving method are provided.

In order to solve the above problems, the present invention
a driving circuit for driving a source line of an electro-optical device based on gradation data of j (j is an integer of 2 or more) bits;
2 ^(j−k) (0 <k <j, k is an integer) A pre-buffer voltage and gradation selected from at least 2 ^j kinds of gradation voltages for each gradation signal line of the gradation signal lines A gradation voltage generating circuit for supplying 2 ^k kinds of gradation voltages having continuous values in a time-division manner during one selection period;
A voltage selection circuit that selects one gradation signal line from the gradation signal lines based on upper (jk) bit data of the gradation data;
An output buffer for driving the source line based on the gradation voltage of the gradation signal line selected by the voltage selection circuit;
A switching element for bypassing an input and an output of the output buffer,
After the output buffer drives the source line based on the pre-buffer voltage in a buffer output period provided during one selection period,
In the gradation voltage output period after the buffer output period in the one selection period, a gradation voltage corresponding to lower k bits of the gradation data among the 2 ^k kinds of gradation voltages is supplied to the switch element. This relates to a drive circuit that supplies the source line via the.

In the driving circuit according to the present invention,
During the the one selection period, assigned the gray-scale voltage output period of the first to 2 ^k is provided in order after the buffer output period, the gradation voltage output period each gradation voltage of 2 ^k kinds of gradation voltages Period,
The gradation voltage of the gradation signal line selected by the voltage selection circuit is supplied to the source line via the switch element during the gradation voltage output period corresponding to the lower-order k-bit data of the gradation data. Can do.

In any of the above aspects, the gradation signal line, and supplies a time-division voltage pre-buffer, the 2 ^k kinds of gradation voltages gradation value are continuous in one selection period, the output buffer is pre After the source line is driven using the buffer voltage, the gradation voltage supplied to the gradation signal line is output to the source line as it is at a timing corresponding to the lower-order k-bit data of the gradation data. This eliminates the need to simply increase the number of gradation signal lines even when the number of bits of gradation data increases with the increase in gradation. In addition, since each source line is supplied with a gradation voltage that can be set with high accuracy as it is, it is possible to provide a drive circuit that can reduce the layout area without reducing the number of gradations without reducing the precision of the gradation voltage. .

In the driving circuit according to the present invention,
An output order designation register for designating which of the first to second ^k grayscale voltage output periods the grayscale voltage output period corresponding to the lower-order k-bit data of the grayscale data is allocated;
In the first to second ^k gradation voltage output periods, the gradation voltage output period corresponding to the set value of the output order specification register, and the lower k bits of the gradation data among the 2 ^k kinds of gradation voltages The gray scale voltage corresponding to the data can be supplied to the gray scale signal line.

  According to the present invention, it is possible to reliably prevent flicker and the like caused by the frequency of the image being lowered depending on the electro-optical device and the display image, and to prevent deterioration of the display image.

In the driving circuit according to the present invention,
Of the first to second ^k grayscale voltage output periods, in the grayscale voltage output period excluding the grayscale voltage output period corresponding to the lower-order k-bit data of the grayscale data, output to the source line is performed. High impedance state can be set.

  According to the present invention, it is possible to provide a drive circuit that avoids useless driving and achieves low power consumption.

In the driving circuit according to the present invention,
The output buffer is
A sample-and-hold circuit that samples the gradation voltage selected by the voltage selection circuit during a sampling period and outputs the gradation voltage as a hold voltage during the hold period;
The gradation voltage output period corresponding to the lower-order k-bit data of the gradation data is any one of the first to (2 ^k -1) gradation voltage output periods. The gradation voltage sampled during the gradation voltage output period corresponding to the lower-order k-bit data is used as the hold voltage, and the second ^k gradation voltage output period after the gradation voltage output period next to the gradation voltage output period Can be output to the source line over a period of time.

  According to the present invention, even when the leakage current of the source line or the like of the electro-optical device is large, it is not necessary to change the potential of the source line, so that a desired voltage can be written to the pixel.

In the driving circuit according to the present invention,
The output to the source line may be set to a high impedance state between the pth (1 ≦ p <k, p is an integer) grayscale voltage output period and the (p + 1) th grayscale voltage output period. it can.

  According to the present invention, in addition to the above effects, it is not necessary to influence the switching of the gradation voltage on the source line, so that it is possible to prevent image quality deterioration.

In the driving circuit according to the present invention,
The pre-buffer voltage is
One of the gradation voltages generated by the gradation voltage generation circuit may be used.

In the driving circuit according to the present invention,
The pre-buffer voltage is
It may be a voltage that is lower than the highest potential and higher than the lowest potential among the 2 ^k kinds of gradation voltages.

  According to any of the above inventions, since the amount of charge to be charged / discharged from the prebuffer voltage can be reduced in order to supply the gradation voltage to be output in the gradation voltage output period, a desired voltage is applied to the source line. The period for setting can be shortened.

The present invention also provides
a driving circuit for driving a source line of an electro-optical device based on gradation data of j (j is an integer of 2 or more) bits;
2 ^(j−k) (0 <k <j, k is an integer) Each gradation signal line of two gradation signal lines has a continuous gradation value selected from 2 ^j kinds of gradation voltages 2 a gradation voltage generating circuit for supplying ^k kinds of gradation voltages in a time-division manner during one selection period;
A voltage selection circuit that selects one gradation signal line from the gradation signal lines based on upper (jk) bit data of the gradation data;
An output buffer for driving the source line based on the gradation voltage of the gradation signal line selected by the voltage selection circuit;
A switching element for bypassing an input and an output of the output buffer,
The ^{q (1 ≦ q ≦ 2 k} , q is an integer) first to 2 ^k buffer output of the gradation voltage output period of the q after the buffer output period of the buffer output period and said q as a set A period and a first to second ^k gradation voltage output period are provided in one selection period,
The r corresponding to the data of the lower k bits of the gradation data among the first to buffer output period of the ^{2 k (1 ≦ r ≦ 2} k, r is an integer) to the buffer output period of the output buffer, after driving the source lines based on the grayscale voltage corresponding to the data of the lower k bits of the 2 ^k different gray-to gray-scale voltage output period of the r, the 2 ^k different gradation The present invention relates to a drive circuit that supplies a grayscale voltage corresponding to the lower k bits of the voltage to the source line via the switch element.

  According to the present invention, since the buffer output period is provided immediately before each gradation voltage output period, the drive capability is insufficient due to the source line being driven by the output buffer only during the buffer output period within one selection period. Thus, the source line voltage can reach the target voltage even with a short writing time.

In the driving circuit according to the present invention,
A gradation voltage supplied from the voltage selection circuit to the output buffer during the r-th buffer output period, and a gradation voltage supplied from the voltage selection circuit to the switch element during the r-th gradation voltage output period May be the same voltage.

  According to the present invention, the control of the drive circuit can be simplified.

In the driving circuit according to the present invention,
The buffer output period and the gradation voltage output period corresponding to the lower-order k-bit data of the gradation data are set to any of the first to second ^k buffer output periods and the first to second ^k buffer output periods. Contains an output order specification register that specifies whether to allocate,
Of the first to second ^k buffer output periods and the first to second ^k gradation voltage output periods, the buffer output period and the gradation voltage output period corresponding to the set value of the output order designation register, Of the 2 ^k kinds of gradation voltages, the gradation voltage corresponding to the lower k bits of the gradation data can be supplied to the gradation signal line.

  According to the present invention, it is possible to reliably prevent flicker and the like caused by the frequency of the image being lowered depending on the electro-optical device and the display image, and to prevent deterioration of the display image.

In the driving circuit according to the present invention,
Of the first to second ^k buffer output periods and the first to second ^k gradation voltage output periods, a buffer output period and a gradation voltage output period corresponding to lower k bits of the gradation data In the buffer output period and the gradation voltage output period excluding, the output to the source line can be set to a high impedance state.

  According to the present invention, it is possible to provide a drive circuit that avoids useless driving and achieves low power consumption.

In the driving circuit according to the present invention,
The output buffer is
A sample-and-hold circuit that samples the gradation voltage selected by the voltage selection circuit during a sampling period and outputs the gradation voltage as a hold voltage during the hold period;
The buffer output period and the gradation voltage output period corresponding to the lower-order k-bit data of the gradation data are the first to (2 ^k −1) buffer output periods and the first to (2 ^k −1). The grayscale voltage sampled during the grayscale voltage output period corresponding to the lower-order k-bit data of the grayscale data is temporarily sourced after the grayscale voltage output period. The output to the line can be set to a high impedance state and output as the hold voltage over a period up to the second ^k gradation voltage output period.

  According to the present invention, even when the leakage current of the source line or the like of the electro-optical device is large, it is not necessary to change the potential of the source line, so that a desired voltage can be written to the pixel.

In the driving circuit according to the present invention,
The output to the source line can be set in a high impedance state between the pth (1 ≦ p <k, p is an integer) grayscale voltage output period and the (p + 1) th buffer output period.

  According to the present invention, in addition to the above effects, it is not necessary to influence the switching of the gradation voltage on the source line, so that it is possible to prevent image quality deterioration.

The present invention also provides
Multiple source lines,
Multiple gate lines,
A plurality of pixels connected to the plurality of source lines and the plurality of gate lines;
A gate driver that scans the plurality of gate lines;
The present invention relates to an electro-optical device including any one of the drive circuits described above that drives the plurality of source lines.

  According to the present invention, a high-quality and low-cost electro-optical device can be provided.

The present invention also provides
The present invention relates to an electronic device including any one of the drive circuits described above.

  ADVANTAGE OF THE INVENTION According to this invention, it can contribute to provision of the electronic device which can obtain high image quality by the drive based on a low-cost and highly accurate gradation voltage.

The present invention also provides
The present invention relates to an electronic apparatus including the electro-optical device described above.

  According to the present invention, it is possible to contribute to provision of an electronic apparatus including an electro-optical device with high image quality and low cost.

The present invention also provides
A driving method for driving a source line of an electro-optical device based on gradation data of j (j is an integer of 2 or more) bits,
2 ^(j−k) (0 <k <j, k is an integer) A pre-buffer voltage and gradation selected from at least 2 ^j kinds of gradation voltages for each gradation signal line of the gradation signal lines ^2k kinds of gradation voltages with continuous values are supplied in a time-division manner during one selection period,
One gradation signal line is selected from the gradation signal lines based on upper (jk) bit data of the gradation data;
After the output buffer drives the source line based on the prebuffer voltage during a buffer output period provided during one selection period,
In the gradation voltage output period after the buffer output period in the one selection period, 2 ^k kinds of gradations of the gradation signal line selected based on the upper (jk) bit data of the gradation data The present invention relates to a driving method in which a gradation voltage corresponding to lower k-bit data of the gradation data among the voltages is supplied to the source line by bypassing the input and output of the output buffer.

In the driving method according to the present invention,
During the the one selection period, assigned the gray-scale voltage output period of the first to 2 ^k is provided in order after the buffer output period, the gradation voltage output period each gradation voltage of 2 ^k kinds of gradation voltages Period,
During the gradation voltage output period corresponding to the lower-order k-bit data of the gradation data, the gradation voltage corresponding to the lower-order k-bit data is bypassed between the input and output of the output buffer to the source line. Can be supplied.

In the driving method according to the present invention,
Of the first to second ^k gradation voltage output periods, the gradation voltage output period corresponding to the lower k bits of the gradation data is defined as any of the first to second ^k gradation voltage output periods. In the gradation voltage output period corresponding to the setting value of the output order specification register that specifies whether to assign to the gradation voltage, the gradation voltage corresponding to the lower k bits of the gradation data among the 2 ^k kinds of gradation voltages It can be supplied to the gradation signal line.

In the driving method according to the present invention,
Of the first to second ^k grayscale voltage output periods, in the grayscale voltage output period excluding the grayscale voltage output period corresponding to the lower-order k-bit data of the grayscale data, output to the source line is performed. High impedance state can be set.

In the driving method according to the present invention,
The output buffer is
A sample-and-hold circuit that samples the gradation voltage selected by the voltage selection circuit during a sampling period and outputs the gradation voltage as a hold voltage during the hold period;
The gradation voltage output period corresponding to the lower-order k-bit data of the gradation data is any one of the first to (2 ^k -1) gradation voltage output periods. The gradation voltage sampled during the gradation voltage output period corresponding to the lower-order k-bit data is used as the hold voltage, and the second ^k gradation voltage output period after the gradation voltage output period next to the gradation voltage output period Can be output to the source line over a period of time.

In the driving method according to the present invention,
The output to the source line may be set to a high impedance state between the pth (1 ≦ p <k, p is an integer) grayscale voltage output period and the (p + 1) th grayscale voltage output period. it can.

The present invention also provides
A driving method for driving a source line of an electro-optical device based on gradation data of j (j is an integer of 2 or more) bits,
2 ^(j−k) (0 <k <j, k is an integer) Each gradation signal line of two gradation signal lines has a continuous gradation value selected from 2 ^j kinds of gradation voltages 2 ^k types of gradation voltages are supplied in a time-division manner during one selection period,
One gradation signal line is selected from the gradation signal lines based on upper (jk) bit data of the gradation data;
The ^{q (1 ≦ q ≦ 2 k} , q is an integer) first to 2 ^k buffer output of the gradation voltage output period of the q after the buffer output period of the buffer output period and said q as a set A period and a first to second ^k gradation voltage output period are provided in one selection period,
The r corresponding to the data of the lower k bits of the gradation data among the first to buffer output period of the ^{2 k (1 ≦ r ≦ 2} k, r is an integer) to the buffer output period, the output buffer, wherein the source based on the grayscale voltage corresponding to the data of the lower k bits of the 2 ^k kinds of gradation voltages of the gradation signal lines selected based on the upper (j-k) of bit data of the grayscale data After driving the line, during the r-th gradation voltage output period, one of the 2 ^k kinds of gradation voltages is supplied to the source line by bypassing the input and output of the output buffer Related to the driving method.

In the driving method according to the present invention,
The gradation voltage supplied to the output buffer during the r-th buffer output period and the gradation voltage supplied to the switch element during the r-th gradation voltage output period may be the same voltage. .

In the driving method according to the present invention,
The buffer output period and the gradation voltage output period corresponding to the lower-order k-bit data of the gradation data are set to any of the first to second ^k buffer output periods and the first to second ^k buffer output periods. In the buffer output period and the gradation voltage output period corresponding to the setting value of the output order designation register for designating whether to allocate, the floor corresponding to the lower k bits of the gradation data among the 2 ^k kinds of gradation voltages A regulated voltage can be supplied to the gradation signal line.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Liquid Crystal Device FIG. 1 shows an outline of the configuration of an active matrix liquid crystal device according to this embodiment. Here, an active matrix type liquid crystal device will be described, but the drive circuit as a source driver in this embodiment can be applied to other liquid crystal devices.

  The liquid crystal device 10 includes a liquid crystal display (LCD) panel (display panel in a broad sense, electro-optical device in a broader sense) 20. The LCD panel 20 is formed on a glass substrate, for example. On this glass substrate, a plurality of gate lines (scanning lines) GL1 to GLM (M is an integer of 2 or more) arranged in the Y direction and extending in the X direction, and a source line arranged in the X direction and extending in the Y direction, respectively. (Data lines) SL1 to SLN (N is an integer of 2 or more) are arranged. The pixel region corresponds to the intersection position of the gate line GLm (1 ≦ m ≦ M, m is an integer, the same applies hereinafter) and the source line SLn (1 ≦ n ≦ N, n is an integer, the same applies hereinafter). (Pixel) is provided, and a thin film transistor (hereinafter abbreviated as TFT) 22 mn is disposed in the pixel region.

  The gate of the TFT 22mn is connected to the gate line GLn. The source of the TFT 22mn is connected to the source line SLn. The drain of the TFT 22mn is connected to the pixel electrode 26mn. Liquid crystal is sealed between the pixel electrode 26mn and the counter electrode 28mn facing the pixel electrode 26mn, thereby forming a liquid crystal capacitor (liquid crystal element in a broad sense) 24mn. The transmittance of the pixel changes according to the applied voltage between the pixel electrode 26mn and the counter electrode 28mn. The counter electrode voltage Vcom is supplied to the counter electrode 28mn.

  Such an LCD panel 20 includes, for example, a first substrate on which pixel electrodes and TFTs are formed and a second substrate on which counter electrodes are formed, and a liquid crystal as an electro-optical material is interposed between the two substrates. It is formed by enclosing.

  The liquid crystal device 10 includes a source driver (display driver in a broad sense, drive circuit in a broader sense) 30. The source driver 30 drives each source line of the source lines SL1 to SLN of the LCD panel 20 based on gradation data of j (j is an integer of 2 or more) bits corresponding to each source line.

  The liquid crystal device 10 can include a gate driver (scan driver in a broad sense) 32. The gate driver 32 scans the gate lines GL1 to GLM of the LCD panel 20 within one vertical scanning period.

  The liquid crystal device 10 can include a power supply circuit 100. The power supply circuit 100 generates voltages necessary for driving the source lines and supplies them to the source driver 30. The power supply circuit 100 generates, for example, power supply voltages VDDH and VSSH necessary for driving a source line of the source driver 30 and a voltage of a logic unit of the source driver 30.

  The power supply circuit 100 generates a voltage necessary for scanning the gate line and supplies it to the gate driver 32.

  Further, the power supply circuit 100 generates a counter electrode voltage Vcom. In accordance with the timing of the polarity inversion signal POL generated by the source driver 30, the power supply circuit 100 generates a common electrode voltage Vcom that periodically repeats the high potential side voltage VCOMH and the low potential side voltage VCOML on the LCD panel 20. Output to electrode.

  The liquid crystal device 10 can include a display controller 38. The display controller 38 controls the source driver 30, the gate driver 32, and the power supply circuit 100 according to contents set by a host such as a central processing unit (hereinafter abbreviated as CPU) (not shown). For example, the display controller 38 sets an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the source driver 30 and the gate driver 32.

  In FIG. 1, the liquid crystal device 10 includes the power supply circuit 100 or the display controller 38, but at least one of these may be provided outside the liquid crystal device 10. Alternatively, the liquid crystal device 10 may be configured to include a host.

  The source driver 30 may incorporate at least one of the gate driver 32 and the power supply circuit 100.

  Furthermore, some or all of the source driver 30, the gate driver 32, the display controller 38, and the power supply circuit 100 may be formed on the LCD panel 20. For example, in FIG. 2, a source driver 30 and a gate driver 32 are formed on the LCD panel 20. As described above, the LCD panel 20 includes a plurality of source lines, a plurality of gate lines, and a plurality of switch elements in which each switch element is connected to each gate line of the plurality of gate lines and each source line of the plurality of source lines. And a source driver for driving a plurality of source lines. A plurality of pixels are formed in the pixel formation region 80 of the LCD panel 20.

2. Gate Driver FIG. 3 shows a configuration example of the gate driver 32 of FIG.

  The gate driver 32 includes a shift register 40, a level shifter 42, and an output buffer 44.

  The shift register 40 includes a plurality of flip-flops in which each flip-flop is provided corresponding to each gate line and sequentially connected. When the shift register 40 holds the start pulse signal STV in the flip-flop in synchronization with the clock signal CPV, the shift register 40 sequentially shifts the start pulse signal STV to the adjacent flip-flop in synchronization with the clock signal CPV. The clock signal CPV input here is a horizontal synchronizing signal, and the start pulse signal STV is a vertical synchronizing signal.

  The level shifter 42 shifts the voltage level from the shift register 40 to a voltage level corresponding to the liquid crystal element of the LCD panel 20 and the transistor capability of the TFT. As this voltage level, for example, a high voltage level of 20 V to 50 V is required.

  The output buffer 44 buffers the scanning voltage shifted by the level shifter 42 and outputs it to the gate line to drive the gate line.

  Note that the gate driver 32 scans a plurality of gate lines by selecting a gate line corresponding to the decoding result by the address decoder without scanning the gate line using a shift register as shown in FIG. Also good.

3. Source driver (drive circuit)
FIG. 4 shows a block diagram of a configuration example of the source driver 30 of FIG. 1 or FIG.

  The source driver 30 includes an I / O buffer 50, a display memory 52, a line latch (gradation data latch in a broad sense) 54, a gradation voltage generation circuit 56, and a DAC (Digital / Analog Converter) (a voltage selection circuit in a broad sense). 58, including the drive unit 60.

  For example, the gradation data D is input to the source driver 30 from the display controller 38. The gradation data D is input in synchronization with the dot clock signal DCLK and buffered in the I / O buffer 50. The dot clock signal DCLK is supplied from the display controller 38.

  The I / O buffer 50 is accessed by the display controller 38 or a host (not shown). The gradation data buffered in the I / O buffer 50 is written in the display memory 52. The gradation data read from the display memory 52 is output to the display controller 38 and the like after being buffered by the I / O buffer 50.

  The display memory (gradation data memory) 52 includes a plurality of memory cells provided corresponding to the output lines in which the memory cells are connected to the source lines. Each memory cell is specified by a row address and a column address. Each memory cell for one scan line is specified by a line address.

  The address control circuit 62 generates a row address, a column address, and a line address for specifying a memory cell in the display memory 52. The address control circuit 62 generates a row address and a column address when writing gradation data into the display memory 52. That is, the gradation data buffered in the I / O buffer 50 is written into the memory cell of the display memory 52 specified by the row address and the column address.

  The row address decoder 64 decodes the row address and selects a memory cell of the display memory 52 corresponding to the row address. The column address decoder 66 decodes the column address and selects a memory cell of the display memory 52 corresponding to the column address.

  When the gradation data is read from the display memory 52 and output to the line latch 54, the address control circuit 62 generates a line address. That is, the line address decoder 68 decodes the line address and selects a memory cell of the display memory 52 corresponding to the line address. Then, gradation data for one horizontal scan read from the memory cell specified by the line address is output to the line latch 54.

  The address control circuit 62 generates a row address and a column address when reading the gradation data from the display memory 52 and outputting it to the I / O buffer 50. That is, the gradation data held in the memory cell of the display memory 52 specified by the row address and the column address is read to the I / O buffer 50. The gradation data read to the I / O buffer 50 is extracted by the display controller 38 or a host (not shown).

  Therefore, in FIG. 4, the row address decoder 64, the column address decoder 66, and the address control circuit 62 function as a write control circuit that performs writing control of gradation data to the display memory 52. On the other hand, in FIG. 4, the line address decoder 68, the column address decoder 66, and the address control circuit 62 function as a readout control circuit that performs readout control of gradation data from the display memory 52.

  The line latch (gradation data latch) 54 latches the gradation data for one horizontal scan read from the display memory 52 at the change timing of the readout clock RCLK. The line latch 54 includes a plurality of registers in which each register holds gradation data for one dot. The gradation data for one dot read from the display memory 52 is taken into each of the plurality of registers of the line latch 54. The readout clock RCLK is generated in synchronization with a horizontal synchronization signal that defines one horizontal scanning period, and has a pulse at, for example, the start timing of one horizontal scanning period or a timing after a given period from the start timing.

A gradation voltage generation circuit (reference voltage generation circuit in a broad sense) 56 generates a plurality of gradation voltages in which each gradation voltage (reference voltage) corresponds to each gradation data. More specifically, the gradation voltage generation circuit 56 generates a plurality of gradation voltages corresponding to each gradation data, based on the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH. . Such a gradation voltage generation circuit 56 generates at least 2 ^j kinds of gradation voltages. The gradation voltage generation circuit 56 has voltages of at least 2 ^j divided nodes of a resistance circuit to which a high potential side power supply voltage VDDH and a low potential side power supply voltage VSSH are supplied at both ends. By outputting as a regulated voltage, it can be output as at least 2 ^j types of gradation voltages. The source driver 30 has 2 ^(j−k) (0 <k <j, k is an integer) gradation signal lines, and each gradation signal line includes at least 2 ^j kinds of gradation voltages. ^2k kinds of gradation voltages selected from the above are supplied in a time division manner during one selection period.

  The DAC 58 generates a gradation voltage corresponding to the gradation data output from the line latch 54 for each output line that is an output of the driving unit 60. More specifically, the DAC 58 corresponds to the gradation data for one output line of the drive unit 60 output from the line latch 54 among the plurality of gradation voltages generated by the gradation voltage generation circuit 56. A gradation voltage is selected, and the selected gradation voltage is output.

The DAC 58 includes voltage selection circuits DEC _{1 to} DEC _N provided for each output line. Each voltage selection circuit outputs one gradation voltage corresponding to the gradation data from among the plurality of gradation voltages from the gradation voltage generation circuit 56.

The driving unit 60 drives a plurality of output lines whose output lines are connected to the source lines of the LCD panel 20. More specifically, the drive unit 60 drives each output line based on the gradation voltage output for each output line by the voltage selection circuit of the DAC 58. The drive unit 60 includes output circuits OUT _{1 to} OUT _N provided for each output line. Each output circuit drives the source line based on the gradation voltage from each voltage selection circuit. Each output circuit can be configured by an operational amplifier (output buffer in a broad sense) connected in a voltage follower.

  FIG. 5 shows an example of a layout image when the source driver is integrated on the semiconductor substrate. The X direction and Y direction in FIG. 5 are the same as those in FIG.

  The X direction, which is the arrangement direction of the source lines SL1 to SLN extending in the Y direction, is mounted on the LCD panel 20 so that each part of the source driver 30 is the long side direction of the chip 90 integrated on the semiconductor substrate. . Therefore, the Y direction becomes the short side direction of the chip 90.

In such a chip 90, each of the output circuits OUT _{1 to} OUT _N of the drive unit 60 of FIG. 4 is placed in a region near the end of the chip 90 where the chip 90 is connected to the source lines SL1 to SLN. It will be arranged along the direction. Then, in order to supply the gradation voltages corresponding to the gradation data to each of the output circuits OUT _{1 to} OUT _N , the gradation signal line group 92 for transmitting the gradation voltages extends in the long side direction of the chip 90. Are arranged as follows.

At this time, in order to increase the length of the grayscale signal line group and disperse the load capacitance, the grayscale voltage generation circuit 56 is provided in the central portion of the chip 90, and the long side of the chip 90 extends from the central portion of the chip 90. The grayscale signal line groups 92 ₁ and 92 ₂ are arranged so as to extend in opposite directions along the direction. The gradation signal line groups 92 ₁ and 92 ₂ each have 2 ^(j−k) gradation signal lines. Then, in order to shorten the length of the word line (bit line) of the display memory 52 extending in the long side direction of the chip 90, the display memory 52 is divided into _two display memories (blocks) 52 ₁ and 52 _2. A logic unit 94 is provided at the center of the chip 90. The logic unit 94 includes at least one of the address control circuit 62, the column address decoder 66, the row address decoder 64, and the line address decoder 68 of FIG.

Thus, considering that the number of bits of grayscale data with the multi-gradation is almost twice the layout area of the gray scale signal line group 92 _1, 92 ₂ in the case of increased 1 bit, gray-scale data Even when the number of bits increases, the increase in the area of the chip 90 can be reliably suppressed by suppressing the increase in the number of gradation signal line groups.

Therefore, in this embodiment, the grayscale voltage generating circuit 56, a grayscale signal line group 92 ₁ to 92 ₂ of the gradation signal lines as described above, so as to supply a time division multiple types of gradation voltages ing. More specifically, the gradation voltage generation circuit 56 applies 2 ^k kinds of gradation voltages corresponding to lower-order k-bit data of gradation data to each gradation signal of 2 ^(j−k) gradation signal lines. Supply the lines in a time-sharing manner. The DAC 58 (voltage selection circuits DEC _{1 to} DEC _N ) selects a gradation signal line corresponding to upper (jk) bit data of gradation data. Then, each output circuit of the output circuits OUT _{1 to} OUT _N drives the source line using the gradation voltage of the gradation signal line selected by the DAC 58 at a timing corresponding to the lower-order k-bit data of the gradation data. To do. Each output circuit includes an operational amplifier connected as a voltage follower as an output buffer, and a bypass switch circuit that bypasses the input and output of the operational amplifier. The source driver charges and discharges the source line with the operational amplifier only once in one horizontal scanning period (one selection period) in accordance with the changeable driving mode, and then the gradation from the DAC 58 via the bypass switch circuit. Supplying the grayscale voltage from the DAC 58 to the source line through the bypass switch circuit after supplying the voltage to the source line or charging / discharging the source line with the operational amplifier within the one horizontal scanning period. Repeat.

3.1 First Drive Mode In the first drive mode, the source driver 30 drives each source line based on j-bit gradation data. At this time, the gradation voltage generating circuit 56 uses a pre-buffer selected from at least 2 ^(jk) kinds of gradation voltages for each gradation signal line of 2 ^(jk) gradation signal lines. supplied in a time division manner 2 ^k kinds of gradation voltages voltages and gradation values are continuous in one selection period. The DAC 58 (each DEC) selects one gradation signal line from 2 ^(j−k) gradation signal lines based on the upper (j−k) bit data of the gradation data. In one selection period, a pre-buffer period (buffer output period) and a DAC period (grayscale voltage output period) after the pre-buffer period are provided. In the prebuffer period, each output circuit drives the source line based on the prebuffer voltage. After that, during the DAC period, the gradation voltage corresponding to the lower k bits of the gradation data among the 2 ^(j−k) kinds of gradation voltages is bypassed between the input and output of the output circuit to the source line. Supply. More specifically, 1 during the selection period, DAC1 period ～DAC2 ^k period after the pre-buffering period (gray-scale voltage output period of the first to ^{2 k)} is provided in order, each DAC period ^{2 k} kinds of This is a period assigned to each gradation voltage of the gradation voltage. Then, during the DAC period corresponding to the lower-order k-bit data of the gradation data, the gradation voltage of the gradation signal line selected by the DAC 58 (each DEC) is supplied to the source line via the bypass switch circuit.

  FIG. 6 shows an example of the timing of the first drive mode of the source driver in this embodiment. In FIG. 6, it is assumed that j is 6 and k is 1.

  When the lower 1 (= k) bit data of the gradation data is “0”, it is a so-called even gradation. When the lower 1 bit data of the gradation data is “1”, it is a so-called odd gradation. In this case, a pre-buffer voltage, a gradation voltage corresponding to an odd gradation, and a gradation voltage corresponding to an even gradation are supplied to each gradation signal line of the gradation signal line group in a time division manner. The odd gradation and the even gradation have continuous gradation values when the gradation value is expressed by 5 (= j−k) bits. Further, it can be said that the odd gradation and the even gradation are adjacent gradations.

  In the first drive mode, when one horizontal scanning period (one selection period, 1H) is started, the pre-buffer period BT is started. In the pre-buffer period BT, the operational amplifier of each output circuit performs impedance conversion based on the pre-buffer voltage to drive the source line. After the pre-buffer period BT, a DAC1 period DT1 and a DAC2 period DT2 are provided. The pre-buffer period BT, the DAC1 period DT1, and the DAC2 period DT2 are time divisions of the pre-buffer voltage supplied to each gradation signal line, the gradation voltage corresponding to the odd gradation, and the gradation voltage corresponding to the even gradation, respectively. Synchronized with timing.

  Further, the output to the source line may be set to a high impedance state between the pth (1 ≦ p <k, p is an integer) grayscale voltage output period and the (p + 1) th grayscale voltage output period. desirable. In FIG. 6, a high impedance period HZT in which the output to the source line is set to a high impedance state is provided between the pre-buffer period BT and the DAC1 period DT1, and between the DAC1 period DT1 and the DAC2 period DT2. By providing the high impedance period HZT, the influence of switching between the gradation voltage of the pre-buffer period BT and the gradation voltage of the DAC1 period DT1, and the influence of switching of the gradation voltage of the DAC1 period DT1 and the gradation voltage of the DAC2 period DT2. It is not necessary to give to the source line, and the deterioration of the image quality can be prevented.

Of the DAC1 period DT1 and DAC2 period DT2 (first to second ^k gradation voltage output periods), in the DAC period excluding the DAC period corresponding to the lower 1 (= k) bit data of the gradation data, It is desirable to set the output to the source line to a high impedance state. By doing so, the driving period of the source line can be minimized, unnecessary driving can be omitted, and power consumption can be reduced.

  When the lower 1-bit data is “0”, for example, a gradation voltage corresponding to an odd gradation (or even gradation) is supplied to the source line in the DAC1 period DT1 by bypassing the operational amplifier. In the DAC2 period DT2, the output to the source line is set to a high impedance state.

  When the lower 1 bit data is “1”, the output to the source line is set to the high impedance state in the DAC1 period DT1. In the DAC2 period DT2, for example, a gradation voltage corresponding to an even gradation (or an odd gradation) is supplied to the source line by bypassing the operational amplifier.

Selection voltage of the gate line rises at a pre-buffering period BT, (in a broad sense gradation voltage output period of the 2 ^k) DAC2 period DT2 falls within. The voltage of the source line when the selection voltage of the gate line falls is written to the pixel electrode. When the lower 1 bit data is “0”, the output to the source line is set to the high impedance state when the selection voltage of the gate line falls, but the electric potential accumulated by the charge accumulated by the parasitic capacitance of the source line Therefore, a desired voltage can be written to the pixel electrode.

  In FIG. 6, the high impedance period HZT is shown as one clock, but the high impedance period HZT is a period of two clocks or more, or a period of several tens of nanoseconds that can be arbitrarily set by the delay element. There may be.

  FIG. 7 shows another example of the timing of the first drive mode of the source driver in this embodiment. In FIG. 7, it is assumed that j is 6 and k is 2.

  In the case of FIG. 7, after the pre-buffer period BT, the DAC1 period DT1 (first gradation voltage output period), the DAC2 period DT2 (second gradation voltage output period), and the DAC3 period DT3 (third gradation voltage output) Period), a DAC4 period DT4 (fourth gradation voltage output period) is provided. Between the pre-buffer period BT and the DAC1 period DT1, between the DAC1 period DT1 and the DAC2 period DT2, between the DAC2 period DT2 and the DAC3 period DT3, and between the DAC3 period DT3 and the DAC4 period DT4, respectively, A high impedance period HZT in which the output to is set to a high impedance state is provided.

When the lower 2 bits of data are “00”, the operational amplifier of each output circuit performs impedance conversion based on the prebuffer voltage and drives the source line during the prebuffer period BT. In subsequent DAC1 period DT1, and a gradation voltage corresponding to the lower 2-bit data "00" of the two ^two gray scale voltages supplied in time division gray scale signal line, to bypass the operational amplifier source Supply to the wire. Thereafter, the output to the source line is set to the high impedance state until the next selection period is started.

When the lower 2 bits of data are “01”, the operational amplifier of each output circuit performs impedance conversion based on the prebuffer voltage during the prebuffer period BT to drive the source line. In the subsequent DAC1 period DT1, the output to the source line is set to a high impedance state. Then, the DAC2 period DT2, and a gradation voltage corresponding to the lower 2-bit data "01" of the two ^two gray scale voltages supplied in time division gray scale signal line, to bypass the operational amplifier source Supply to the wire. Thereafter, the output to the source line is set to the high impedance state until the next selection period is started.

When the lower 2 bits of data are “10”, the operational amplifier of each output circuit performs impedance conversion based on the pre-buffer voltage and drives the source line during the pre-buffer period BT. During the subsequent DAC1 period DT1 to the start of the DAC3 period DT3, the output to the source line is set to a high impedance state. Then, the DAC3 period DT3, and a gradation voltage corresponding to the lower 2-bit data "10" of the two ^two gray scale voltages supplied in time division gray scale signal line, to bypass the operational amplifier source Supply to the wire. Thereafter, the output to the source line is set to the high impedance state until the next selection period is started.

When the lower 2 bits of data are “11”, the operational amplifier of each output circuit performs impedance conversion based on the pre-buffer voltage and drives the source line during the pre-buffer period BT. During the subsequent DAC1 period DT1 to the start of the DAC4 period DT4, the output to the source line is set to the high impedance state. Then, in DAC4 period DT4, and a gradation voltage corresponding to the lower 2-bit data "11" of the two ^two gray scale voltages supplied in time division gray scale signal line, to bypass the operational amplifier source Supply to the wire. Thereafter, the output to the source line is set to the high impedance state until the next selection period is started.

  In the case of FIG. 7, the selection voltage of the gate line rises in the prebuffer period BT and falls in the DAC4 period DT4. When the lower 2 bits of data are “00”, “01”, “10”, the output to the source line is set to the high impedance state when the selection voltage of the gate line falls, but the source line parasitic Since the potential is held by the charge accumulated by the capacitor, a desired voltage can be written to the pixel electrode.

  By adopting such a driving method in the first driving mode, the number of gradation signal lines can be greatly reduced without reducing the number of gradations, and the layout area of the source driver can be reduced without degrading the image quality. Cost reduction can be achieved.

3.1.1 Detailed Configuration Example Next, a hardware configuration example for realizing the first drive mode will be described.

  FIG. 8 shows a main part of a configuration example per output of the source driver 30 of FIG.

  FIG. 8 shows a configuration example of a portion for driving the source line SL1 of the source driver 30 where j, which is the number of bits of gradation data, is 6, k is 1, which is the number of lower bits. In FIG. 8, the same parts as those in FIG. 4 are shown by adding the source line number “1” to the reference numerals in FIG. 4. FIG. 8 shows only a configuration example of a portion for driving the source line SL1, but a portion for driving each source line of the source lines SL2 to SLN has a similar configuration. In FIG. 8, the control signals KK1 and KK2 are prohibited from being simultaneously at the H level.

The display memory 52 _1, grayscale data D of 6 bits for driving the source line SL1 [5: 0] is stored. Gradation data read from the display memory 52 ₁ is taken into the line latch 54 ₁ at the change timing of the read clock RCLK. The gradation data fetched by the line latch 54 ₁ is supplied to the control logic unit 110 ₁ . The control logic unit 110 _1, the polarity inversion signal POL from the display controller 38, control signals KK_MODE from the logic unit 94, KK1, KK2 is input. Control logic unit 110 ₁ from these input signals, the control signal DACEN, PSI, higher gradation data 5 bit data DOUT: outputting the 5 1].

The level shifter 112 _1, the control signal DACEN, PSI, the upper 5-bit data DOUT of the gradation data [5: 1] performs level shifting the amplitude voltage is increased for each bit of the signal, and outputs the signal after level shift. Control signal DACEN which is level-shifted by the level shifter 112 ₁ is input to the bypass switching circuit 114 _1. The control signal PSI level-shifted by the level shifter 112 ₁ is input to the PS logic unit 116 ₁ . Top grayscale data level-shifted by the level shifter 112 ₁ 5-bit data DOUT [5: 1] is inputted to the voltage selection circuit DEC _1.

The voltage selection circuit DEC ₁ is connected with 32 gradation signal lines to which the gradation voltage from the gradation voltage generation circuit 56 is supplied. The voltage selection circuit DEC ₁ selects a gradation signal line corresponding to the upper 5-bit data DOUT [5: 1] of gradation data from among the 32 gradation signal lines, and the gradation voltage of the gradation signal line is selected. the output to the operational amplifier OP _1.

The bypass switch circuit 114 _1, the control signal DACON from the logic unit 94 is input. The bypass switch circuit 114 ₁ performs control to bypass the input and output of the operational amplifier OP ₁ based on the control signals DACON and DACEN. The PS logic unit 116 _1, the control signal PS from the logic unit 94 is input. PS logic unit 116 _1, the control signal PS, based on the PSI, stop or limit the operating current of the operational amplifier OP _1, performs control of setting an output of the operational amplifier OP ₁ to the high-impedance state. In FIG. 8, the output circuit OUT ₁ includes an operational amplifier OP ₁ , a bypass switch circuit 114 ₁ , and a PS logic unit 116 ₁ .

  FIG. 9 shows an example of operation timing of the read clock RCLK, the control signals PS, DACON, KK1, and KK2 of FIG. 8 in the first drive mode.

  In the present embodiment, for example, the logic unit 94 includes a control register unit (not shown). The control register unit has a drive mode setting register. The source driver 30 operates in the first drive mode or the second drive mode according to the set value of the drive mode setting register set by the display controller 38 or the like. For this reason, the logic unit 94 generates the read clock RCLK, the control signals PS, DACON, KK1, and KK2 having the change timing corresponding to the set value of the drive mode setting register.

When one horizontal scanning period (one selection period) is started, the logic unit 94 generates a pulse of the read clock RCLK. For example the falling of the read clock RCLK, grayscale data D to the line latch 54 ₁ [5: 0] is captured.

Then, the logic unit 94 outputs a control signal PS that changes from the H level to the L level after a given period from the falling edge of the read clock RCLK. Control signal PS is a signal defining the variation timing of the control signal PSOUT as power saving signal of the operational amplifier OP _1. The control signal PS becomes L level only during the period corresponding to the pre-buffer period BT, and then changes to H level.

The control signal DACON changes from the L level to the H level after a given period from the timing when the control signal PS changes to the H level. Control signal DACON is a signal for defining a timing of bypassing the input and the output of the operational amplifier OP _1. The control signal DACON becomes H level only during a period corresponding to the DAC1 period DT1 and the DAC2 period DT2. The control signal DACON changes to the L level for a given period between the DAC1 period DT1 and the DAC2 period DT2, so that the high impedance period HZT can be provided.

  The control signal KK1 is a signal indicating, for example, an odd gradation (even gradation), and is a signal that is at an H level only during the DAC1 period DT1, for example. On the other hand, the control signal KK2 is a signal indicating, for example, an even gradation (odd gradation), and is, for example, a signal that becomes H level only during the DAC2 period DT2.

10 and 11 is a circuit diagram showing a configuration example of a control logic unit 110 ₁ of FIG.

Figure 10 is based in order to carry out polarity inversion driving of the counter electrode in the polarity inversion signal POL, the line latch 54 grayscale data D read out from the ₁ [5: 0] indicating the circuit which performs the inversion control. When the polarity inversion signal POL is at the H level, this circuit outputs DOUT [5: 1] in which each bit of the gradation data D [5: 1] is output as it is, and when the polarity inversion signal POL is at the L level. DOUT [5: 1] output by inverting each bit of the gradation data D [5: 1] is output. Further, when the polarity inversion signal POL is at H level, the gradation data D [0] is output as D0OUT as it is, and when the polarity inversion signal POL is at L level, the gradation data D [0] is inverted and output as D0OUT. Is done.

  FIG. 11 shows a circuit for generating control signals DACEN and PSI based on D0OUT and control signals KK_MODE, KK1 and KK2. In the first drive mode, the control signal KK_MODE is set to the L level. Therefore, in the first drive mode, the control signal PSI is fixed at the L level.

  When the lower 1 bit (least significant bit) of the gradation data is “0”, when the control signal KK1 is H level and the control signal KK2 is L level, the control signal DACEN is H level, the control signal KK1 is L level, and the control signal KK1 is L level. When signal KK2 is at H level, control signal DACEN is at L level.

  When the lower 1 bit (least significant bit) of the gradation data is “1”, when the control signal KK1 is H level and the control signal KK2 is L level, the control signal DACEN is L level, the control signal KK1 is L level, and the control signal KK1 is L level. When the signal KK2 is at H level, the control signal DACEN is at H level.

Such gray-scale data DOUT [5: 1], the control signal DACEN, PSI is level-shifted by the level shifter 112 _1. The gradation data DOUT [5: 1] after the level shift is input to the voltage selection circuit DEC ₁ of the DAC 58. The voltage selection circuit DEC ₁ is connected to the gradation signal lines V 0 L to V 31 L from the gradation voltage generation circuit 56.

  FIG. 12 shows a diagram of a configuration example of the gradation voltage generation circuit 56 of FIG.

  The gradation voltage generation circuit 56 includes a voltage generation circuit 130p for positive polarity in which the applied voltage of the liquid crystal is positive, a voltage generation circuit 130n for negative polarity in which the applied voltage is negative, a polarity reversing switch 132, including.

The voltage generation circuit 130p for positive polarity has a resistance circuit inserted between a power supply line to which the high potential side power supply voltage VDDH is supplied and a power supply line to which the low potential side power supply voltage VSSH is supplied. The node voltage divided by the circuit is output as a gradation voltage. Further, the voltage generation circuit 130p for positive polarity has a gradation selection switch 134p. Such a positive voltage generation circuit 130p can generate 26 ^{(= j)} types of gradation voltages V0 to V63. Further, the positive voltage generating circuit 130p can generate pre-buffer voltages V0m, V2m,..., V30m,. Here, the potential of the prebuffer voltage V0m is a potential equal to or lower than the gradation voltage V0 and equal to or higher than the gradation voltage V1. The potential of the prebuffer voltage V2m is a potential equal to or lower than the gradation voltage V2 and equal to or higher than the gradation voltage V3. Hereinafter, the pre-buffer voltage has the same relationship with the gradation voltage having continuous gradation values.

Therefore, the gradation voltage generation circuit 56 can generate at least ^{26 (= j)} kinds of gradation voltages. In addition, the prebuffer voltage is a voltage that is equal to or lower than the highest potential and is equal to or higher than the lowest potential among ^2k types of gradation voltages. Such a pre-buffer voltage is desirably an intermediate voltage between gradation voltages having continuous gradation values. For example, the prebuffer voltage V0m is preferably an intermediate voltage between the gradation voltages V0 and V1. For example, the pre-buffer voltage V2m is preferably an intermediate voltage between the gradation voltages V2 and V3. In this way, since the amount of charge to be charged / discharged from the prebuffer voltage can be reduced in order to supply the gradation voltage to be output in the DAC period, the period for setting a desired voltage on the source line can be shortened.

  Among the gradation selection switches 134p, the switch that outputs the gradation voltage V0P outputs the prebuffer voltage V0m and the gradation voltages V0 and V1 while switching at the time division timing. Of the gradation selection switches 134p, the switch that outputs the gradation voltage V1P outputs the prebuffer voltage V2m and the gradation voltages V2 and V3 while switching at the time division timing. Of the gradation selection switches 134p, the switch that outputs the gradation voltage V15P outputs the pre-buffer voltage V30m and the gradation voltages V30 and V31 while switching at the time division timing. Further, of the gradation selection switches 134p, the switch that outputs the gradation voltage V31P outputs the prebuffer voltage V62m and the gradation voltages V62 and V63 while switching at the time division timing.

  The negative polarity voltage generation circuit 130n also has the same configuration as the positive polarity voltage generation circuit 130p, and at the same time division timing, the pre-buffer voltage and the two gradation voltages are time-divisionally divided. The gradation voltages V0N to V31N are output.

  The polarity reversing switch 132 converts the gradation voltages V0P to V31P generated by the positive polarity voltage generation circuit 130p and the gradation voltages V0N to V31N generated by the negative polarity voltage generation circuit 130n into the polarity inversion signal POL. Are switched to the gradation signal lines V0L to V31L.

  FIG. 13 schematically shows the gradation signal lines V0L to V31L of FIG. 12 to which voltages are supplied in a time division manner. In FIG. 13, only one horizontal scanning period in which the applied voltage of the liquid crystal is positive is illustrated, and the high impedance period HZT provided between the DAC1 period DT1 and the DAC2 period DT2 is omitted.

  To the gradation signal line V0L, the gradation selection switch 134p outputs the prebuffer voltage V0m in the prebuffer period BT, the gradation voltage V0 is output in the DAC1 period DT1, and the gradation voltage in the DAC2 period DT2. V1 is output. In addition, the gradation selection switch 134p outputs to the gradation signal line V15L the prebuffer voltage V30m in the prebuffer period BT, the gradation voltage V30 in the DAC1 period DT1, and the gradation in the DAC2 period DT2. The voltage V31 is output. Further, to the gradation signal line V31L, the gradation selection switch 134p outputs the prebuffer voltage V62m during the prebuffer period BT, the gradation voltage V62 during the DAC1 period DT1, and the gradation during the DAC2 period DT2. The voltage V63 is output. The same applies to the other gradation signal lines V1L to V14L and V16L to V30L.

On the other hand, the control signals DACEN and PSI level-shifted by the level shifter 112 ₁ are input to the bypass switch circuit 114 ₁ and the PS logic unit 116 ₁ , respectively.

Figure 14 is a circuit diagram showing a configuration example of the PS logic unit 116 _1.

The PS logic unit 116 ₁ outputs the logical sum operation result of the control signal PS and the control signal PSI to the operational amplifier OP ₁ as the control signal PSOUT. Control signal PSOUT is a signal for controlling the operating current of the operational amplifier OP _1. Since the control signal PS is generated as shown in FIG. 9, the control signal PSI is generated as a mask control signal of the control signal PS. In the first drive mode, the logic of the control signal PSI is fixed.

When the control signal PSOUT is H level, the operation current of the operational amplifier OP ₁ is stopped or limited, the output of the operational amplifier OP ₁ is set to the high impedance state. When the control signal PSOUT is at the L level, the operational amplifier to generate an operating current of the OP _1, to operate the operational amplifier OP _1.

Figure 15 is a circuit diagram showing a configuration example of a bypass switch circuit 114 _1.

The bypass switch circuit 114 ₁ includes a switch element BSW ₁ . The switch element BSW ₁ bypasses the input and output of the operational amplifier OP ₁ . The switch control signal for the switch element BSW ₁ is generated based on the control signals DACON and DACEN. This switch control signal is generated based on the result of the NAND operation of the control signals DACON and DACEN. Since the control signal DACON is generated as shown in FIG. 9, the control signal DACEN is generated as a mask control signal of the control signal DACON. That is, the control signal DACON and the control signal DACEN is at the H level, the output and input of the operational amplifier OP ₁ is bypassed.

By controlling as above, in the first driving mode, the pre-buffering period BT, on the basis of the voltage pre-buffer supplied to the gray scale signal line, the operational amplifier OP ₁ drives the source line SL1. Then, in response to data of the lower 1 bit of the gray scale data, the DAC1 period DT1 or DAC2 period DT2, can bypass the switch circuit 114 ₁ supplies a grayscale voltage to the source line SL1. For example if the DAC1 period DT1 gradation voltage is supplied, the output of the operational amplifier OP ₁ is set in a high impedance state, via the switch BSW ₁ bypass switching circuit 114 _1, in time division gray scale signal line The supplied gradation voltage is supplied to the source line SL1. Also, when the gradation voltage is supplied to, for example, DAC2 period DT2, the output of the operational amplifier OP ₁ is set in a high impedance state, via the switch BSW ₁ bypass switching circuit 114 _1, time to grayscale signal line The divided gradation voltage is supplied to the source line SL1. Control signal PS is in a period of H level, the output of the operational amplifier OP ₁ is set to the high impedance state. During the period when the control signal DACON is at the L level, the switch element BSW ₁ is set to the OFF state. Accordingly, the output to the source line is set to the high impedance state during the period when the control signal PS is at the H level and the period when the control signal DACON is at the L level.

8 to 15, the case where j is 6 and k is 1 has been described. However, the same applies to the case where j is 2 to 5, 7 or more. The same applies when k is 2 or more. For example, when k is 2, within one horizontal scanning period, the period during which the control signal PS is at the L level is shortened, and 22 ^{(= k)} types of periods during which the control signal DACON is at the H level are provided. If the control signals KK1, KK2, KK3, and KK4 are set to the H level, those skilled in the art can generate the control signal DACEN as in FIG. 11 and the above.

3.1.2 sample hold circuit embodiment, by adding a sample-hold function to the operational amplifier OP _1, at the falling edge of the DAC period (DAC2 period) of the gate line after the end of the selection voltage, the hold voltage to the source line You may be in the state of outputting. By doing so, even if the leakage current of the LCD panel 20 is large, it is not necessary to change the potential of the source line, so that a desired voltage can be written to the pixel electrode.

FIG. 16 shows a circuit diagram of a configuration example of a sample and hold circuit provided in the output circuit OUT ₁ . Although only the output circuit OUT ₁ is shown in FIG. 16, the same parts as those in FIG.

The sample hold circuit SH ₁ includes a voltage follower-connected operational amplifier OP ₁ , a sampling switch element SSW _1, and a hold capacitor CP ₁ . The sampling switch element SSW ₁ is inserted in series between the output of the voltage selection circuit DEC _{1 and} the input of the operational amplifier OP ₁ . The bypass switch circuit 114 ₁ is supplied with the output of the voltage selection circuit DEC ₁ . The input of the operational amplifier OP _1, one end of the holding capacitor CP ₁ is connected. The other end of the holding capacitor CP _1, for example, a ground power supply voltage VSS is supplied.

Figure 17 is a timing diagram of an operation example of the sample-and-hold circuit SH ₁ of FIG. 16.

The normal operational amplifier OP ₁ drives the source line based on the pre-buffer voltage during the pre-buffer period BT, and supplies the gray scale voltage to the source line via the bypass switch circuit 114 ₁ , for example, during the subsequent DAC 1 period DT _1. It shall be. At this time, the switch control signal ST for switching control of the sampling switch elements SSW ₁ becomes H level in the pre-buffering period BT and DAC1 period DT1. Such a switch control signal ST is also generated in the logic unit 94. On the other hand, unlike FIG. 9, the control signal PS becomes L level after the DAC1 period DT1 ends, and the state continues until the end timing of the last DAC period (when the k is 2, the DAC2 period DT2).

With such a control signal, the sampling switch element SSW ₁ is set to the ON state by the switch control signal ST in the pre-buffer period BT. In the pre-buffering period BT, the operational amplifier OP ₁ drives the source line based on the voltage pre-buffer. Thereafter, the DAC1 period DT1, gray scale voltage through the bypass switch circuit 114 ₁ is supplied to the source line. However, the DAC1 period DT1, the control signal PS is output of the operational amplifier OP ₁ because it is L level is set to the high impedance state, since the sampling switch elements SSW ₁ is turned on, the hierarchical charge corresponding to the voltage between the tone voltage and the ground power supply voltage VSS is accumulated in the hold capacitor CP _1.

Thereafter, the switch control signal ST becomes L level, the control signal PS becomes L level, and the hold period is started. In the hold period, the sampling switch element SSW ₁ is set in the OFF state, and a voltage corresponding to the electric charge accumulated in the hold capacitor CP ₁ is supplied to the input of the operational amplifier OP ₁ . Thus, the operational amplifier OP ₁ is in the hold period, it can be output to the source line voltage sampled in the sampling period as a hold voltage. Accordingly, since the gate line selection voltage falls during the hold period, even if the leakage current of the LCD panel 20 is large, it is not necessary to change the potential of the source line, so that a desired voltage is written to the pixel electrode. Will be able to.

18 shows an example of the timing of the first drive mode in the case of applying the sample and hold circuit SH _1. In FIG. 18, it is assumed that j is 6 and k is 1.

  In FIG. 18, the high impedance period HZT is shown as one clock, but the high impedance period HZT is a period of two clocks or more, or a period of several tens of nanoseconds that can be arbitrarily set by the delay element. There may be.

By applying the sample hold circuit SH ₁ instead of the operational amplifier OP ₁ to the output circuit OUT _1, when the LSB (Least Significant Bit, synonymous with lower 1 bit) of the gradation data is “0”, the DAC 2 period DT 2 The voltage is supplied to the source line even in the DAC2 period DT2 without the source line being set to the high impedance state. On the other hand, when the LSB of the gradation data is "1", since the voltage need only be supplied to the source line by DAC2 period DT2, the sample and hold circuit SH ₁ has a high impedance output to the source line in DAC1 period DT1 Set to state.

Figure 19 shows another example of the timing of the first drive mode in the case of applying the sample and hold circuit SH _1. In FIG. 19, it is assumed that j is 6 and k is 2.

When the lower 2 bits of data are “00”, the operational amplifier of each output circuit performs impedance conversion based on the prebuffer voltage and drives the source line during the prebuffer period BT. In subsequent DAC1 period DT1, and a gradation voltage corresponding to the lower 2-bit data "00" of the two ^two gray scale voltages supplied in time division gray scale signal line, to bypass the operational amplifier source Supply to the wire. At this time, the sample-and-hold circuit SH ₁ samples the gradation voltage DAC1 period DT1, after the end of the DAC1 period DT1, until the end timing of DAC4 period DT4, supplying the sample and hold circuit SH ₁ is the hold voltage to the source line To do.

When the lower 2 bits of data are “01”, the operational amplifier of each output circuit performs impedance conversion based on the prebuffer voltage during the prebuffer period BT to drive the source line. In the subsequent DAC1 period DT1, the output to the source line is set to a high impedance state. Then, the DAC2 period DT2, and a gradation voltage corresponding to the lower 2-bit data "01" of the two ^two gray scale voltages supplied in time division gray scale signal line, to bypass the operational amplifier source Supply to the wire. At this time, the sample-and-hold circuit SH ₁ samples the gradation voltage DAC2 period DT2, after the end of DAC2 period DT2, until the end timing of DAC4 period DT4 after the start of DAC3 period DT3, the sample and hold circuit SH ₁ is, A hold voltage is supplied to the source line.

When the lower 2 bits of data are “10”, the operational amplifier of each output circuit performs impedance conversion based on the pre-buffer voltage and drives the source line during the pre-buffer period BT. During the subsequent DAC1 period DT1 to the start of the DAC3 period DT3, the output to the source line is set to a high impedance state. Then, the DAC3 period DT3, and a gradation voltage corresponding to the lower 2-bit data "10" of the two ^two gray scale voltages supplied in time division gray scale signal line, to bypass the operational amplifier source Supply to the wire. At this time, the sample-and-hold circuit SH ₁ samples the gradation voltage DAC3 period DT3, the DAC4 period DT4, the sample and hold circuit SH ₁ supplies the holding voltage to the source line.

When the lower 2 bits of data are “11”, the operational amplifier of each output circuit performs impedance conversion based on the pre-buffer voltage and drives the source line during the pre-buffer period BT. During the subsequent DAC1 period DT1 to the start of the DAC4 period DT4, the output to the source line is set to the high impedance state. Then, in DAC4 period DT4, and a gradation voltage corresponding to the lower 2-bit data "11" of the two ^two gray scale voltages supplied in time division gray scale signal line, to bypass the operational amplifier source Supply to the wire. Thereafter, the output to the source line is set to the high impedance state until the next selection period is started. Thus, when the lower 2 bits of data are “11”, the sample hold circuit SH ₁ does not need to supply the hold voltage to the source line.

As described above, the operational amplifier OP ₁ (output buffer in a broad sense) samples the gradation voltage selected by the voltage selection circuit DEC ₁ during the sampling period, and outputs the gradation voltage as the hold voltage during the hold period. The sample-and-hold circuit SH ₁ can be used. Then, the sample hold circuit SH ₁ has a gradation voltage output period corresponding to the lower k bits of the gradation data in any one of the first to (2 ^k −1) gradation voltage output periods. In some cases, the gradation voltage sampled during the gradation voltage output period corresponding to the lower-order k-bit data of the gradation data is used as the hold voltage, and the second ^k after the gradation voltage output period following the gradation voltage output period. Can be output to the source line over the period up to the grayscale voltage output period. For example, in the case of FIG. 19, the DAC2 period DT2 corresponding to the lower two bits of data “01” of the gradation data is the DAC1 period DT1 to DAC3 period DT3 (first to (2 ² −1) gradation voltage output periods. ) One of the periods. In this case, the sample and hold circuit SH ₁ is a grayscale voltage sampled DAC2 period DT2 corresponding to the data "01" in the lower two bits of the gradation data as a hold voltage, DAC 3 period DT3 later, DAC 4 period DT4 (No. it can be output over a period of up to 2 ^second gray-scale voltage output period) to the source line.

3.2 in the second drive mode the first driving mode, 1 in the selection period, the source line is driven only by the operational amplifier OP ₁ to the pre-buffer period, the DAC period provided DAC1 period DT1 later, There is a possibility that charge cannot be charged or discharged before the source line reaches the target voltage. When the charge cannot be sufficiently charged / discharged, the voltage of the source line does not reach the target voltage, resulting in degradation of image quality. Therefore, in the second driving mode, a pre-buffer period is provided immediately before each DAC period, so that the voltage of the source line reaches the target voltage even in a short writing time.

In such a second drive mode, the source driver 30 has the gradation voltage generation circuit 56 in which 2 ^{(jk )} types of gradation signal lines are provided for each of 2 ^(jk) gradation signal lines. selected from among the gradation voltages supplied by time division to 2 ^k kinds of gradation voltages gradation value are continuous in one selection period. The DAC 58 (each DEC) selects one gradation signal line from 2 ^(j−k) gradation signal lines based on the upper (j−k) bit data of the gradation data. During one selection period, a qth (1 ≦ q ≦ 2 ^k , q is an integer) pre-buffer period (buffer output period) BTq and a DACq period DTq (qth gradation) after the qth prebuffer period voltage output period) and the pre-buffering period BT1~BT2 ^k (buffer output period of the first to ^{2 k)} and DAC1 period DT1～DAC2 ^k period DT2 ^k (first to gradation voltage output of the ^{2 k} as one set Period). Then, the pre-buffering period corresponding to the data of k low-order bits of the gradation data of the pre-buffering period BT1~BT2 ^k BTr (a ^{r (1 ≦ r ≦ 2 k} , r buffer output period is an integer)), the output The circuit is based on the gradation voltage corresponding to the lower k bits of the 2 ^k kinds of gradation voltages of the gradation signal line selected based on the upper (j−k) bits of the gradation data. Drive the source line. Thereafter, during the DACr period DTr (the r-th gradation voltage output period), one of the 2 ^k kinds of gradation voltages is supplied to the source line by bypassing the input and output of the output circuit. Note that the gradation voltage supplied from the voltage selection circuit to the output buffer in the pre-buffer period BTr (rth buffer output period) and the switching element from the voltage selection circuit in the DACr period DTr (rth gradation voltage output period) The grayscale voltage supplied to may be the same voltage.

  FIG. 20 shows an example of the timing of the second drive mode of the source driver in this embodiment. In FIG. 20, it is assumed that j is 6 and k is 1.

  In FIG. 20, the high impedance period HZT is shown as one clock, but the high impedance period HZT is a period of two clocks or more, or a period of several tens of nanoseconds that can be arbitrarily set by the delay element. There may be.

In the second drive mode, 2 (= 2 ¹ ) sets of pre-buffer period and DAC period are provided in one horizontal scanning period. When one horizontal scanning period is started, a pre-buffer period BT1 is first started. In the pre-buffer period BT1, the operational amplifier of each output circuit performs impedance conversion based on the gradation voltage selected in the DAC1 period DT1 provided thereafter, and drives the source line. A DAC1 period DT1 is provided after the prebuffer period BT1, a prebuffer period BT2 is provided after the DAC1 period DT1, and a DAC2 period DT2 is provided after the prebuffer period BT2. The pre-buffer period BT1 and the DAC1 period DT1 are synchronized with the time division timing of the gradation voltage corresponding to the odd gradation supplied to each gradation signal line. The pre-buffer period BT2 and the DAC2 period DT2 are synchronized with the time division timing of the gradation voltage corresponding to the even gradation supplied to each gradation signal line. The output to the source line is set to the high impedance state between the pre-buffer period BT1 and the DAC1 period DT1, between the DAC1 period DT1 and the pre-buffer period BT2, and between the pre-buffer period BT2 and the DAC2 period DT2. A high impedance period HZT is provided. By providing the high-impedance period HZT, the effect of switching between the gradation voltage in the pre-buffer period and the gradation voltage in the DAC period, and the effect of switching between the gradation voltage in the DAC period and the gradation voltage in the pre-buffer period are applied to the source line. It is not necessary to give it and can prevent deterioration of image quality.

  When the lower 1 bit data is “0”, the source line is driven by impedance-converting, for example, a gradation voltage corresponding to an odd gradation in the pre-buffer period BT1. Further, the operational amplifier is bypassed and supplied to the source line in the DAC1 period DT1 using the same gradation voltage as in the prebuffer period BT1. In the pre-buffer period BT2 and the DAC2 period DT2, the output to the source line is set to a high impedance state.

  When the lower 1 bit data is “1”, the output to the source line is set to the high impedance state in the pre-buffer period BT1 and the DAC1 period DT1. Then, during the pre-buffer period BT2, for example, the source line is driven by impedance conversion of a gradation voltage corresponding to an even gradation. Further, the operational amplifier is bypassed and supplied to the source line in the DAC2 period DT2 by using the same gradation voltage as in the prebuffer period BT2.

  The selection voltage of the gate line rises in the pre-buffer period BT1 and falls in the DAC2 period DT2. The voltage of the source line at the rise of the selection voltage of the gate line is written into the pixel electrode. When the lower 1 bit data is “0”, the output to the source line is set to the high impedance state when the selection voltage of the gate line falls, but the electric potential accumulated by the charge accumulated by the parasitic capacitance of the source line Therefore, a desired voltage can be written to the pixel electrode.

  FIG. 21 shows another example of the timing of the second drive mode of the source driver in this embodiment. In FIG. 21, it is assumed that j is 6 and k is 2.

  In the case of FIG. 21, a pre-buffer period BT1 (first buffer output period), a DAC1 period DT1 (first gradation voltage output period), a pre-buffer period BT2 (second buffer output period), and a DAC2 period DT2 (first) 2 gradation voltage output period), pre-buffer period BT3 (third buffer output period), DAC3 period DT3 (third gradation voltage output period), pre-buffer period BT4 (fourth buffer output period), DAC4 A period DT4 (fourth gradation voltage output period) is provided. Between the prebuffer period BT1 and the DAC1 period DT1, between the DAC1 period DT1 and the prebuffer period BT2, between the prebuffer period BT2 and the DAC2 period DT2, between the DAC2 period DT2 and the prebuffer period BT3, The output to the source line is set to a high impedance state between the period BT3 and the DAC3 period DT3, between the DAC3 period DT3 and the prebuffer period BT4, and between the prebuffer period BT4 and the DAC4 period DT4, respectively. A high impedance period HZT is provided.

When the lower two bits of the data is "00", corresponding to the pre-buffering period BT1, lower 2-bit data "00" of the two ^two gray scale voltages supplied in time division gray scale signal line floors The operational amplifier of each output circuit performs impedance conversion based on the regulated voltage and drives the source line. In the subsequent DAC1 period DT1, the same gradation voltage as in the prebuffer period BT1 is supplied to the source line by bypassing the operational amplifier. Thereafter, the output to the source line is set to the high impedance state until the next selection period is started.

When the lower 2 bits of data are “01”, the output to the source line is set to the high impedance state until the pre-buffer period BT2 is started. Then, the pre-buffering period BT2, operation of the output circuits on the basis of a gradation voltage corresponding to the lower 2-bit data "01" of the two ^two gray scale voltages supplied in time division gray scale signal line The amplifier performs impedance conversion and drives the source line. In the subsequent DAC2 period DT2, the same gradation voltage as in the prebuffer period BT2 is supplied to the source line by bypassing the operational amplifier. Thereafter, the output to the source line is set to the high impedance state until the next selection period is started.

When the lower 2 bits of data are “10”, the output to the source line is set to the high impedance state until the pre-buffer period BT3 is started. Then, the pre-buffering period BT3, operation of the output circuits on the basis of a gradation voltage corresponding to the lower 2-bit data "10" of the two ^two gray scale voltages supplied in time division gray scale signal line The amplifier performs impedance conversion and drives the source line. In the subsequent DAC3 period DT3, the same gradation voltage as in the pre-buffer period BT3 is supplied to the source line by bypassing the operational amplifier. Thereafter, the output to the source line is set to the high impedance state until the next selection period is started.

When the lower 2 bits of data are “11”, the output to the source line is set to the high impedance state until the pre-buffer period BT4 is started. Then, the pre-buffering period BT4, operation of the output circuits on the basis of a gradation voltage corresponding to the lower 2-bit data "11" of the two ^two gray scale voltages supplied in time division gray scale signal line The amplifier performs impedance conversion and drives the source line. In the subsequent DAC4 period DT4, the same gradation voltage as in the pre-buffer period BT4 is supplied to the source line by bypassing the operational amplifier. Thereafter, the output to the source line is set to the high impedance state until the next selection period is started.

  In the case of FIG. 21, the selection voltage of the gate line rises within the pre-buffer period BT1 and falls within the DAC4 period DT4. When the lower 2 bits of data are “00”, “01”, “10”, the output to the source line is set to the high impedance state when the selection voltage of the gate line falls, but the source line parasitic Since the potential is held by the charge accumulated by the capacitor, a desired voltage can be written to the pixel electrode.

  By adopting such a driving method in the second driving mode, the number of gradation signal lines can be significantly reduced without reducing the number of gradations, and the layout area of the source driver can be reduced without degrading the image quality. Cost reduction can be achieved.

3.2.1 Detailed Configuration Example Next, a hardware configuration example for realizing the second drive mode will be described. Since the second drive mode can be realized using the hardware shown in FIG. 8 that realizes the first drive mode, detailed description thereof is omitted. In the following, it is assumed that j is 6 and k is 1.

  FIG. 22 shows an operation timing example of the read clock RCLK, the control signals PS, DACON, KK1, and KK2 of FIG. 8 in the second drive mode.

  For example, when the second drive mode is designated by the drive mode setting register of the logic unit 94, the read clock RCLK and the control signals PS, DACON, KK1, and KK2 having the timing shown in FIG. 22 are generated.

When one horizontal scanning period (one selection period) is started, the logic unit 94 generates a pulse of the read clock RCLK. For example the falling of the read clock RCLK, grayscale data D to the line latch 54 ₁ [5: 0] is captured.

  Then, the logic unit 94 outputs a control signal PS that changes from the H level to the L level after a given period from the falling edge of the read clock RCLK. At this time, the control signal PS becomes L level only during the period corresponding to the pre-buffer period BT1, and then changes to H level.

  The control signal DACON changes from the L level to the H level after a given period from the timing when the control signal PS changes to the H level. At this time, the control signal DACON becomes H level only during the period corresponding to the DAC1 period DT1.

  The control signal PS changes from the H level to the L level after a given period from the timing when the control signal DACON changes to the L level. At this time, the control signal PS becomes L level only during the period corresponding to the pre-buffer period BT2, and then changes to H level.

  The control signal DACON changes from the L level to the H level after a given period from the timing when the control signal PS changes to the H level. At this time, the control signal DACON becomes H level only during the period corresponding to the DAC2 period DT2.

  By providing a given period between the timing when the control signal PS changes from the L level to the H level and the timing when the control signal DACON changes from the L level to the H level, the high impedance period HZT can be provided. It has become. Further, the high impedance period HZT can be provided by providing a given period between the timing when the control signal DACON changes from the H level to the L level and the timing when the control signal PS changes from the H level to the L level. It can be done.

  The control signals KK1 and KK2 are at the H level in the DAC1 period DT1 and the DAC2 period DT2 as in the first drive mode.

  In the second drive mode, the control signal KK_MODE in FIG. 11 is at the H level. Therefore, the control signals PSI and DACEN are generated as follows by the circuit shown in FIG.

  When the lower 1 bit (least significant bit) of the gradation data is “0”, when the control signal KK1 is at the H level and the control signal KK2 is at the L level, the control signal DACEN is at the H level and the control signal PSI is at the L level. When signal KK1 is at L level and control signal KK2 is at H level, control signal DACEN is at L level and control signal PSI is at H level.

  When the lower 1 bit (least significant bit) of the gradation data is “1”, the control signal DACEN is at the L level and the control signal PSI is at the H level when the control signal KK1 is at the H level and the control signal KK2 is at the L level. When signal KK1 is at L level and control signal KK2 is at H level, control signal DACEN is at H level and control signal PSI is at L level.

Such gray-scale data DOUT [5: 1], the control signal DACEN, PSI is level-shifted by the level shifter 112 _1. The gradation data DOUT [5: 1] after the level shift is input to the voltage selection circuit DEC ₁ of the DAC 58. The voltage selection circuit DEC ₁ is connected to the gradation signal lines V 0 L to V 31 L from the gradation voltage generation circuit 56.

  FIG. 23 schematically shows the grayscale signal lines V0L to V31L of FIG. 8 to which a voltage is supplied in a time division manner in the second drive mode. In FIG. 23, only one horizontal scanning period in which the voltage applied to the liquid crystal is positive is shown, and the high impedance period HZT is not shown.

  The gradation voltage V0 is output to the gradation signal line V0L in the pre-buffer period BT1 and the DAC1 period DT1 by the gradation selection switch 134p. Thereafter, during the pre-buffer period BT2 and the DAC2 period DT2, the gradation voltage V1 is output to the gradation signal line V0L. Further, the prebuffer voltage V30 is output to the grayscale signal line V15L in the prebuffer period BT1 and the DAC1 period DT1 by the grayscale selection switch 134p. Thereafter, during the pre-buffer period BT2 and the DAC2 period DT2, the gradation voltage V31 is output to the gradation signal line V15L.

  Further, the gradation voltage V62 is output to the gradation signal line V31L in the pre-buffer period BT1 and the DAC1 period DT1 by the gradation selection switch 134p. Thereafter, during the pre-buffer period BT2 and the DAC2 period DT2, the gradation voltage V63 is output to the gradation signal line V31L. The same applies to the other gradation signal lines V1L to V14L and V16L to V30L.

The signals as described above are input to the PS logic unit 116 ₁ shown in FIG. 14 and the bypass switch circuit 114 ₁ shown in FIG. 15, thereby realizing the second drive mode as shown in FIG. That is, in the second drive mode, 2 ^(j−k) (j is an integer of 2 or more, 0 <k <j, k is an integer) 2 ^j types of gradation signal lines are provided for each gradation signal line. selected from among the gradation voltages, 2 ^k kinds of gradation voltages gradation value is continuously supplied in time division during one selecting period. Then, one gradation signal line is selected from the 2 ^(j−k) gradation signal lines based on the upper (j−k) bit data of the gradation data. During one selection period, a pre-buffer period BTq (qth (1 ≦ q ≦ 2 ^k , q is an integer) buffer output period) and a DACq period DTq (qth grayscale voltage output after the prebuffer period BTq) Period) as a set, pre-buffer periods BT1 to BT2 ^k (first to second ^k buffer output periods) and DAC1 periods DT1 to DAC2 ^k periods DT2 ^k (first to second ^k grayscale voltage output periods) And are provided. Prebuffers period BT1～BT2 ^k prebuffers period BTr corresponding to the data of k low-order bits of the gray scale data of (the ^{r (1 ≦ r ≦ 2 k} , r is the buffer output period of an integer)), the output buffer The source line based on the gradation voltage corresponding to the lower k bits of the 2 ^k kinds of gradation voltages of the gradation signal line selected based on the upper (j−k) bit data of the gradation data Is driven, in the DACr period DTr (the r-th gradation voltage output period), one of the 2 ^k kinds of gradation voltages is bypassed between the input and output of the output buffer and is supplied to the source line. Supply.

  It is desirable to set the output to the source line in a high impedance state between the pth (1 ≦ p <k, p is an integer) grayscale voltage output period and the (p + 1) th buffer output period. . By doing so, it is possible to prevent deterioration in image quality without affecting the source line due to the switching of the gradation voltage.

  In the above description, the case where j is 6 and k is 1 is described, but the same applies to the case where j is 2 to 5, 7 or more. The same applies when k is 2 or more. For example, when k is 2, four sets of pre-buffer periods and DAC periods are provided in one horizontal scanning period.

3.2.2 Sample and Hold Circuit Also in the second drive mode, the operational amplifier OP ₁ of the output circuit OUT ₁ may be used as the sample and hold circuit of FIG. 16, as in the first drive mode. In this case, the hold voltage can be output to the source line when the selection voltage of the gate line falls after the DAC period ends. By doing so, even if the leakage current of the LCD panel 20 is large, it is not necessary to change the potential of the source line, so that a desired voltage can be written to the pixel electrode.

Figure 24 shows an example of the timing of the second driving mode in the case of applying the sample and hold circuit SH _1. In FIG. 24, j is 6 and k is 1.

  In FIG. 24, the high impedance period HZT is shown as one clock, but the high impedance period HZT is a period of two clocks or more, or a period of several tens of nanoseconds that can be arbitrarily set by the delay element. There may be.

By applying the sample hold circuit SH ₁ instead of the operational amplifier OP ₁ to the output circuit OUT ₁ , when the LSB of the gradation data is “0”, the source line is in a high impedance state in the pre-buffer period BT 2 and the DAC 2 period DT 2 The voltage is supplied to the source line even in the pre-buffer period BT2 and the DAC2 period DT2. On the other hand, when the LSB of the gradation data is "1", since the voltage need only be supplied to the source line by DAC2 period DT2, the sample and hold circuit SH ₁ is to the source line in the pre-buffering period BT1 and DAC1 period DT1 Set the output of to high impedance.

Figure 25 shows another example of the timing of the second driving mode in the case of applying the sample and hold circuit SH _1. In FIG. 25, it is assumed that j is 6 and k is 2.

When the lower 2 bits of data are “00”, the operational amplifier of each output circuit performs impedance conversion based on the prebuffer voltage and drives the source line during the prebuffer period BT1. In subsequent DAC1 period DT1, and a gradation voltage corresponding to the lower 2-bit data "00" of the two ^two gray scale voltages supplied in time division gray scale signal line, to bypass the operational amplifier source Supply to the wire. At this time, the sample-and-hold circuit SH ₁ samples the gradation voltage DAC1 period DT1, after the end of the DAC1 period DT1, once set the source lines in a high impedance state, until the end timing of DAC4 period DT4, sample-and-hold circuit SH ₁ supplies the holding voltage to the source line.

When the lower 2 bits of data are “01”, the operational amplifier of each output circuit performs impedance conversion based on the prebuffer voltage in the prebuffer period BT2, and drives the source line. Therefore, the output to the source line is set to the high impedance state after one selection period is started until the pre-buffer period BT2 is started. Then, the DAC2 period DT2, and a gradation voltage corresponding to the lower 2-bit data "01" of the two ^two gray scale voltages supplied in time division gray scale signal line, to bypass the operational amplifier source Supply to the wire. At this time, the sample hold circuit SH ₁ samples the grayscale voltage in the DAC 2 period DT 2, and once the DAC 2 period DT 2 ends, sets the source line to a high impedance state, and performs the sample hold until the end timing of the DAC 4 period DT 4. circuit SH ₁ supplies the holding voltage to the source line.

When the lower 2 bits of data are “10”, the operational amplifier of each output circuit performs impedance conversion based on the pre-buffer voltage and drives the source line during the pre-buffer period BT3. Therefore, the output to the source line is set to the high impedance state after one selection period is started and before the prebuffer period BT3 is started. Then, the DAC3 period DT3, and a gradation voltage corresponding to the lower 2-bit data "10" of the two ^two gray scale voltages supplied in time division gray scale signal line, to bypass the operational amplifier source Supply to the wire. At this time, the sample hold circuit SH ₁ samples the grayscale voltage of the DAC 3 period DT 3, and once the DAC 3 period DT 3 ends, sets the source line to a high impedance state, and performs the sample hold until the end timing of the DAC 4 period DT 4. circuit SH ₁ supplies the holding voltage to the source line.

When the lower 2 bits of data are “11”, the operational amplifier of each output circuit performs impedance conversion based on the pre-buffer voltage and drives the source line during the pre-buffer period BT. Therefore, the output to the source line is set to the high impedance state after one selection period is started and before the prebuffer period BT4 is started. Then, in DAC4 period DT4, and a gradation voltage corresponding to the lower 2-bit data "11" of the two ^two gray scale voltages supplied in time division gray scale signal line, to bypass the operational amplifier source Supply to the wire. Thereafter, the output to the source line is set to the high impedance state until the next selection period is started. Thus, when the lower 2 bits of data are “11”, the sample hold circuit SH ₁ does not need to supply the hold voltage to the source line.

As described above, the operational amplifier OP ₁ (output buffer in a broad sense) samples the gradation voltage selected by the voltage selection circuit DEC ₁ during the sampling period, and outputs the gradation voltage as the hold voltage during the hold period. The sample-and-hold circuit SH ₁ can be used. The buffer output period and the gradation voltage output period corresponding to the lower-order k-bit data of the gradation data are pre-buffer periods BT1 to BT (2 ^k −1) and DAC periods DT1 to DT (2 ^k −1) ( The sample-and-hold circuit SH ₁ outputs the grayscale data in any of the first to (2 ^k -1) buffer output periods and the first to (2 ^k -1) gray scale voltage output periods The grayscale voltage sampled in the DAC period corresponding to the lower-order k-bit data is set to the high impedance state once in the DAC period, and then the DAC2 ^k period DT2 ^k (second ^k grayscale voltage output period) ) Can be output as a hold voltage over a period up to. For example, in the case of FIG. 25, the DAC2 period DT2 corresponding to the lower two bits data “01” of the gradation data is the DAC1 period DT1 to DAC3 period DT3 (first to (2 ² −1) gradation voltage output periods. ) One of the periods. In this case, the sample and hold circuit SH ₁ is a grayscale voltage sampled DAC2 period DT2 corresponding to the data of the lower 2 bits of the gradation data "01" as the hold voltage, DAC2 period DT2 later, once the high source line it can be output over a period of up to set the impedance DAC4 period DT4 (second ^second gray-scale voltage output period) to the source line.

3.3 Output Order Specification In this embodiment, in the first and second drive modes, for example, when k is 1, for example, a voltage corresponding to an even gradation in the DAC1 period DT1, and an odd number in the DAC2 period DT2, for example. It has been described that the driving is performed in the order of voltages corresponding to the gradations. However, in this embodiment, the order of gradation voltages output in each DAC period can be changed during one selection period. In this way, depending on the characteristics of the LCD panel 20 and the display image, the frequency is lowered and flicker and the like can be reliably prevented, and the display image can be prevented from deteriorating.

  For this reason, the control register unit including the drive mode setting register described above includes an output order designation register, and the source driver 30 can designate the output order of the gradation voltages output in a plurality of DAC periods in one selection period. It is like that.

  FIG. 26 shows a main configuration part of the logic unit 94 including the control register unit.

  The logic unit 94 includes a control register unit 200 and a control timing generation unit 210. The control register unit 200 includes a plurality of control registers, and set values are set in the control registers by the display controller 38 or the host. The set value set in each control register of the control register unit 200 is supplied to the control timing generation unit 210. The control timing generation unit 210 is supplied with a clock (for example, a dot clock signal DCLK), and the count number of the clock matches the set value of the control register based on a given reference timing (the leading timing of one horizontal scanning period). A desired control signal is changed at the timing.

  FIG. 27 shows an outline of the configuration of the control register unit 200 of FIG.

  In FIG. 27, a case where k is 1 will be described. That is, the configuration of the control register unit 200 when driven at the timing shown in FIG. 6 and FIG. 24 is shown.

  The control register unit 200 includes a source output on timing setting register 220, a source output off timing setting register 222, a gate signal selection timing setting register 224, a gate signal non-selection timing setting register 226, a drive mode setting register 228, first to third. Drive switching timing setting registers 230, 232, and 234, and an output order designation register 238.

  The source output on timing setting register 220 is a register for designating the timing for turning on the source output during one horizontal scanning period. For example, the source output on timing setting register 220 is set at the timing for turning on the source output with reference to the head timing of one horizontal scanning period. The count number of the corresponding clock is set as the set value. The source output off timing setting register 222 is a register for designating the timing for turning off the source output during one horizontal scanning period. For example, the source output off timing setting register 222 is set at a timing for turning off the source output with reference to the head timing of one horizontal scanning period. The count number of the corresponding clock is set as the set value.

  The gate signal selection timing setting register 224 is a register for designating timing for supplying a selection voltage to the gate signal during one horizontal scanning period. For example, the gate signal selection timing setting register 224 is selected as a gate signal based on the start timing of one horizontal scanning period. The count value of the clock corresponding to the timing for supplying the voltage is set as the set value. The gate signal non-selection timing setting register 226 is a register for designating the timing for supplying the non-selection voltage to the gate signal during one horizontal scanning period. For example, the gate signal non-selection timing setting register 226 is based on the leading timing of one horizontal scanning period. The count value of the clock corresponding to the timing for supplying the non-selection voltage is set as the set value.

  The drive mode setting register 228 is a register for designating the first or second drive mode as described above as the drive method.

  The first drive switching timing setting register 230 is a register for designating the switching timing from the pre-buffer period BT1 to the DAC1 period DT1, and corresponds to the switching timing, for example, based on the start timing of one horizontal scanning period. The clock count is set as the set value.

  The second drive switching timing setting register 232 is a register for designating the switching timing from the DAC1 period DT1 to the DAC2 period DT2 in the first driving mode. For example, the second driving switching timing setting register 232 is based on the start timing of one horizontal scanning period. A clock count corresponding to the switching timing is set as a set value. The second drive switching timing setting register 232 is a register for designating the switching timing from the DAC1 period DT1 to the prebuffer period BT2 in the second driving mode. For example, the second driving switching timing setting register 232 is based on the start timing of one horizontal scanning period. In addition, the clock count corresponding to the switching timing is set as the set value.

  The third drive switching timing setting register 234 is a register for designating the switching timing from the pre-buffer period BT2 to the DAC2 period DT2 in the second driving mode. For example, the third driving switching timing setting register 234 is based on the start timing of one horizontal scanning period. The clock count corresponding to the switching timing is set as the set value.

  The output order designation register 238 is a register for designating the output order of gradation voltages output in the pre-buffer period and the DAC period in one selection period.

  Based on the setting value of each control register of the control register unit 200 as described above, the control timing generation unit 210 generates the control signals KK_MODE, KK1, KK2, PS, and DACON.

  FIG. 28 is an explanatory diagram of drive modes that can be set by the drive mode setting register 228. When the parameters P1 and P0 are set to “00” according to the set value of the drive mode setting register 228, the control timing generation unit 210 generates a control signal so as to realize the first drive mode described above. That is, during the pre-buffer period BT, an intermediate voltage between the gradation voltage corresponding to the even gradation and the gradation voltage corresponding to the odd gradation is driven as the pre-buffer voltage, and the even voltage is applied to the DAC 1 period DT1 and the DAC 2 period DT2, respectively. A gradation voltage corresponding to gradation or odd gradation is output.

  Even when the parameters P1 and P0 are set to “01” according to the setting value of the drive mode setting register 228, the control timing generation unit 210 performs the above-described process similarly to when the parameters P1 and P0 are set to “00”. A control signal is generated so as to realize the first drive mode. However, in this case, in the prebuffer period BT, the grayscale voltage output in the DAC1 period DT1 is output as the prebuffer voltage. Therefore, it can be said that the pre-buffer voltage is one of the gradation voltages generated by the gradation voltage generation circuit 56.

  When the parameters P1 and P0 are set to “10” according to the set value of the drive mode setting register 228, the control timing generation unit 210 generates a control signal so as to realize the second drive mode described above. That is, the gradation voltage output in the DAC1 period DT1 is output as the prebuffer voltage in the prebuffer period BT1, and the gradation voltage output in the DAC2 period is prebuffered in the prebuffer period BT2 after the DAC1 period DT1. Is output as a voltage.

  FIG. 29 is an explanatory diagram of the parameters P2 to P0 of the output order designation register 238.

  When “000” is set in the parameters P2 to P0 according to the set value of the output order specification register 238, the control timing generation unit 210 performs gradation voltage output in the DAC1 period DT1 with a period of two frames and one scanning line. A control signal is generated so that the grayscale voltage output in the DAC2 period DT2 is switched. That is, with a period of two frames and one scanning line, for example, a gradation voltage corresponding to an odd gradation is output in the DAC1 period DT1, a gradation voltage corresponding to an even gradation is output in the DAC2 period DT2, or an even gradation is supported. The gradation voltage thus output is output in the DAC1 period DT1, and the gradation voltage corresponding to the odd gradation is output in the DAC2 period DT2.

  When “001” is set in the parameters P2 to P0 of the output order specification register 238, the control timing generation unit 210 outputs the grayscale voltage output in the DAC1 period DT1 and the DAC2 period DT2 with a period of two frames. A control signal is generated so as to replace the gradation voltage.

  When “010” is set in the parameters P2 to P0 of the output order specification register 238, the control timing generation unit 210 performs the polarity inversion driving in the DAC1 period DT1 in which the applied voltage of the liquid crystal is positive. A control signal is generated so as to output a gradation voltage corresponding to the odd gradation and output a gradation voltage corresponding to the even gradation in the DAC2 period DT2 of the positive polarity period. In addition, the gradation voltage corresponding to the odd gradation is output in the DAC1 period DT1 when the applied voltage of the liquid crystal is negative, and the gradation voltage corresponding to the even gradation is output during the DAC2 period DT2 of the positive period. The control signal is generated as follows.

  When “011” is set to the parameters P2 to P0 of the output order specification register 238, the control timing generation unit 210 performs control so that the output is performed in the reverse order to that when “010” is set to the parameters P2 to P0. Generate a signal.

  When “100” is set in the parameters P2 to P0 of the output order specification register 238, a gradation voltage corresponding to an odd gradation is output in the DAC1 period DT1, and a gradation voltage corresponding to an even gradation is output in the DAC2 period DT2. The control signal is generated as follows.

  When “101” is set in the parameters P2 to P0 of the output order specification register 238, the control timing generation unit 210 performs control so that the output is performed in the reverse order to that when “100” is set in the parameters P2 to P0. Generate a signal.

  By combining the setting values of the drive mode setting register 228 and the output order specification register 238, in this embodiment, a voltage can be output in each pre-buffer period and each DAC period with the following variations.

  30A, FIG. 30B, FIG. 31A, and FIG. 31B, the gradation voltage when “00” is set to the parameters P1 and P0 by the drive mode setting register 228 of FIG. The explanatory view of the output pattern of is shown. That is, in the first drive mode, an intermediate voltage between the gradation voltage corresponding to the even gradation and the gradation voltage corresponding to the odd gradation is output in the pre-buffer period.

  FIG. 30A shows an output pattern of gradation voltages when “000” is set in the parameters P2 to P0 of the output order specification register 238. FIG. 30B shows an output pattern of gradation voltages when “001” is set in the parameters P2 to P0 of the output order designation register 238. FIG. 31A shows an output pattern of gradation voltages when “010” is set in the parameters P2 to P0 of the output order specification register 238. FIG. FIG. 31B shows an output pattern of gradation voltages when “100” is set in the parameters P2 to P0 of the output order designation register 238.

  In FIG. 30A, FIG. 30B, FIG. 31A, and FIG. 31B, “C” represents a gradation voltage corresponding to an odd gradation and a gradation voltage corresponding to an even gradation. "E" indicates that a gradation voltage corresponding to an even gradation is output, and "O" indicates a gradation voltage corresponding to an even gradation. It shows that.

  In FIG. 30A, FIG. 30B, FIG. 31A, and FIG. 31B, the horizontal axis indicates the number of frames, the vertical axis indicates the scanning line, and during the selection period of each scanning line of each frame, The order in which gradation voltages are output is shown. In FIGS. 30A and 30B, the horizontal axis indicates that the output pattern of the first frame is returned after the fourth frame. In FIGS. 31A and 31B, the horizontal axis indicates that the output pattern of the first frame is restored after the second frame.

For example, in FIG. 30A, (C → E → O) _{P in} the selection period of one scan line of one frame, and the pre-period in the selection period that is the positive polarity period (P) in the polarity inversion drive. In the buffer period BT1, the pre-buffer voltage (C), which is an intermediate voltage, the gradation voltage (E) corresponding to the even gradation in the DAC1 period DT1, and the gradation voltage (O) corresponding to the odd gradation in the DAC2 period DT2 Indicates that each is output. Further, for example, in FIG. 30B, (C → O → E) _{N in} the selection period of 3 scan lines of 4 frames, and in the selection period, which is the positive polarity period (N) in polarity inversion driving. In the pre-buffer period BT1, the pre-buffer voltage (C), which is an intermediate voltage, the gradation voltage (O) corresponding to the odd gradation in the DAC1 period DT1, and the gradation voltage (E) corresponding to the even gradation in the DAC2 period DT2. ) Indicates that each is output. 31A and 31B also show output patterns in the same manner.

  Note that the gradation voltage output patterns when the parameters P1 and P0 are set to “01” by the drive mode setting register 228 of FIG. 28 are shown in FIGS. 30A, 30B, 31A, and 31B. In FIG. 31B, the gradation voltage in the pre-buffer period is the same as the gradation voltage in the DAC1 period, and thus illustration is omitted.

Therefore, the output order specification register 238 sets the DAC period (grayscale voltage output period) corresponding to the lower 1 (= k) bit data of the grayscale data to the DAC1 period DT1 and the DAC2 period DT2 (first to second ^k ). It is possible to specify which period of the gradation voltage output period). In the DAC period corresponding to the set value of the output order specifying register 238 in the DAC1 period DT1 and the DAC2 period DT2 (first to second ^k gradation voltage output periods), the gradation voltage corresponding to the odd gradation and Of the gradation voltages corresponding to the even gradations ( ^2k kinds of gradation voltages), the gradation voltage corresponding to the lower 1 (= k) bit data of the gradation data is supplied to the gradation signal line.

  32A, FIG. 32B, FIG. 33A, and FIG. 33B, the gradation voltage when “10” is set to the parameters P1 and P0 by the drive mode setting register 228 of FIG. The explanatory view of the output pattern of is shown. That is, in the second drive mode, the same gradation voltage as that in the immediately following DAC period is output in the pre-buffer period.

  FIG. 32A shows an output pattern of gradation voltages when “000” is set in the parameters P2 to P0 of the output order specifying register 238. FIG. FIG. 32B shows an output pattern of gradation voltages when “001” is set in the parameters P2 to P0 of the output order specification register 238. FIG. 33A shows an output pattern of gradation voltages when “010” is set in the parameters P2 to P0 of the output order specification register 238. FIG. FIG. 33B shows an output pattern of gradation voltages when “100” is set in the parameters P2 to P0 of the output order designation register 238.

  In FIGS. 32A and 32B, the output pattern is viewed in the same manner as in FIGS. 30A and 30B, and detailed description thereof is omitted. In FIGS. 33 (A) and 33 (B), the output pattern is viewed in the same manner as in FIGS. 31 (A) and 31 (B), and detailed description thereof is omitted. However, in FIGS. 32A, 32B, 33A, and 33B, the pre-buffer period BT1 and the DAC1 period DT1, and the pre-buffer period BT2 and the DAC2 period DT2 have the same gray level. When the voltage is output, the gradation voltage corresponding to the even gradation is output in the prebuffer period BT1 and the DAC1 period DT1, and the gradation voltage corresponding to the odd gradation is output in the prebuffer period BT2 and the DAC2 period DT2. This is simply indicated as (E → O).

Therefore, the output order specification register 238 sets the prebuffer period and the DAC period (buffer output period and gradation voltage output period) corresponding to the lower k bits of the gradation data to the prebuffer periods BT1, BT2, DAC1 period DT1, This is a register for designating which one of the DAC2 periods DT2 (first to second ^k buffer output periods and first to second ^k buffer output periods) to be allocated. Then, in the pre-buffer periods BT1, BT2, DAC1 period DT1, DAC2 period DT2 (first to second ^k buffer output periods and first to second ^k buffer output periods), the set value of the output order designation register 238 is set. In the corresponding pre-buffer period and DAC period, the gradation voltage corresponding to the lower 1 (= k) bit data of the gradation data among the 21 ^{(= k)} kinds of gradation voltages is supplied to the gradation signal line. .

  As described above, the output order of the gradation voltages can be changed in various patterns depending on the polarity of the polarity inversion drive and the scanning line. As a result, the frequency at which the image changes increases, and flicker and the like can be reliably prevented.

4). Electronic Device FIG. 34 shows a block diagram of a configuration example of the electronic device in the present embodiment. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device. In FIG. 34, the same parts as those in FIG. 1 or FIG.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies image data captured by the CCD camera to the display controller 38 in the YUV format.

  Mobile phone 900 includes LCD panel 20. The LCD panel 20 is driven by a source driver 30 and a gate driver 32. The LCD panel 20 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels.

  The display controller 38 is connected to the source driver 30 and the gate driver 32, and supplies gradation data in RGB format to the source driver 30.

  The power supply circuit 100 is connected to the source driver 30 and the gate driver 32 and supplies a driving power supply voltage to each driver. Further, the counter electrode voltage Vcom is supplied to the counter electrode of the LCD panel 20.

  The host 940 is connected to the display controller 38. The host 940 controls the display controller 38. The host 940 can supply the gradation data received via the antenna 960 to the display controller 38 after demodulating the modulation / demodulation unit 950. The display controller 38 displays on the LCD panel 20 by the source driver 30 and the gate driver 32 based on the gradation data.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the LCD panel 20 based on operation information from the operation input unit 970.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

1 is a diagram illustrating an outline of a configuration of a liquid crystal device according to an embodiment. FIG. 5 is a diagram illustrating an outline of another configuration of the liquid crystal device according to the present embodiment. The block diagram of the structural example of the gate driver of FIG. FIG. 2 is a block diagram of a configuration example of a source driver in FIG. 1. The figure which shows an example of the layout image when a source driver is integrated on the semiconductor substrate. The figure which shows an example of the timing of the 1st drive mode of the source driver in this embodiment. The figure which shows the other example of the timing of the 1st drive mode of the source driver in this embodiment. The figure which shows the principal part of the structural example per output of the source driver of FIG. FIG. 9 is a diagram illustrating an example of operation timings of the read clock RCLK, the control signals PS, DACON, KK1, and KK2 in FIG. 8 in the first drive mode. FIG. 9 is a circuit diagram of a configuration example of a control logic unit in FIG. 8. FIG. 9 is a circuit diagram of a configuration example of a control logic unit in FIG. 8. FIG. 5 is a diagram illustrating a configuration example of a gradation voltage generation circuit in FIG. 4. The figure which shows typically the gradation voltage of the gradation signal line in a 1st drive mode. The circuit diagram of the structural example of PS logic part. The circuit diagram of the example of composition of a bypass switch circuit. The circuit diagram of the structural example of the sample hold circuit provided in an output circuit. FIG. 17 is a timing diagram of an operation example of the sample hold circuit of FIG. 16. The figure which shows an example of the timing of the 1st drive mode at the time of applying a sample hold circuit. The figure which shows the other example of the timing of the 1st drive mode at the time of applying a sample hold circuit. The figure which shows an example of the timing of the 2nd drive mode of the source driver in this embodiment. The figure which shows the other example of the timing of the 2nd drive mode of the source driver in this embodiment. FIG. 9 is a diagram illustrating an example of operation timings of the read clock RCLK, the control signals PS, DACON, KK1, and KK2 of FIG. 8 in the second drive mode. The figure which shows typically the gradation voltage of the gradation signal line | wire of FIG. 8 in a 2nd drive mode. The figure which shows an example of the timing of the 2nd drive mode at the time of applying a sample hold circuit. The figure which shows the other example of the timing of the 2nd drive mode at the time of applying a sample hold circuit. The figure which shows the structure principal part of the logic part containing a control register part. The figure which shows the outline | summary of a structure of the control register part of FIG. Explanatory drawing about the drive mode which can be set by a drive mode setting register. Explanatory drawing of the parameter of an output order designation | designated register. 30A and 30B are explanatory diagrams of output patterns of gradation voltages. FIG. 31A and FIG. 31B are explanatory diagrams of output patterns of gradation voltages. 32A and 32B are explanatory diagrams of output patterns of gradation voltages. 33A and 33B are explanatory diagrams of output patterns of gradation voltages. 1 is a block diagram of a configuration example of an electronic device according to an embodiment.

Explanation of symbols

10 liquid crystal device, 20 LCD panel, 30 source driver,
32 gate drivers, 38 display controllers, 40 shift registers,
42 level shifter, 44 output buffer, 50 I / O buffer,
52, 52 ₁ display memory, 54, 54 ₁ line latch,
56 gradation voltage generating circuit, 58 DAC, 60 driving unit,
62 address control circuit, 64 row address decoder,
66 column address decoder, 68 line address decoder,
100 power supply circuit, 110 ₁ control logic unit, level shifter 112 ₁ ,
114 ₁ bypass switch circuit, 116 ₁ PS logic part,
DEC ₁ voltage selection circuit, OP ₁ operational amplifier, V0L to V31L gradation signal line

Claims (12)

a driving circuit for driving a source line of an electro-optical device based on gradation data of j (j is an integer of 2 or more) bits;
2 ^(j−k) (0 <k <j, k is an integer) Each gradation signal line of two gradation signal lines has a continuous gradation value selected from 2 ^j kinds of gradation voltages 2 a gradation voltage generating circuit for supplying ^k kinds of gradation voltages in a time-division manner during one selection period;
A voltage selection circuit that selects one gradation signal line from the gradation signal lines based on upper (jk) bit data of the gradation data;
An output buffer for driving the source line based on the gradation voltage of the gradation signal line selected by the voltage selection circuit;
A switching element for bypassing an input and an output of the output buffer,
The ^{q (1 ≦ q ≦ 2 k} , q is an integer) first to 2 ^k buffer output of the gradation voltage output period of the q after the buffer output period of the buffer output period and said q as a set A period and a first to second ^k gradation voltage output period are provided in one selection period,
The r corresponding to the data of the lower k bits of the gradation data among the first to buffer output period of the ^{2 k (1 ≦ r ≦ 2} k, r is an integer) to the buffer output period of the output buffer, after driving the source lines based on the grayscale voltage corresponding to the data of the lower k bits of the 2 ^k different gray-to gray-scale voltage output period of the r, the 2 ^k different gradation A driving circuit for supplying a gradation voltage corresponding to the lower-order k-bit data of the voltage to the source line through the switch element. In claim 1,
A gradation voltage supplied from the voltage selection circuit to the output buffer during the r-th buffer output period, and a gradation voltage supplied from the voltage selection circuit to the switch element during the r-th gradation voltage output period Are the same voltage. In claim 1 or 2,
The buffer output period and the gradation voltage output period corresponding to the lower-order k-bit data of the gradation data are set to any of the first to second ^k buffer output periods and the first to second ^k buffer output periods. Contains an output order specification register that specifies whether to allocate,
Of the first to second ^k buffer output periods and the first to second ^k gradation voltage output periods, the buffer output period and the gradation voltage output period corresponding to the set value of the output order designation register, 2. A driving circuit that supplies a gradation voltage corresponding to lower k bits of gradation data among 2 ^k kinds of gradation voltages to a gradation signal line. In any one of Claims 1 thru | or 3,
Of the first to second ^k buffer output periods and the first to second ^k gradation voltage output periods, a buffer output period and a gradation voltage output period corresponding to lower k bits of the gradation data In the buffer output period and the gradation voltage output period excluding, the drive circuit is characterized in that the output to the source line is set to a high impedance state. In claim 4,
The output buffer is
A sample-and-hold circuit that samples the gradation voltage selected by the voltage selection circuit during a sampling period and outputs the gradation voltage as a hold voltage during the hold period;
The buffer output period and the gradation voltage output period corresponding to the lower-order k-bit data of the gradation data are the first to (2 ^k −1) buffer output periods and the first to (2 ^k −1). The grayscale voltage sampled during the grayscale voltage output period corresponding to the lower-order k-bit data of the grayscale data is temporarily sourced after the grayscale voltage output period. A drive circuit characterized in that an output to a line is set in a high impedance state and is output as the hold voltage over a period up to a 2 ^k gradation voltage output period. In any one of Claims 1 thru | or 5,
The output to the source line is set in a high impedance state between a p-th (1 ≦ p <k, p is an integer) gradation voltage output period and a (p + 1) th buffer output period. Drive circuit. Multiple source lines,
Multiple gate lines,
A plurality of pixels connected to the plurality of source lines and the plurality of gate lines;
A gate driver that scans the plurality of gate lines;
An electro-optical device comprising: the drive circuit according to claim 1 that drives the plurality of source lines.   An electronic apparatus comprising the drive circuit according to claim 1.   An electronic apparatus comprising the electro-optical device according to claim 7. A driving method for driving a source line of an electro-optical device based on gradation data of j (j is an integer of 2 or more) bits,
2 ^(j−k) (0 <k <j, k is an integer) Each gradation signal line of two gradation signal lines has a continuous gradation value selected from 2 ^j kinds of gradation voltages 2 ^k types of gradation voltages are supplied in a time-division manner during one selection period,
One gradation signal line is selected from the gradation signal lines based on upper (jk) bit data of the gradation data;
The ^{q (1 ≦ q ≦ 2 k} , q is an integer) first to 2 ^k buffer output of the gradation voltage output period of the q after the buffer output period of the buffer output period and said q as a set A period and a first to second ^k gradation voltage output period are provided in one selection period,
The r corresponding to the data of the lower k bits of the gradation data among the first to buffer output period of the ^{2 k (1 ≦ r ≦ 2} k, r is an integer) to the buffer output period, the output buffer, wherein the source based on the grayscale voltage corresponding to the data of the lower k bits of the 2 ^k kinds of gradation voltages of the gradation signal lines selected based on the upper (j-k) of bit data of the grayscale data After driving the line, during the r-th gradation voltage output period, one of the 2 ^k kinds of gradation voltages is supplied to the source line by bypassing the input and output of the output buffer A driving method characterized by: In claim 10,
The gradation voltage supplied to the output buffer during the r-th buffer output period and the gradation voltage supplied to the switch element during the r-th gradation voltage output period are the same voltage. Driving method. In claim 10 or 11,
The buffer output period and the gradation voltage output period corresponding to the lower-order k-bit data of the gradation data are set to any of the first to second ^k buffer output periods and the first to second ^k buffer output periods. In the buffer output period and the gradation voltage output period corresponding to the setting value of the output order designation register for designating whether to allocate, the floor corresponding to the lower k bits of the gradation data among the 2 ^k kinds of gradation voltages A driving method comprising supplying a regulated voltage to a gradation signal line.

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