JP5119901B2 - Source driver, electro-optical device, projection display device, and electronic device - Google Patents

Description

  The present invention relates to a source driver, an electro-optical device, a projection display device, an electronic apparatus, and the like.

  2. Description of the Related Art Conventionally, an active matrix type liquid crystal panel using a switching element such as a thin film transistor (hereinafter referred to as TFT) is known as a liquid crystal panel (electro-optical device) used in a mobile phone or a projection display device. ing.

  Until now, when an active matrix liquid crystal panel is used in a portable electronic device such as a mobile phone, it has been considered difficult to reduce power consumption in the active matrix method. However, in recent years, even in an active matrix liquid crystal panel, a sufficiently low power consumption has been realized. On the other hand, the advantage of being suitable for multi-coloring and moving image display by an active matrix liquid crystal panel has been attracting attention.

In order to display an image with high accuracy, generally, a drive signal of the display device is subjected to gamma correction in accordance with the gradation characteristics of the display device. Taking a liquid crystal panel as an example, a gradation voltage corrected so as to realize an optimal transmittance of a pixel is output based on gradation data for performing gradation display by gamma correction. Then, the source line is driven based on this gradation voltage.
JP-A-7-306660

  However, in recent years, the demand for higher image quality of displayed images has further increased, and there has been an increasing demand for multi-gradation for a source driver that drives a source line of an electro-optical device. In this case, it is necessary to supply more types of gradation voltages to the output buffers that drive the source lines of the plurality of source lines of the electro-optical device.

Generally, when a source driver is integrated on a semiconductor substrate, a configuration in which a plurality of output buffers are arranged along the long side direction of the semiconductor substrate is employed. Therefore, the gradation voltage signal line group is also arranged so as to extend in the long side direction of the semiconductor substrate. Therefore, when the number of gradation voltage signal lines is increased, the layout area (circuit scale) in the short side direction of the semiconductor substrate intersecting the long side direction of the semiconductor substrate is increased. For example, if the number of bits of gradation data for each dot is 6, the number of gradation voltage signal lines is 64 (= 2 ⁶ ), but if the number of bits of gradation data is 8, the gradation voltage signal The number of lines becomes 256 (= 2 ⁸ ), and the layout area of the grayscale voltage signal line group increases 4 times (= 2 ^8-6 ) times.

  On the other hand, in Patent Document 1, in order to reduce the number of gradation voltage signal lines, a staircase voltage is generated, and a desired voltage is sampled from a plurality of voltages set in a staircase pattern to thereby obtain a pulse width. A technique for expressing a halftone by generating a modulation signal is disclosed. However, the gradation expression is limited to the pulse width modulation method, and there is a problem that it is difficult to improve the image quality when a larger number of gradations are required.

  In addition, it is difficult to set all the levels of a plurality of voltages set in a staircase shape with high accuracy, and even if the level can be set with high accuracy, the circuit scale becomes complicated. In particular, as the number of gradations increases and the voltage difference between the gradations decreases, it is difficult to generate a stepped voltage in which the level of each voltage is set with high accuracy as disclosed in Patent Document 1. Become.

  Furthermore, the demand for high-definition image display is common to projection display devices. Although the demand for reducing the power consumption is not high for the source driver employed in the projection display device, the demand for reducing the circuit scale of the source driver is high for the purpose of downsizing the device.

  According to some embodiments of the present invention, it is possible to provide a source driver, an electro-optical device, a projection display device, and an electronic apparatus that can display a high-definition image without causing an increase in circuit scale.

In order to solve the above problems, the present invention
A source driver for driving a source line of an electro-optical device based on (j + k) (j, k are natural numbers) bit gradation data,
2 ^j gradation signal lines;
A gradation voltage selection circuit for outputting two gray scale voltages of 2 ^j types of gradation voltages supplied by 2 ^j present grayscale signal lines,
Of the voltages between the two voltages including the low potential side gradation voltage and the high potential side gradation voltage from the gradation voltage selection circuit, the gradation voltage corresponding to the lower k bits of the gradation data is used as the source line. The present invention relates to a source driver including a source line driver circuit for outputting.

  According to the present invention, since the number of gradation signal lines can be greatly reduced, it is possible to provide a source driver capable of displaying a high-definition image without increasing the circuit scale.

In the source driver according to the present invention,
The source line driving circuit is
A voltage follower circuit including a differential amplifier having a differential transistor pair and a drive unit that drives a source line based on an output of the differential amplifier;
By changing the current drive capability of the differential transistor pair, it corresponds to the lower k-bit data of the gradation data among the voltages between the two voltages including the low potential side gradation voltage and the high potential side gradation voltage. The gradation voltage thus produced can be output to the source line.

In the source driver according to the present invention,
Of the first and second differential transistor groups constituting the differential transistor pair, the second differential transistor group is k transistors,
A signal corresponding to each bit data of the lower k bits of the gradation data may be supplied to the gate of each of the k transistors.

In the source driver according to the present invention,
A lower bit decoder for decoding lower k bits of the gradation data;
Of the first and second differential transistor groups constituting the differential transistor pair, the current drive capability of each transistor of the second differential transistor group is the same,
A signal corresponding to the decoding result of the lower bit decoder may be supplied to the gate of each transistor.

  According to any one of the above inventions, by controlling the current drive capability of the differential transistor pair of the voltage follower circuit that constitutes the source line drive circuit, the low potential side grayscale voltage and the high potential grayscale voltage from the grayscale voltage selection circuit are controlled. Since the voltage between the two voltages including the potential-side gradation voltage can be output according to the lower bit data of the gradation data, it has a simpler structure and high definition without increasing the circuit scale. A source driver capable of displaying an image can be provided.

In the source driver according to the present invention,
Including a first gradation selection exception handling register;
When the gradation voltage selection circuit outputs the gradation voltage sequentially assigned to VSEL1 to VSEL (2 ^k ) to the high potential side based on the low-order k-bit data with the low potential side gradation voltage as VSEL1. In addition,
The high potential side gradation voltage may be assigned to VSEL (2 ^k ) in accordance with a set value of the first gradation selection exception processing register.

In the source driver according to the present invention,
A second gradation selection exception handling register;
When the high potential side gradation voltage is assigned to VSEL (2 ^k ) by the first gradation selection exception processing register,
Only when the data of each bit of the gradation data is all 0 or when the data of each bit of the gradation data is all 1, according to the set value of the second gradation selection exception processing register, As the high potential side gradation voltage, the highest potential gradation voltage among the ^2j kinds of gradation voltages may be assigned.

In the source driver according to the present invention,
Including a first gradation selection exception handling register;
When the gradation voltage selection circuit outputs the gradation voltage sequentially assigned to VSEL1 to VSEL (2 ^k ) to the low potential side based on the low-order k-bit data with the high-potential-side gradation voltage as VSEL1. In addition,
The low potential side gradation voltage may be assigned to VSEL (2 ^k ) in accordance with a set value of the first gradation selection exception processing register.

In the source driver according to the present invention,
A second gradation selection exception handling register;
When the low potential side gradation voltage is assigned to VSEL (2 ^k ) by the first gradation selection exception processing register,
Only when the data of each bit of the gradation data is all 0 or when the data of each bit of the gradation data is all 1, according to the set value of the second gradation selection exception processing register, As the low potential side gradation voltage, the lowest potential gradation voltage among the ^2j kinds of gradation voltages may be assigned.

  According to any one of the above inventions, as an exception process, the gradation voltage assignment method associated with the reduction of the gradation signal lines can be changed, so that the optimum gradation according to the gradation characteristics of the electro-optical device can be changed. The expression can be realized with a simple configuration.

The present invention also provides
A source driver for driving a source line of an electro-optical device based on (j + k) (j, k are natural numbers) bit gradation data,
A gradation voltage selection circuit which outputs the two adjacent gradation voltage of 2 ^j types of gray scale voltages,
A source that outputs, to a source line, a gradation voltage corresponding to lower k bits of the gradation data among 2 ^k kinds of gradation voltages between the two adjacent gradation voltages from the gradation voltage selection circuit. The present invention relates to a source driver including a line driver circuit.

The present invention also provides
Multiple gate lines,
Multiple source lines,
Each pixel is a plurality of pixels specified by each gate line and each source line;
The present invention relates to an electro-optical device including the source driver described above for driving the plurality of source lines.

In the electro-optical device according to the invention,
A gate driver for scanning the plurality of gate lines may be included.

The present invention also provides
The present invention relates to an electro-optical device including the source driver described above.

  According to any one of the above-described inventions, it is possible to provide an electro-optical device to which a source driver capable of displaying a high-definition image without causing an increase in circuit scale is applied.

The present invention also provides
Any of the above electro-optical devices;
A light source for entering light into the electro-optical device;
The present invention relates to a projection display apparatus including projection means for projecting light emitted from the electro-optical device.

The present invention also provides
The present invention relates to a projection display apparatus including any one of the source drivers described above.

  According to any one of the above inventions, it is possible to provide a projection display device to which a source driver capable of displaying a high-definition image without causing an increase in circuit scale is applied.

The present invention also provides
The present invention relates to an electronic apparatus including any of the electro-optical devices described above.

The present invention also provides
Any of the above electro-optical devices;
The present invention relates to an electronic apparatus including means for supplying gradation data to the electro-optical device.

The present invention also provides
The present invention relates to an electronic device including any of the source drivers described above.

  According to any one of the above inventions, it is possible to provide an electronic apparatus including a source driver capable of displaying a high-definition image without causing an increase in circuit scale.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Liquid Crystal Device FIG. 1 shows an outline of the configuration of an active matrix liquid crystal device according to this embodiment.

  The liquid crystal device 10 includes a liquid crystal display (LCD) panel (display panel in a broad sense, electro-optical device in a broader sense) 20. The LCD panel 20 is formed on a glass substrate, for example. On this glass substrate, a plurality of gate lines (scanning lines) GL1 to GLM (M is an integer of 2 or more) arranged in the Y direction and extending in the X direction, and a source line arranged in the X direction and extending in the Y direction, respectively. (Data lines) SL1 to SLN (N is an integer of 2 or more) are arranged. The pixel region corresponds to the intersection position of the gate line GLm (1 ≦ m ≦ M, m is an integer, the same applies hereinafter) and the source line SLn (1 ≦ n ≦ N, n is an integer, the same applies hereinafter). (Pixel) is provided, and a thin film transistor (hereinafter abbreviated as TFT) 22 mn is disposed in the pixel region. The electro-optical device can include a device using a light emitting element such as an organic EL (Electro Luminescence) element or an inorganic EL element.

  The gate of the TFT 22mn is connected to the gate line GLm. The source of the TFT 22mn is connected to the source line SLn. The drain of the TFT 22mn is connected to the pixel electrode 26mn. Liquid crystal is sealed between the pixel electrode 26mn and the counter electrode 28mn facing the pixel electrode 26mn, thereby forming a liquid crystal capacitor (liquid crystal element in a broad sense) 24mn that is an element capacitor. The transmittance of the pixel changes according to the applied voltage between the pixel electrode 26mn and the counter electrode 28mn. The counter electrode voltage Vcom is supplied to the counter electrode 28mn. The element capacitance can include a liquid crystal capacitance formed in a liquid crystal element and a capacitance formed in an EL element such as an inorganic EL element.

  Such an LCD panel 20 includes, for example, a first substrate on which pixel electrodes and TFTs are formed and a second substrate on which counter electrodes are formed, and a liquid crystal as an electro-optical material is interposed between the two substrates. It is formed by enclosing.

  The liquid crystal device 10 includes a source driver (display driver in a broad sense, drive circuit in a broader sense) 30. The source driver 30 drives the source lines SL <b> 1 to SLN of the LCD panel 20 based on (j + k) (j and k are natural numbers) bit gradation data.

  The liquid crystal device 10 can include a gate driver (scan driver in a broad sense) 32. The gate driver 32 scans the gate lines GL1 to GLM of the LCD panel 20 within one vertical scanning period.

  The liquid crystal device 10 can include a power supply circuit 100. The power supply circuit 100 generates voltages necessary for driving the source lines and supplies them to the source driver 30. The power supply circuit 100 generates, for example, power supply voltages VDDH and VSSH necessary for driving a source line of the source driver 30 and a voltage of a logic unit of the source driver 30.

  The power supply circuit 100 generates a voltage necessary for scanning the gate line and supplies it to the gate driver 32.

  Further, the power supply circuit 100 generates a counter electrode voltage Vcom. In accordance with the timing of the polarity inversion signal POL generated by the source driver 30, the power supply circuit 100 generates a common electrode voltage Vcom that periodically repeats the high potential side voltage VCOMH and the low potential side voltage VCOML on the LCD panel 20. Output to electrode. Alternatively, when the color unevenness of the LCD panel 20 occurs due to the change of the counter electrode voltage Vcom, the power supply circuit 100 may output the counter electrode voltage Vcom, which is a fixed constant voltage, to the counter electrode of the LCD panel 20.

  The liquid crystal device 10 can include a display controller 38. The display controller 38 controls the source driver 30, the gate driver 32, and the power supply circuit 100 according to contents set by a host such as a central processing unit (hereinafter abbreviated as CPU) (not shown). For example, the display controller 38 sets an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the source driver 30 and the gate driver 32. Here, the display controller 38 or the host can supply the gradation data to the source driver 30.

  In FIG. 1, the liquid crystal device 10 includes the power supply circuit 100 or the display controller 38, but at least one of these may be provided outside the liquid crystal device 10. Alternatively, the liquid crystal device 10 may be configured to include a host.

  The source driver 30 may incorporate at least one of the gate driver 32 and the power supply circuit 100.

  Furthermore, some or all of the source driver 30, the gate driver 32, the display controller 38, and the power supply circuit 100 may be formed on the LCD panel 20. For example, in FIG. 2, a source driver 30 and a gate driver 32 are formed on the LCD panel 20. As described above, the LCD panel 20 includes a plurality of source lines, a plurality of gate lines, a plurality of switching elements connected to the gate lines of the plurality of gate lines, and a plurality of source lines. And a display driver for driving the source line. A plurality of pixels are formed in the pixel formation region 80 of the LCD panel 20.

1.1 Gate Driver FIG. 3 shows a configuration example of the gate driver 32 shown in FIG.

  The gate driver 32 includes a shift register 40, a level shifter 42, and an output buffer 44.

  The shift register 40 includes a plurality of flip-flops provided corresponding to the gate lines and sequentially connected. When the shift register 40 holds the start pulse signal STV in the flip-flop in synchronization with the clock signal CPV, the shift register 40 sequentially shifts the start pulse signal STV to the adjacent flip-flop in synchronization with the clock signal CPV. The clock signal CPV input here is a horizontal synchronizing signal, and the start pulse signal STV is a vertical synchronizing signal.

  The level shifter 42 shifts the voltage level from the shift register 40 to a voltage level corresponding to the liquid crystal element of the LCD panel 20 and the transistor capability of the TFT. As this voltage level, for example, a high voltage level of 20 V to 50 V is required.

  The output buffer 44 buffers the scanning voltage shifted by the level shifter 42 and outputs it to the gate line to drive the gate line.

1.2 Source Driver FIG. 4 shows a block diagram of a configuration example of the source driver 30 of FIG. 1 or FIG.

  The source driver 30 includes an I / O buffer 50, a display memory 52, a line latch 54, a gradation voltage generation circuit 56, a DAC (Digital / Analog Converter) 58 (a gradation voltage selection circuit in a broad sense), and a source line driving circuit 60. including.

  For example, the gradation data D is input to the source driver 30 from the display controller 38. The gradation data D is input in synchronization with the dot clock signal DCLK and buffered in the I / O buffer 50. The dot clock signal DCLK is supplied from the display controller 38.

  The I / O buffer 50 is accessed by the display controller 38 or a host (not shown). The gradation data buffered in the I / O buffer 50 is written in the display memory 52. The gradation data read from the display memory 52 is output to the display controller 38 and the like after being buffered by the I / O buffer 50.

  The display memory (gradation data memory) 52 includes a plurality of memory cells provided corresponding to the output lines in which the memory cells are connected to the source lines. Each memory cell is specified by a row address and a column address. Each memory cell for one scan line is specified by a line address.

  The address control circuit 62 generates a row address, a column address, and a line address for specifying a memory cell in the display memory 52. The address control circuit 62 generates a row address and a column address when writing gradation data into the display memory 52. That is, the gradation data buffered in the I / O buffer 50 is written into the memory cell of the display memory 52 specified by the row address and the column address.

  The row address decoder 64 decodes the row address and selects a memory cell of the display memory 52 corresponding to the row address. The column address decoder 66 decodes the column address and selects a memory cell of the display memory 52 corresponding to the column address.

  When the gradation data is read from the display memory 52 and output to the line latch 54, the address control circuit 62 generates a line address. That is, the line address decoder 68 decodes the line address and selects a memory cell of the display memory 52 corresponding to the line address. Then, gradation data for one horizontal scan read from the memory cell specified by the line address is output to the line latch 54.

  The address control circuit 62 generates a row address and a column address when reading the gradation data from the display memory 52 and outputting it to the I / O buffer 50. That is, the gradation data held in the memory cell of the display memory 52 specified by the row address and the column address is read to the I / O buffer 50. The gradation data read to the I / O buffer 50 is extracted by the display controller 38 or a host (not shown).

  Therefore, in FIG. 4, the row address decoder 64, the column address decoder 66, and the address control circuit 62 function as a write control circuit that performs writing control of gradation data to the display memory 52. On the other hand, in FIG. 4, the line address decoder 68, the column address decoder 66, and the address control circuit 62 function as a readout control circuit that performs readout control of gradation data from the display memory 52.

  The line latch 54 latches the grayscale data for one horizontal scan read from the display memory 52 at the change timing of the horizontal synchronization signal HSYNC. The line latch 54 includes a plurality of registers in which each register holds gradation data for one dot. The gradation data for one dot read from the display memory 52 is taken into each of the plurality of registers of the line latch 54.

A gradation voltage generation circuit (reference voltage generation circuit in a broad sense) 56 generates a plurality of gradation voltages in which each gradation voltage (reference voltage) corresponds to each gradation data. More specifically, the gradation voltage generation circuit 56 generates a plurality of gradation voltages corresponding to each gradation data, based on the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH. . More specifically, 2 ^j types of gradation voltages are generated based on upper j bits of the (j + k) bits of gradation data. The source driver 30 has 2 ^j types of gradation signal lines, and each gradation signal line is supplied with 2 ^j types of gradation voltages. Such a gradation voltage generation circuit 56 includes 2 ^j kinds of gradation voltages at the same time among the voltages of a plurality of divided nodes of the resistance circuit to which the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH are supplied at both ends. Is output.

  The DAC 58 outputs the gradation voltage corresponding to the gradation data output from the line latch 54 (more specifically, the upper j bits of the gradation data) for each output line that is the output of the source line driving circuit 60. Generate. More specifically, the DAC 58 outputs gradation data (one output line of the source line driver circuit 60 output from the line latch 54 from the plurality of gradation voltages generated by the gradation voltage generation circuit 56 ( More specifically, the gradation voltage corresponding to the upper j bits of gradation data) is selected, and the selected gradation voltage is output.

The DAC 58 includes voltage selection circuits DEC _{1 to} DEC _N provided for each output line. Each voltage selection circuit outputs one gradation voltage corresponding to the gradation data from among the plurality of gradation voltages from the gradation voltage generation circuit 56.

The source line driving circuit 60 drives a plurality of output lines whose output lines are connected to the source lines of the LCD panel 20. More specifically, the source line driving circuit 60 drives each output line based on the gradation voltage output for each output line by the voltage selection circuit of the DAC 58. The source line drive circuit 60 includes output circuits OUT _{1 to} OUT _N provided for each output line. Each output circuit drives the source line based on the gradation voltage from each voltage selection circuit. Each output circuit is a voltage follower circuit, and this voltage follower circuit can be constituted by an operational amplifier or the like connected to a voltage follower.

  FIG. 5 is a diagram for explaining the operation of the source driver in this embodiment.

In the present embodiment, each voltage selection circuit of the DAC 58 uses the high-potential-side power supply voltage VDDH and the low-potential-side power supply voltage VSSH among the 2 ^{(j + k)} types of gradation voltages that the source driver 30 can supply to each source line. The two voltages SELA and SELB between the two power supply voltages including are selected based on the upper j bits of the gradation data. Thereafter, each output circuit of the source line driver circuit 60 outputs a voltage between the two voltages including the two voltages SELA and SELB selected by each voltage selection circuit based on the lower-order k-bit data of the gradation data. .

  FIG. 6 shows a configuration example of a main part of the source driver in the present embodiment.

  FIG. 6 shows the line latch 54, the gradation voltage generation circuit 56, the DAC 58, and the source line drive circuit 60 in the source driver 30 of FIG. 4.

  The line latch 54 includes data latches DLAT1 to DLATN provided for each output destination. In each data latch of the data latches DLAT1 to DLATN, (j + k) -bit gradation data for one dot is latched.

2 ^j This gradation signal lines is ^{2 j} types of gray scale voltages to the voltage selection circuit _DEC 1 _{~DEC N} is provided to be supplied. Each voltage selection circuit outputs a low-potential-side voltage SELA and a high-potential-side voltage SELB in which one section corresponding to the upper j-bit data of the gradation data is specified.

The source driver 30 includes output control blocks OCB _{1 to} OCB _N provided for each output line. The output control blocks OCB _{1 to} OCB _N have the same configuration. Each output control block of the output control block OCB ₁ ~OCB _N outputs a control signal of the voltage follower circuit constituting the output circuits. More specifically, each output control block outputs a control signal for controlling each output circuit based on one of the voltages SELA and SELB from each voltage selection circuit. In FIG. 6, each output control block outputs a control signal corresponding to the lower k bits of grayscale data. The voltage level of this control signal is the voltage SELA or the voltage SELB. The output circuit outputs any voltage between the two voltages including the voltages SELA and SELB based on the control signal from the output control block.

  FIG. 7 shows a block diagram of a configuration example of the voltage selection circuit of FIG.

In FIG. 7, it is assumed that j is 6 and k is 4. 7 shows a configuration example of the voltage selection circuit DEC ₁ of the voltage selection circuit _DEC 1 _{~DEC N,} also other voltage select circuit _DEC 2 _{~DEC N} have the same configuration as that of the voltage selection circuit DEC ₁ Yes.

The voltage selection circuit DEC ₁ has a plurality of voltage selection blocks. Each voltage selection block in FIG. 7 has the same configuration. Voltages VDD, VNL, VSSH, VPH, VDDH, data D5 to D1, and inverted data XD5 to XD1, XDA, and XDB are input to the plurality of voltage selection blocks. The inversion data XD5 to XD1 are data obtained by inverting the 5-bit data D5 to D1 excluding the least significant bit among the lower 6 bits of the gradation data. The inversion data XDA becomes H level when the least significant bit data D0 of the gradation data is “1”. The inversion data XDB becomes H level when the least significant bit data D0 of the gradation data is “0”.

  For example, inversion data XD5 to XD1 are input to the voltage selection block that selects two voltages from the gradation voltages V1 to V3, and the voltage selection block that selects two voltages from the gradation voltages V3 to V5. Inverted data XD5 to XD2, data D1 are inputted,..., And data D5 to D1 are inputted to the last voltage selection block to which gradation voltages V63 to V64 are inputted.

Of the plurality of voltage selection blocks, gradation voltages V1 to V3, V3 to V5, V5 to V7,... Among ^{26 (= j)} kinds of gradation voltages are input to each voltage selection block. Has been. Each voltage selection block outputs voltages SELA and SELB from three kinds of gradation voltages.

  FIG. 8 shows an outline of the configuration of the voltage selection block of FIG.

  The voltage selection block 200 includes a decoder 210, a level shifter 220, and a selector 230. The decoder 210 generates a switch control signal based on the inverted data xd5 to xd1, xda, xdb. This switch control signal is converted into a voltage level between the voltage VDDH and the voltage VSSH by the level shifter 220. The selector 230 outputs the voltages SELB and SELA in the descending order of the voltage from the voltages GRADA to GRADC based on the switch control signal converted in level by the level shifter 220.

  FIG. 9 shows a circuit diagram of a configuration example of the voltage selection block of FIG.

  The decoder 210 has two sets of decoder circuits in which six p-type (first conductivity type) metal oxide semiconductor (hereinafter, MOS) transistors are connected in series. A voltage VDD is supplied to one end of each decoder circuit. An n-type (second conductivity type) MOS transistor is connected to the other end of each decoder circuit. Xd5 to xd1, xda are supplied to the gate of the p-type MOS transistor of one decoder circuit, and the voltage VNL is supplied to the gate of the n-type MOS transistor. Xd5 to xd1, xdb are supplied to the gate of the p-type MOS transistor of the other decoder circuit, and the voltage VNL is supplied to the gate of the n-type MOS transistor.

  The voltage VNL is higher than the threshold voltage of the n-type MOS transistor. By generating the drain current of the n-type MOS transistor by this voltage VNL, when all of xd5 to xd1 and xda are at the L level, or when all of xd5 to xd1 and xdb are at the L level, the p-type connected in series A constant current is generated between the source and drain of each of the MOS transistors, and an H level signal can be output to the level shifter 220.

  The level shifter 220 is a two-element level shifter. Further, the level shifter 220 has a p-type MOS transistor whose gate is supplied with a voltage VPH. The voltage VPH is a voltage having a low potential by at least the threshold voltage of the p-type MOS transistor with respect to the voltage VDD, and is a voltage set so that a drain current which is a constant current is generated in the p-type MOS transistor. is there. Thus, the output of the level shifter 220 is set to the H level when the n-type MOS transistor constituting the level shifter 220 is turned on, and the output of the level shifter 220 is set to the L level when the n-type MOS transistor is turned off. it can.

  Based on the output of the level shifter 220, the selector 230 outputs one of the voltages GRADA and GRAD as the voltage SELB, and outputs one of the voltages GRADB and GRADC as the voltage SELA.

  FIG. 10 shows a timing chart of an operation example of the voltage selection circuit of FIG.

  In FIG. 10, SELB and SELA are sequentially changed to the high potential side by the inverted data xd5 to xd1, xda, and xdb. In addition, even if the inverted data xd5 to xd1, xda, and xdb change, there is a potential difference between the voltages SELA and SELB. In FIG. 10, each time the inverted data xd5 to xd1, xda, and xdb change, the voltage selection block that outputs the voltages SELA and SELB is different.

  The output circuit outputs a voltage between the two voltages including the voltages SELA and SELB.

FIG. 11 shows a block diagram of a configuration example of the output control block OCB ₁ of FIG.

The output control block OCB ₁ can output control signals p1 to p4 to the output circuit OUT ₁ . The output control block OCB ₁ outputs _one of the voltages SELA and SELB from the voltage selection circuit DEC ₁ as control signals p1 to p4 based on the lower 4 (= k) bit data D3 to D0 of the gradation data. .

Further, the output control block OCB ₁ can include an exception processing circuit ECB ₁ . The exception processing circuit ECB ₁ can output to the output circuit OUT ₁ a control signal p5 for improving gradation characteristics according to the characteristics of the LCD panel 20. For example, the enhancement or the like of the black display enhancement and white display of the LCD panel 20 for adjusting the contrast for the purpose, using a control signal p5 from the exception processing circuit ECB _1. Therefore, the source driver 30 has a control register unit in a control circuit (not shown), and the exception processing circuit ECB ₁ outputs a control signal p5 based on the set value of the control register unit.

  FIG. 12 shows an outline of the configuration of the control register unit of the source driver 30 in the present embodiment.

  The source driver 30 has the control register unit 250 shown in FIG. 12 in the configuration of FIG. The control register unit 250 includes a plurality of control registers, and each control register is configured to be accessible by the display controller 38 or a host (not shown). The display controller 38 or the host sets control data (setting value) in each control register, so that each unit of the source driver 30 performs control corresponding to the control data in the control register.

  The control register unit 250 includes first and second gradation selection exception processing registers 252 and 254. The first gradation selection exception processing register 252 is a control register for designating whether or not to perform the first exception processing. Here, the first exceptional process is a process for emphasizing the gradation expression corresponding to the gradation voltage on the high potential side or the low potential side. The second gradation selection exception processing register 254 is a control register for designating whether or not to perform the second exception processing as the exception processing at the time of the first exception processing. Here, the second exception process is a process for emphasizing the gradation expression corresponding to the gradation voltage when each bit of the gradation data is all “0” or “1”.

Control signal REG1 corresponding to the setting value of the first gradation selecting exception processing registers 252 is input to the exception processing circuit of the output control block _OCB 1 _{~OCB N.} Control signal REG2 which corresponds to the set value of the second gradation selecting exception handling register 254, in the same manner as the control signal REG1, it is input to the exception processing circuit of the output control block _OCB 1 _{~OCB N.}

  FIG. 13A, FIG. 13B, FIG. 14A, and FIG. 14B are explanatory diagrams of the first exception processing.

  In FIG. 13A, FIG. 13B, FIG. 14A, and FIG. 14B, in order to simplify the description, four types of continuous gradations are present between both voltages including the voltages SELA and SELB. An example is shown in which gradation voltages corresponding to values are divided. When the LCD panel 20 is driven to invert the polarity, FIGS. 13A and 13B are explanatory diagrams when the counter electrode voltage has a positive polarity lower than the voltage of the pixel electrode. FIGS. 14A and 14B are explanatory diagrams when the counter electrode voltage has a negative polarity higher than the voltage of the pixel electrode.

  FIG. 13A shows an example in which the first exception selection register 252 specifies that the first exception processing is not performed. On the other hand, FIG. 13B shows an example in which the first exception selection register 252 designates the first exception process.

In the present embodiment, in the case of positive polarity or fixing the counter electrode voltage by inverting the polarity of the counter electrode, the DAC 58 uses the low potential side voltage (low potential side gradation voltage) as the VSEL 1 to adjust the gradation. When the gradation voltages assigned to VSEL1 to VSEL (2 ^k ) are sequentially output to the high potential side based on the lower k bits of the data, according to the set value of the first gradation selection exception processing register 252 The voltage on the high potential side (high potential side gradation voltage) is assigned to VSEL (2 ^k ). That is, as shown in FIG. 13A, when the first exception processing is not performed, four types of gradation voltages are assigned between the two voltages including the voltages SELA and SELB. The voltage SELB on the highest potential side is not assigned as the gradation voltage between the voltages selected corresponding to the bits. On the other hand, as shown in FIG. 13B, when the first exception processing is performed, although four types of gradation voltages are assigned between the voltages SELA and SELB, the gradation data The voltage SELA on the lowest potential side is not assigned as the gradation voltage between the voltages selected corresponding to the higher-order bits. Such first exception processing can be realized by fixing the control signal p5 of FIG. 11 to the voltage SELB. When the first exception process is not performed, the control signal p5 in FIG. 11 is fixed to, for example, the voltage SELA.

In the present embodiment, in the case of negative polarity by driving the counter electrode with the polarity reversed, the DAC 58 uses the high-potential side voltage (high-potential side gradation voltage) as VSEL1 and is based on the lower k bits of the gradation data. When the gradation voltages sequentially assigned to VSEL1 to VSEL (2 ^k ) are output to the low potential side, the voltage on the low potential side (low potential) is set according to the set value of the first gradation selection exception processing register 252. Side gradation voltage) is assigned to VSEL (2 ^k ). That is, as shown in FIG. 14A, when the first exception processing is not performed, four types of gradation voltages are assigned between the two voltages including the voltages SELA and SELB, but the upper level of the gradation data is high. The voltage SELA on the lowest potential side is not assigned as the gradation voltage between the voltages selected corresponding to the bits. On the other hand, as shown in FIG. 14B, when the first exception processing is performed, although four kinds of gradation voltages are assigned between the two voltages including the voltages SELA and SELB, the gradation data The voltage SELA on the lowest potential side is not assigned as the gradation voltage between the voltages selected corresponding to the higher-order bits. Such first exception processing can be realized by fixing the control signal p5 of FIG. 11 to the voltage SELA. When the first exception process is not performed, the control signal p5 in FIG. 11 is fixed to, for example, the voltage SELB.

  By performing the first exception processing as described above, it is possible to finely set the gradation expression for black display (or white display).

FIGS. 15A to 15D and FIGS. 16A to 16B are explanatory diagrams of the second exception processing. In FIGS. 15A to 15D and FIGS. 16A to 16B, both the high-potential-side power supply voltage VDDH and the low-potential-side power supply voltage VSSH are included for simplification of description. Although it is assumed that four kinds of gradation voltages are output between the voltages, ^2j kinds of gradation voltages can be outputted between the two voltages in this embodiment. Also, in FIGS. 15A to 15D and FIGS. 16A to 16B, as the second exception process, only when all the bits of the gradation data are “0” or all the bits Only when “1” is “1”, the assignment of the gradation voltage output between the two voltages including the high-potential-side power supply voltage VDDH and the low-potential-side power supply voltage VSSH will be described. Even when all the bits of the gradation data are “0” or only when all the bits are “1” between the voltages selected corresponding to the bits, the assignment of the gradation voltages may be changed. Good.

  FIG. 15A and FIG. 15C show a case where the first exception processing is performed while the second exception processing is not performed. FIG. 15B and FIG. 15D show cases where the first exception processing is performed and the second exception processing is performed. 15C and 15D are other examples of FIGS. 15A and 15B.

First, in FIG. 15A, for example, the high potential side power supply voltage VDDH is assigned to the gradation voltage by the first exception process. For this reason, the low potential side power supply voltage VSSH is not output as the gradation voltage. On the other hand, in FIG. 15B, by performing the second exception process in the first exception process, for example, the low-potential-side power supply voltage VSSH is assigned to the gradation voltage, and the high-potential-side power supply voltage VDDH Is output as a gradation voltage. In other words, when the high potential side gradation voltage is assigned to VSEL (2 ^k ) by the first gradation selection exception processing register 252, or only when all the bits of the gradation data are all 0 or Only when the data of each bit of the tone data is all 1, the highest potential of the ^2j types of tone voltages is set as the high potential side tone voltage according to the setting value of the second tone selection exception processing register 254 Grayscale voltages are assigned.

Similarly, in FIG. 15C, for example, the low-potential-side power supply voltage VSSH is assigned to the gradation voltage by the first exception process. For this reason, the high potential side power supply voltage VDDH is not output as the gradation voltage. On the other hand, in FIG. 15D, by performing the second exception process in the first exception process, for example, the high potential side power supply voltage VDDH is assigned to the gradation voltage, and the low potential side power supply voltage VSSH is assigned. Is output as a gradation voltage. That is, when the low potential side gradation voltage is assigned to VSEL (2 ^k ) by the first gradation selection exception processing register 252, or only when all the bits of the gradation data are 0 or Only when the data of each bit of the tone data is all 1, the lowest potential of the ^2j types of tone voltages is set as the low potential side tone voltage according to the setting value of the second tone selection exception processing register 254 Grayscale voltages are assigned.

  In FIG. 15B and FIG. 15D, although there is a possibility that the continuity of gradation expression in the middle may be impaired, the gradation voltage can be output in the range of the power supply voltages VDDH to VSSH. By doing so, in FIG. 15B, the display quality of the gradation display of pure white or pure black can be improved. In FIG. 15D, the gradation expression of the black or white portion can be set finely.

  FIG. 16A and FIG. 16C show a case where the first exception processing is performed while the second exception processing is not performed. FIG. 16B and FIG. 16D show a case where the first exception processing is performed and the second exception processing is performed. FIGS. 16C and 16D are other examples of FIGS. 16A and 16B.

  First, in FIG. 16A, for example, the low-potential-side power supply voltage VSSH is assigned to the gradation voltage by the first exception process. For this reason, the high potential side power supply voltage VDDH is not output as the gradation voltage. On the other hand, in FIG. 16B, by performing the second exception process in the first exception process, for example, the high potential side power supply voltage VDDH is assigned to the gradation voltage, and the low potential side power supply voltage VSSH is assigned. Is output as a gradation voltage.

  Similarly, in FIG. 16C, for example, the high potential side power supply voltage VDDH is assigned to the gradation voltage by the first exception process. For this reason, the low potential side power supply voltage VSSH is not output as the gradation voltage. On the other hand, in FIG. 16D, by performing the second exception process in the first exception process, for example, the low-potential-side power supply voltage VSSH is assigned to the gradation voltage, and the high-potential-side power supply voltage VDDH Is output as a gradation voltage.

  In FIG. 16B and FIG. 16D, the gradation voltage can be output in the range of the power supply voltages VDDH to VSSH although there is a possibility that the continuity of gradation expression in the middle may be impaired. By doing so, in FIG. 16B, the display quality of the gradation display of pure white or pure black can be improved. In FIG. 16D, it is possible to finely set the gradation expression of the black or white portion.

FIG. 17 shows a circuit diagram of a configuration example of the output circuit OUT ₁ of FIG.

Although FIG. 17 shows a configuration example of the output circuit OUT ₁ , the other output circuits OUT _{2 to} OUT _N have the same configuration.

The output circuit OUT ₁ is a voltage follower circuit VTG ₁ including a differential amplifier DIF ₁ and a drive unit DRV ₁ . The differential amplifier DIF ₁ has a differential transistor pair. The drive unit DRV ₁ drives the source line based on the output of the differential amplifier DIF ₁ . Then, by changing the current driving capability of the differential transistor pair of the differential amplifier DIF ₁ , the low-order k of the grayscale data among the voltages between the two voltages including the low potential side grayscale voltage and the high potential side grayscale voltage is changed. The gradation voltage corresponding to the bit data can be output to the source line.

In FIG. 17, the second differential transistor group among the first and second differential transistor groups constituting the differential transistor pair of the differential amplifier DIF ₁ has k transistors. Then, signals (control signals p1 to p4 in FIG. 17) corresponding to the data of the lower k bits of the gradation data are supplied to the gates of the k transistors.

  Further, in the case of performing the above-described exception processing, an exception processing transistor is provided in parallel with the above-mentioned k transistors so that the control signal p5 is supplied to the gate. In this case, the current drive capability when the first differential transistor group is all in the conductive state is equal to the current drive capability when the second differential transistor group and the exception processing transistor are all in the conductive state. . By doing so, as described above, the first and second exception processing can be realized with a simple configuration.

Such an output circuit OUT ₁ is (eg, when all the control signals p1~p5 the voltage SELB) when the current driving capability of the first and second transistor groups are equal, the output circuit OUT ₁ is the same voltage as the input voltage Can be output. Further, the output circuit OUT ₁ can change the current drive capability of the first and second transistor groups by changing the conduction state of the transistors constituting the second transistor group. As a result, the output circuit OUT ₁ can output a voltage different from the voltage SELB, for example. By setting the voltage level of the control signals p1 to p5 to a voltage level between the voltages SELA and SELB, the output circuit OUT ₁ can output an output voltage having a voltage level between the voltages SELA and SELB.

The output circuit OUT ₁ includes a lower-order bit decoder that decodes lower-order k-bit data of the gradation data, and the second differential transistor group of the first and second differential transistor groups constituting the differential transistor pair. The current drive capability of each transistor in the transistor group may be the same, and a signal corresponding to the decoding result of the lower bit decoder may be supplied to the gate of each transistor. By doing so, the number of transistors constituting the differential transistor group can be reduced.

2. Electronic Device Next, an electronic device to which the liquid crystal device 10 (source driver 30) in the present embodiment is applied will be described.

2.1 Projection Display Device As an electronic apparatus configured using the liquid crystal device 10 described above, there is a projection display device.

  FIG. 18 shows a block diagram of a configuration example of a projection display device to which the liquid crystal device 10 according to the present embodiment is applied.

  The projection display device 700 includes a display information output source 710, a display information processing circuit 720, a display drive circuit 730 (display driver), a liquid crystal panel 740, a clock generation circuit 750, and a power supply circuit 760. The display information output source 710 includes a ROM (Read Only Memory) and a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs an image signal, and the like. Based on this, display information such as an image signal in a predetermined format is output to the display information processing circuit 720. The display information processing circuit 720 can include an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, and the like. The display driving circuit 730 includes a gate driver and a source driver, and drives the liquid crystal panel 740. The power supply circuit 760 supplies power to each circuit described above.

  FIG. 19 shows a schematic configuration diagram of a main part of the projection display device.

  The projection display device includes a light source 810, dichroic mirrors 813 and 814, reflection mirrors 815, 816 and 817, an incident lens 818, a relay lens 819, an exit lens 820, liquid crystal light modulators 822, 823 and 824, a cross dichroic prism 825, A projection lens 826 is included. The light source 810 includes a lamp 811 such as a metal halide and a reflector 812 that reflects the light of the lamp. The blue light / green light reflecting dichroic mirror 813 transmits red light of the light flux from the light source 810 and reflects blue light and green light. The transmitted red light is reflected by the reflection mirror 817 and is incident on the liquid crystal light modulation device 822 for red light. On the other hand, of the color light reflected by the dichroic mirror 813, green light is reflected by the dichroic mirror 814 that reflects green light and enters the liquid crystal light modulator 823 for green light. On the other hand, the blue light also passes through the second dichroic mirror 814. For blue light, in order to prevent light loss due to a long optical path, a light guide means 821 including a relay lens system including an incident lens 818, a relay lens 819, and an output lens 820 is provided, through which blue light is blue. The light enters the light liquid crystal light modulator 824. The three color lights modulated by the respective light modulation circuits are incident on the cross dichroic prism 825. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. These dielectric multilayer films combine the three color lights to form light representing a color image. As described above, the projection unit of the projection display apparatus is configured. The light synthesized by this projection means is projected onto the screen 827 by the projection lens 826 which is a projection optical system, and the image is enlarged and displayed.

2.2 Mobile Phone Another example of electronic equipment configured using the liquid crystal device 10 is a mobile phone.

  FIG. 20 is a block diagram showing a configuration example of a mobile phone to which the liquid crystal device 10 according to this embodiment is applied. In FIG. 20, the same parts as those in FIG. 1 or FIG.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies image data captured by the CCD camera to the display controller 38 in the YUV format.

  Mobile phone 900 includes LCD panel 20. The LCD panel 20 is driven by a source driver 30 and a gate driver 32. The LCD panel 20 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels.

  The display controller 38 is connected to the source driver 30 and the gate driver 32, and supplies gradation data in RGB format to the source driver 30.

  The power supply circuit 100 is connected to the source driver 30 and the gate driver 32 and supplies a driving power supply voltage to each driver. Further, the counter electrode voltage Vcom is supplied to the counter electrode of the LCD panel 20.

  The host 940 is connected to the display controller 38. The host 940 controls the display controller 38. The host 940 can supply the gradation data received via the antenna 960 to the display controller 38 after demodulating the modulation / demodulation unit 950. The display controller 38 displays on the LCD panel 20 by the source driver 30 and the gate driver 32 based on the gradation data.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the LCD panel 20 based on operation information from the operation input unit 970.

  In FIG. 20, it can be said that the host 940 or the display controller 38 is means for supplying gradation data.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

1 is a diagram illustrating an outline of a configuration of an active matrix liquid crystal device according to an embodiment. FIG. 6 is a diagram illustrating an outline of another configuration of an active matrix liquid crystal device according to the present embodiment. FIG. 3 is a block diagram of a configuration example of the gate driver in FIG. 1 or FIG. 2. FIG. 3 is a block diagram of a configuration example of the source driver in FIG. 1 or FIG. 2. FIG. 6 is an operation explanatory diagram of a source driver in the present embodiment. The figure which shows the structural example of the principal part of the source driver in this embodiment. FIG. 7 is a block diagram of a configuration example of the voltage selection circuit in FIG. 6. The figure which shows the outline | summary of a structure of the voltage selection block of FIG. FIG. 9 is a circuit diagram of a configuration example of the voltage selection block of FIG. 8. FIG. 9 is a timing diagram of an operation example of the voltage selection circuit of FIG. 8. The block diagram of the structural example of the output control block of FIG. The figure which shows the outline | summary of a structure of the control register part of the source driver in this embodiment. 13A and 13B are explanatory diagrams of the first exception process. 14A and 14B are explanatory diagrams of the first exception processing. FIG. 15A, FIG. 15B, FIG. 15C, and FIG. 15D are explanatory diagrams of second exception processing. FIGS. 16A, 16B, 16C, and 16D are explanatory diagrams of second exception processing. FIG. 7 is a circuit diagram of a configuration example of the output circuit of FIG. 6. The block diagram of the structural example of the projection type display apparatus to which the liquid crystal device in this embodiment was applied. The schematic block diagram of the principal part of a projection type display apparatus. 1 is a block diagram of a configuration example of a mobile phone to which a liquid crystal device according to an embodiment is applied.

Explanation of symbols

10 liquid crystal device, 20 LCD panel, 30 source driver,
32 gate drivers, 38 display controllers, 50 I / O buffers,
52 display memory, 54 line latch, 56 gradation voltage generation circuit,
58 DAC, 60 source line drive circuit, 100 power supply circuit,
DEC _{1 to} DEC _N voltage selection circuit, DLAT _{1 to} DLATN data latch,
GL1~GLM gate lines, _OCB 1 ~OCB _N output control block,
OUT ₁ to OUT _N output circuit, SL1 to SLn source line

Claims (12)

A source driver for driving a source line of an electro-optical device based on (j + k) (j, k are natural numbers) bit gradation data,
2 ^j gradation signal lines;
A gradation voltage selection circuit for outputting two gray scale voltages of 2 ^j types of gradation voltages supplied by 2 ^j present grayscale signal lines,
Of the voltages between the two voltages including the low potential side gradation voltage and the high potential side gradation voltage from the gradation voltage selection circuit, the gradation voltage corresponding to the lower k bits of the gradation data is used as the source line. A source line driving circuit for outputting ,
The source line driving circuit is
A voltage follower circuit including a differential amplifier having a differential transistor pair and a drive unit that drives a source line based on an output of the differential amplifier;
Of the first and second differential transistor groups constituting the differential transistor pair, the second differential transistor group includes ^{first to kth} transistors each having 2 ^k−1 transistors. Transistor group,
The source line driving circuit is
A control signal corresponding to each bit data of the lower k bits of the gradation data is applied to the gate of each transistor group of the first to kth transistor groups, and the low potential side gradation voltage or the high potential side By supplying a control signal set to any voltage level of the gradation voltage, the gradation data of the voltage between the two voltages including the low potential side gradation voltage and the high potential side gradation voltage is changed. A source driver characterized in that a gradation voltage corresponding to lower-order k-bit data is output to a source line . In claim 1 ,
Including a first gradation selection exception handling register;
When the gradation voltage selection circuit outputs the gradation voltage sequentially assigned to VSEL1 to VSEL (2 ^k ) to the high potential side based on the low-order k-bit data with the low potential side gradation voltage as VSEL1. In addition,
A source driver characterized in that whether or not to assign the high potential side gradation voltage to VSEL (2 ^k ) is determined according to a set value of the first gradation selection exception processing register . In claim 2 ,
A second gradation selection exception handling register;
When the high potential side gradation voltage is assigned to VSEL (2 ^k ) by the first gradation selection exception processing register,
Only when the data of each bit of the gradation data is all 0 or when the data of each bit of the gradation data is all 1, according to the set value of the second gradation selection exception processing register, The source driver characterized in that the highest potential gradation voltage among the ^2j kinds of gradation voltages is assigned as the high potential side gradation voltage. In any one of Claims 1 thru | or 3 ,
Before Kikaicho voltage selection circuit, as VSEL1 the high potential side gradation voltage, and outputs the gray scale voltage to be assigned to sequential VSEL1~VSEL ^{(2 k)} to the low potential side based on the data of the lower k bits In case,
A source driver characterized in that whether or not to assign the low potential side gradation voltage to VSEL (2 ^k ) is determined according to a set value of the first gradation selection exception processing register . Multiple gate lines,
Multiple source lines,
Each pixel is a plurality of pixels specified by each gate line and each source line;
Electro-optical device characterized in that it comprises a source driver according to any one of claims 1 to 4 for driving the plurality of source lines. In claim 5 ,
An electro-optical device comprising a gate driver for scanning the plurality of gate lines. An electro-optical device comprising the source driver according to claim 1 . An electro-optical device according to any one of claims 5 to 7 ,
A light source for entering light into the electro-optical device;
And a projection means for projecting light emitted from the electro-optical device. A projection display device comprising the source driver according to claim 1 . An electronic apparatus comprising the electro-optical device according to claim 5 . An electro-optical device according to any one of claims 5 to 7 ,
Means for supplying gradation data to the electro-optical device. An electronic apparatus comprising a source driver according to any one of claims 1 to 4.

Images