JP5374867B2 - Source driver, electro-optical device, projection display device, and electronic device - Google Patents

Source driver, electro-optical device, projection display device, and electronic device Download PDF

Info

Publication number
JP5374867B2
JP5374867B2 JP2007327196A JP2007327196A JP5374867B2 JP 5374867 B2 JP5374867 B2 JP 5374867B2 JP 2007327196 A JP2007327196 A JP 2007327196A JP 2007327196 A JP2007327196 A JP 2007327196A JP 5374867 B2 JP5374867 B2 JP 5374867B2
Authority
JP
Japan
Prior art keywords
dac
voltage
gradation
output
source line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007327196A
Other languages
Japanese (ja)
Other versions
JP2008233863A (en
Inventor
晶 森田
Original Assignee
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2007043309 priority Critical
Priority to JP2007043309 priority
Application filed by セイコーエプソン株式会社 filed Critical セイコーエプソン株式会社
Priority to JP2007327196A priority patent/JP5374867B2/en
Priority claimed from US12/071,374 external-priority patent/US8427415B2/en
Publication of JP2008233863A publication Critical patent/JP2008233863A/en
Publication of JP5374867B2 publication Critical patent/JP5374867B2/en
Application granted granted Critical
Application status is Active legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a source driver which can achieve high grayscale precision even with an increased number of grayscales, an electro-optical device, a projection-type display device, and an electronic instrument. <P>SOLUTION: The source driver 30 includes P (P is a positive integer of &ge;2) grayscale signal lines, a grayscale voltage being supplied to each of the grayscale signal lines, Q (Q&le;P, Q is a positive integer) switch signal lines, a grayscale voltage being supplied to each of the switch signal lines, a first DAC 58A that outputs a grayscale voltage among grayscale voltages supplied to the grayscale signal lines based on grayscale data, a second DAC 58B that outputs a grayscale voltage among grayscale voltages supplied to the switch signal lines based on the grayscale data, and a source line driver section that drives a source line based on an output from the first DAC 58A or the second DAC 58B. The source line driver section generates a drive signal of the source line based on the output from the second DAC 58B, and then generates a drive signal of the source line based on the output from the first DAC 58A within one horizontal scan period. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a source driver, an electro-optical device, a projection display device, an electronic apparatus, and the like.

  2. Description of the Related Art Conventionally, an active matrix type liquid crystal panel using a switching element such as a thin film transistor (hereinafter referred to as TFT) is known as a liquid crystal panel (electro-optical device) used in a mobile phone or a projection display device. ing.

  Until now, when an active matrix liquid crystal panel is used in a portable electronic device such as a mobile phone, it has been considered difficult to reduce power consumption in the active matrix method. However, in recent years, even in an active matrix liquid crystal panel, a sufficiently low power consumption has been realized. On the other hand, the advantage of being suitable for multi-coloring and moving image display by an active matrix liquid crystal panel has been attracting attention.

In order to perform high-accuracy image display, generally, gamma correction corresponding to the gradation characteristics of the display device is performed on the drive signal of the display device. Taking a liquid crystal panel as an example, a gradation voltage corrected so as to realize an optimal transmittance of a pixel is output based on gradation data for performing gradation display by gamma correction. Then, the source line is driven based on this gradation voltage.
JP-A-7-306660

  In recent years, the demand for higher image quality of display images has further increased, and there has been an increasing demand for multi-gradation for source drivers that drive source lines of electro-optical devices. In this case, it is necessary to supply more types of gradation voltages to the output buffers that drive the source lines of the plurality of source lines of the electro-optical device.

  In addition, as the screen size of the liquid crystal panel is increased, higher definition is progressing, and the number of pixels (number of dots) per scanning line is greatly increased. For this reason, it is necessary to apply a gradation voltage selected from a plurality of gradation voltages to each pixel within one prescribed horizontal scanning period.

  However, one horizontal scanning period becomes shorter and it becomes difficult to apply a voltage having a desired potential to each pixel within a specified time. For this reason, it is very difficult for the source driver to achieve high gradation accuracy.

  Further, in a liquid crystal panel, in order to avoid applying a direct current component to a pixel (liquid crystal) over a long period, the voltage supplied to the source line is changed at a given period by polarity inversion driving. Is called. The greater the change in voltage, the longer it takes to converge the voltage level after the change, making it more difficult to achieve high gradation accuracy.

  In Patent Document 1, in order to reduce the number of gradation voltage signal lines, a stepped voltage is generated, and a desired voltage is sampled from a plurality of voltages set in a stepped manner to thereby generate a pulse width modulation signal. A technique for expressing halftones by generating a gray level is disclosed. However, the gradation expression is limited to the pulse width modulation method, and there is a problem that it is difficult to improve the image quality when a larger number of gradations are required.

  In addition, it is difficult to set all the levels of a plurality of voltages set in a staircase shape with high accuracy, and even if the level can be set with high accuracy, the circuit scale becomes complicated. In particular, as the number of gradations increases and the voltage difference between the gradations decreases, it is difficult to generate a stepped voltage in which the level of each voltage is set with high accuracy as disclosed in Patent Document 1. Become.

  The demand for high-definition and multi-gradation image display as described above is common to projection display devices.

  According to some aspects of the present invention, it is possible to provide a source driver, an electro-optical device, a projection display device, and an electronic apparatus that can achieve high gradation accuracy even when the number of gradations increases.

In order to solve the above problems, the present invention
A source driver for driving a source line of an electro-optical device based on gradation data,
P (P is a positive integer greater than or equal to 2) gradation signal lines, and P gradation signal lines to which the corresponding gradation voltage is supplied to each of the P gradation signal lines. When,
Q (Q ≦ P, Q is a positive integer) switching signal lines, and Q switching signals are supplied with a corresponding gradation voltage to each of the Q switching signal lines. Lines and,
A first DAC that outputs one gradation voltage among the P kinds of gradation voltages supplied to the P gradation signal lines based on the gradation data;
A second DAC that outputs one gradation voltage among the Q kinds of gradation voltages supplied to the Q switching signal lines based on the gradation data;
A source line driver that drives the source line based on the output of the first or second DAC,
The source line driver is
The first drive signal of the source line is generated based on the output of the first DAC after the second drive signal of the source line is generated based on the output of the second DAC within one horizontal scanning period. Related to the source driver that generates

  In the present invention, the voltage of the gradation signal line is supplied after the voltage of the switching signal line provided for shock absorption is once supplied to the input of the source line driver. For this reason, the capacitive division between the parasitic capacitance of the input of the source line driver and the parasitic capacitance of the signal line is repeated, and the width of the voltage fluctuation when switching the gradation voltage is reduced. Therefore, according to the present invention, even when the gradation voltage is changed by polarity inversion driving or the like, the voltage of the gradation signal line does not fluctuate, and the voltage is applied to the source line driver in a stable potential level. Can supply. As a result, a source driver that realizes high gradation accuracy can be provided.

In the source driver according to the present invention,
The source line driver is
An output buffer for driving the source line based on the output of the first or second DAC;
Within the one horizontal scanning period, the source line is driven by the output buffer during the buffer output period, and the input voltage of the output buffer can be supplied to the source line during the DAC output period after the buffer output period. .

  According to the present invention, the voltage of the source line can be set early in the buffer output period. At this time, the accuracy of the voltage level of the source line is low due to the offset of the output buffer. Therefore, in the present invention, the input voltage of the output buffer is set to the source line as it is in the DAC output period. Thus, according to the present invention, the voltage of the source line can be set with high accuracy in the DAC output period.

In the source driver according to the present invention,
The buffer output period is
The source line driving unit may overlap with a period for driving the source line based on the output of the second DAC.

  According to the present invention, since the source line driving unit drives the source line based on the output voltage of the second DAC in the buffer output period, the voltage of the source line is quickly stabilized at a voltage level with coarse accuracy. be able to.

In the source driver according to the present invention,
The DAC output period may be started after a start timing of a period in which the source line driver drives the source line based on the output of the first DAC.

  According to the present invention, in the DAC output period, the grayscale voltage from the first DAC is supplied to the source line, and the voltage of the source line can be set with a highly accurate voltage level.

In the source driver according to the present invention,
In the period t B in which the source line driver drives the source line based on the output of the second DAC, the impedance of one switching signal line is Z B , and the source line driver is the first DAC. If the impedance of one of said tone signal line in a period t a which drives the source line based on the output of the DAC and the Z a,
t A / t B may be Z A / Z B.

In the present invention, the voltage at the input node of the source line driver section gradually changes according to a time constant determined by the capacitance component and resistance component of the signal line to which the voltage is transmitted. Since the capacitance component is mainly determined by the input capacitance of the source line driver, the difference in time constant in the periods t A and t B is caused by the difference in impedances Z A and Z B. Therefore, according to the present invention, the output of the first DAC can be used for as long a time as possible without wastefully using the output of the second DAC, and the grayscale voltage can be input to the source line driving unit with high accuracy. It can be given to the node.

In the source driver according to the present invention,
P is 2 K (K is an integer of 2 or more),
Q may be 2 KL (K> L, L is a natural number).

  According to the present invention, by setting P and Q to numerical values of powers of 2, it is possible to select a gradation voltage using only the necessary bits of gradation data, and therefore only bit division of gradation data is possible. This simplifies the source driver configuration. Furthermore, by setting Q to a value smaller than P, the layout area of signal lines and DACs can be reduced.

In the source driver according to the present invention,
A gradation voltage generating circuit for generating a plurality of gradation voltages obtained by resistance-dividing between two given voltages;
The gradation voltage generated by the gradation voltage generation circuit is supplied to each gradation signal line,
At least one of the switching signal lines may be driven by a buffer circuit.

  According to the present invention, the voltage of the gradation signal line can be set with high accuracy. Furthermore, according to the present invention, since the voltage of the switching signal line is driven by the buffer circuit, the voltage of the switching signal line can be set at a high speed, and the buffer circuit is compared with the case where the buffer circuit is provided for each gradation signal line Therefore, a significant increase in layout area can be suppressed.

The present invention also provides
A source driver for driving a source line of an electro-optical device based on gradation data,
P (P is a positive integer greater than or equal to 2) gradation signal lines, and P gradation signal lines to which the corresponding gradation signals are supplied to each of the P gradation signal lines. When,
Q (Q ≦ P, Q is a positive integer) switching signal lines, and Q switching signals are supplied with a corresponding gradation signal to each of the Q switching signal lines. Lines and,
A first DAC that outputs one of the P types of gradation signals supplied to the P number of gradation signal lines based on the gradation data;
A second DAC that outputs one of the Q types of gradation signals supplied to the Q switching signal lines based on the gradation data;
A source line driver that drives the source line based on the output of the first or second DAC,
The source line driver is
The first drive signal of the source line is generated based on the output of the first DAC after the second drive signal of the source line is generated based on the output of the second DAC within one horizontal scanning period. Relates to a source driver characterized by generating

The present invention also provides
Multiple gate lines,
Multiple source lines,
Each pixel is a plurality of pixels specified by each gate line and each source line;
The present invention relates to an electro-optical device including any of the above-described source drivers for driving the plurality of source lines.

In the electro-optical device according to the invention,
A gate driver for scanning the plurality of gate lines may be included.

The present invention also provides
The present invention relates to an electro-optical device including the source driver described above.

  According to any one of the above inventions, it is possible to provide an electro-optical device to which a source driver that can achieve high gradation accuracy even when the number of gradations increases is applied.

The present invention also provides
Any of the above electro-optical devices;
A light source for entering light into the electro-optical device;
The present invention relates to a projection display apparatus including projection means for projecting light emitted from the electro-optical device.

The present invention also provides
The present invention relates to a projection display apparatus including any one of the source drivers described above.

  According to any one of the above inventions, it is possible to provide a projection display device to which a source driver that can achieve high gradation accuracy even when the number of gradations is increased is applied.

The present invention also provides
The present invention relates to an electronic apparatus including any of the electro-optical devices described above.

The present invention also provides
Any of the above electro-optical devices;
The present invention relates to an electronic apparatus including means for supplying gradation data to the electro-optical device.

The present invention also provides
The present invention relates to an electronic device including any of the source drivers described above.

  According to any one of the above-described inventions, it is possible to provide an electronic device to which a source driver that can achieve high gradation accuracy even when the number of gradations increases is applied.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Liquid Crystal Device FIG. 1 shows an outline of the configuration of an active matrix liquid crystal device according to this embodiment.

  The liquid crystal device 10 includes a liquid crystal display (LCD) panel (display panel in a broad sense, electro-optical device in a broader sense) 20. The LCD panel 20 is formed on a glass substrate, for example. On this glass substrate, a plurality of gate lines (scanning lines) GL1 to GLM (M is an integer of 2 or more) arranged in the Y direction and extending in the X direction, and a source line arranged in the X direction and extending in the Y direction, respectively. (Data lines) SL1 to SLN (N is an integer of 2 or more) are arranged. The pixel region corresponds to the intersection position of the gate line GLm (1 ≦ m ≦ M, m is an integer, the same applies hereinafter) and the source line SLn (1 ≦ n ≦ N, n is an integer, the same applies hereinafter). (Pixel) is provided, and a thin film transistor (hereinafter abbreviated as TFT) 22 mn is disposed in the pixel region. The electro-optical device can include a device using a light emitting element such as an organic EL (Electro Luminescence) element or an inorganic EL element.

  The gate of the TFT 22mn is connected to the gate line GLm. The source of the TFT 22mn is connected to the source line SLn. The drain of the TFT 22mn is connected to the pixel electrode 26mn. Liquid crystal is sealed between the pixel electrode 26mn and the counter electrode 28mn facing the pixel electrode 26mn, thereby forming a liquid crystal capacitor (liquid crystal element in a broad sense) 24mn that is an element capacitor. The transmittance of the pixel changes according to the applied voltage between the pixel electrode 26mn and the counter electrode 28mn. The counter electrode voltage Vcom is supplied to the counter electrode 28mn. The element capacitance can include a liquid crystal capacitance formed in a liquid crystal element and a capacitance formed in an EL element such as an inorganic EL element.

  Such an LCD panel 20 includes, for example, a first substrate on which pixel electrodes and TFTs are formed and a second substrate on which counter electrodes are formed, and a liquid crystal as an electro-optical material is interposed between the two substrates. It is formed by enclosing.

  The liquid crystal device 10 includes a source driver (display driver in a broad sense, drive circuit in a broader sense) 30. The source driver 30 drives the source lines SL1 to SLN of the LCD panel 20 based on the gradation data.

  The liquid crystal device 10 can include a gate driver (scan driver in a broad sense) 32. The gate driver 32 scans the gate lines GL1 to GLM of the LCD panel 20 within one vertical scanning period.

  The liquid crystal device 10 can include a power supply circuit 100. The power supply circuit 100 generates voltages (signals in a broad sense) necessary for driving the source lines and supplies them to the source driver 30. The power supply circuit 100 generates, for example, power supply voltages VDDH and VSSH necessary for driving a source line of the source driver 30 and a voltage of a logic unit of the source driver 30.

  The power supply circuit 100 generates a voltage necessary for scanning the gate line and supplies it to the gate driver 32.

  Further, the power supply circuit 100 generates a counter electrode voltage Vcom. In accordance with the timing of the polarity inversion signal POL generated by the source driver 30, the power supply circuit 100 generates a common electrode voltage Vcom that periodically repeats the high potential side voltage VCOMH and the low potential side voltage VCOML on the LCD panel 20. Output to electrode.

  The liquid crystal device 10 can include a display controller 38. The display controller 38 controls the source driver 30, the gate driver 32, and the power supply circuit 100 according to contents set by a host such as a central processing unit (hereinafter abbreviated as CPU) (not shown). For example, the display controller 38 sets an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the source driver 30 and the gate driver 32. Here, the display controller 38 or the host can supply the gradation data to the source driver 30.

  In FIG. 1, the liquid crystal device 10 includes the power supply circuit 100 or the display controller 38, but at least one of these may be provided outside the liquid crystal device 10. Alternatively, the liquid crystal device 10 may be configured to include a host.

  The source driver 30 may incorporate at least one of the gate driver 32 and the power supply circuit 100.

  Furthermore, some or all of the source driver 30, the gate driver 32, the display controller 38, and the power supply circuit 100 may be formed on the LCD panel 20. For example, in FIG. 2, a source driver 30 and a gate driver 32 are formed on the LCD panel 20. As described above, the LCD panel 20 includes a plurality of source lines, a plurality of gate lines, a plurality of switching elements connected to the gate lines of the plurality of gate lines, and a plurality of source lines. And a display driver for driving the source line. A plurality of pixels are formed in the pixel formation region 80 of the LCD panel 20.

1.1 Gate Driver FIG. 3 shows a configuration example of the gate driver 32 shown in FIG.

  The gate driver 32 includes a shift register 40, a level shifter 42, and an output buffer 44.

  The shift register 40 includes a plurality of flip-flops provided corresponding to the gate lines and sequentially connected. When the shift register 40 holds the start pulse signal STV in the flip-flop in synchronization with the clock signal CPV, the shift register 40 sequentially shifts the start pulse signal STV to the adjacent flip-flop in synchronization with the clock signal CPV. The clock signal CPV input here is a horizontal synchronizing signal, and the start pulse signal STV is a vertical synchronizing signal.

  The level shifter 42 shifts the voltage level from the shift register 40 to a voltage level corresponding to the liquid crystal element of the LCD panel 20 and the transistor capability of the TFT. As this voltage level, for example, a high voltage level of 20 V to 50 V is required.

  The output buffer 44 buffers the scanning voltage shifted by the level shifter 42 and outputs it to the gate line to drive the gate line.

1.2 Source Driver FIG. 4 shows a block diagram of a configuration example of the source driver 30 of FIG. 1 or FIG.

  The source driver 30 includes an I / O buffer 50, a display memory 52, a line latch 54, a gradation voltage generation circuit (a reference voltage generation circuit in a broad sense, a reference signal generation circuit in a broader sense) 56, and a DAC (Digital / Analog Converter). ) 58 (a gradation voltage selection circuit in a broad sense, a gradation signal selection circuit in a broader sense), and a source line drive circuit (source line drive unit) 60.

  For example, the gradation data D is input to the source driver 30 from the display controller 38. The gradation data D is input in synchronization with the dot clock signal DCLK and buffered in the I / O buffer 50. The dot clock signal DCLK is supplied from the display controller 38.

  The I / O buffer 50 is accessed by the display controller 38 or a host (not shown). The gradation data buffered in the I / O buffer 50 is written in the display memory 52. The gradation data read from the display memory 52 is output to the display controller 38 and the like after being buffered by the I / O buffer 50.

  The display memory (gradation data memory) 52 includes a plurality of memory cells provided corresponding to the output lines in which the memory cells are connected to the source lines. Each memory cell is specified by a row address and a column address. Each memory cell for one scan line is specified by a line address.

  The address control circuit 62 generates a row address, a column address, and a line address for specifying a memory cell in the display memory 52. The address control circuit 62 generates a row address and a column address when writing gradation data into the display memory 52. That is, the gradation data buffered in the I / O buffer 50 is written into the memory cell of the display memory 52 specified by the row address and the column address.

  The row address decoder 64 decodes the row address and selects a memory cell of the display memory 52 corresponding to the row address. The column address decoder 66 decodes the column address and selects a memory cell of the display memory 52 corresponding to the column address.

  When the gradation data is read from the display memory 52 and output to the line latch 54, the address control circuit 62 generates a line address. That is, the line address decoder 68 decodes the line address and selects a memory cell of the display memory 52 corresponding to the line address. Then, gradation data for one horizontal scan read from the memory cell specified by the line address is output to the line latch 54.

  The address control circuit 62 generates a row address and a column address when reading the gradation data from the display memory 52 and outputting it to the I / O buffer 50. That is, the gradation data held in the memory cell of the display memory 52 specified by the row address and the column address is read to the I / O buffer 50. The gradation data read to the I / O buffer 50 is extracted by the display controller 38 or a host (not shown).

  Therefore, in FIG. 4, the row address decoder 64, the column address decoder 66, and the address control circuit 62 function as a write control circuit that performs writing control of gradation data to the display memory 52. On the other hand, in FIG. 4, the line address decoder 68, the column address decoder 66, and the address control circuit 62 function as a readout control circuit that performs readout control of gradation data from the display memory 52.

  The line latch 54 latches the grayscale data for one horizontal scan read from the display memory 52 at the change timing of the horizontal synchronization signal HSYNC. The line latch 54 includes a plurality of registers in which each register holds gradation data for one dot. The gradation data for one dot read from the display memory 52 is taken into each of the plurality of registers of the line latch 54.

  The gradation voltage generation circuit 56 generates a plurality of gradation voltages in which each gradation voltage (reference voltage in a broad sense, reference signal in a broader sense) corresponds to each gradation data. More specifically, the gradation voltage generation circuit 56 generates a plurality of gradation voltages corresponding to each gradation data, based on the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH. . More specifically, the gradation voltage generation circuit 56 generates two sets of gradation voltage groups. The gradation voltages of one set of gradation voltage groups generated by the gradation voltage generation circuit 56 are the gradation signal lines of P (P is a positive integer of 2 or more) gradation signal lines provided in the DAC 58. To be supplied. Each gradation voltage of the other set of gradation voltages generated by the gradation voltage generation circuit 56 is Q (Q ≦ P, Q is a positive integer) provided in the DAC 58 for absorbing shock accompanying charge transfer. Are supplied to each switching signal line.

  Such a gradation voltage generation circuit 56 has two resistance circuits (ladder resistance circuits) supplied with the high-potential-side power supply voltage VDDH and the low-potential-side power supply voltage VSSH at both ends. P types of gradation voltages are simultaneously output from among the voltages at the divided nodes, and Q types of gradation voltages are simultaneously output from among the voltages at the plurality of divided nodes of the other resistance circuit.

  The DAC 58 generates a gradation voltage corresponding to the gradation data output from the line latch 54 for each output line that is an output of the source line driving circuit 60. More specifically, the DAC 58 converts the gradation data for one output line of the source line driver circuit 60 output from the line latch 54 from the plurality of gradation voltages generated by the gradation voltage generation circuit 56. A corresponding gradation voltage is selected, and the selected gradation voltage is output.

  More specifically, the DAC 58 has two DACs as the first and second DACs. One DAC selects the gradation voltage corresponding to the data of all bits of the gradation data from the P kinds of gradation voltages supplied to the P gradation signal lines. The other DAC has a gradation voltage corresponding to partial bit data (more specifically, higher-order bit data) of gradation data, Q types of levels supplied to Q switching signal lines. Select from among regulated voltages.

Here, it is desirable that P is 2 K (K is an integer of 2 or more) and Q is 2 KL (K> L, L is a natural number). By setting P and Q to powers of 2, gradation voltage selection processing can be performed using only the necessary bits of gradation data. Therefore, the source driver can be configured only by bit division of gradation data. It can be simplified. Furthermore, by setting Q to a value smaller than P, the layout area of signal lines and DACs can be reduced.

  The source line driving circuit 60 drives a plurality of output lines whose output lines are connected to the source lines of the LCD panel 20. More specifically, the source line driving circuit 60 drives each output line based on the gradation voltage output for each output line by the voltage selection circuit of the DAC 58. The source line drive circuit 60 includes an output circuit provided for each output line. Each output circuit drives the source line based on the gradation voltage from each voltage selection circuit. Each output circuit is a voltage follower circuit, and this voltage follower circuit can be constituted by an operational amplifier or the like connected to a voltage follower.

  In the present embodiment, when the gradation voltage is changed by polarity inversion driving or the like, high gradation accuracy is realized by stabilizing the input of each output circuit of the source line driving circuit 60 at an early stage. For this reason, in the present embodiment, the voltage of the gradation signal line is supplied after the voltage of the switching signal line provided for shock absorption is once supplied to the output circuits of the source line driving circuit 60. That is, by repeating the capacitive division between the input parasitic capacitance of each output circuit and the signal line parasitic capacitance, the width of the voltage fluctuation when switching the gradation voltage is reduced. Therefore, even when the gradation voltage is changed by polarity inversion driving or the like, a voltage is applied to each output circuit of the source line driver circuit 60 in a stable potential level without fluctuation of the voltage of the gradation signal line. Can supply. As a result, a source driver that realizes high gradation accuracy can be provided.

In the following description, it is assumed that K is 8, L is 3, gradation signal lines are 256 (= 2 8 ), and switching signal lines are 32 (= 2 5 ). The present embodiment is not limited to the number of gradation signal lines and the number of switching signal lines.

  FIG. 5 shows a block diagram of a configuration example of the gradation voltage generation circuit 56, the DAC 58, and the source line driver circuit 60 of FIG.

  In FIG. 5, the same parts as those in FIG.

  The gradation voltage generation circuit 56 includes first and second gradation voltage generation circuits 56A and 56B. High potential power supply voltage VDDH and low potential power supply voltage VSSH are supplied to the first gradation voltage generation circuits 56A and 56B. The first gradation voltage generation circuit 56A includes a resistance circuit to which the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH are supplied at both ends, and outputs voltages of a plurality of divided nodes provided in the resistance circuit. As a result, 256 kinds of gradation voltages V0A to V255A are output. The second gradation voltage generation circuit 56B includes a resistance circuit to which the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH are supplied at both ends, and outputs voltages of a plurality of divided nodes provided in the resistance circuit. Thus, 32 kinds of gradation voltages V0B to V31B are output.

  FIG. 6 is an operation explanatory diagram of the gradation voltage generation circuit 56 of FIG.

  The first gradation voltage generation circuit 56A of the gradation voltage generation circuit 56 in FIG. 5 corrects 256 types of voltages corresponding to the 8-bit gradation data in accordance with the gradation characteristics of the LCD panel 20. Output as gradation voltages V0A to V255A. On the other hand, the second gradation voltage generation circuit 56B of the gradation voltage generation circuit 56 in FIG. 5 corresponds to the upper 5 bits of 8-bit gradation data according to the gradation characteristics of the LCD panel 20. 32 types of voltages can be corrected and output as gradation voltages V0B to V31B. In FIG. 6, the gradation voltage V4A as the gradation voltage V0B, the gradation voltage V12A as the gradation voltage V1B, the gradation voltage V20A as the gradation voltage V2B,..., The gradation voltage V244A as the gradation voltage V30B, A gradation voltage V252A is output as the voltage V31B.

  In FIG. 6, each of the gradation voltages V0B to V31B generated by the second gradation voltage generation circuit 56B corresponds to any of the gradation voltages V0A to V255A generated by the first gradation voltage generation circuit 56A. However, the present embodiment is not limited to this. For example, the grayscale voltages V0B to V31B generated by the second grayscale voltage generation circuit 56B are different from the grayscale voltages V0A to V255A generated by the first grayscale voltage generation circuit 56A. There may be.

  Furthermore, in FIG. 5, the first and second gradation voltage generation circuits 56A and 56B are described as generating a plurality of gradation voltages using the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH. However, the present embodiment is not limited to this. For example, at least one of the high-potential-side power supply voltage VDDH and the low-potential-side voltage VSSH supplied to the second gradation voltage generation circuit 56B may be another voltage.

  In FIG. 5, the DAC 58 includes first and second DACs 58A and 58B. To the first DAC 58A, 256 gradation signal lines to which the gradation voltages V0A to V255A are supplied are connected to the gradation signal lines. The second DAC 58B is connected to 32 switching signal lines to which each voltage of the gradation voltages V0B to V31B is supplied to each switching signal line.

The first DAC 58A includes voltage selection circuits DEC 1 A to DEC N A provided for each output line. Each of the voltage selection circuits DEC 1 A to DEC N A has 256 gradation signal lines based on 8-bit data of gradation data D [7: 0] stored in the line latch 54. One gradation voltage from the gradation voltages V0A to V255A is output as the output voltage DACAOUT.

The second DAC 58B includes voltage selection circuits DEC 1 B to DEC N B provided for each output line. Each voltage selection circuit of the voltage selection circuits DEC 1 B to DEC N B converts the gradation data D [7: 0] stored in the line latch 54 into 5-bit data of the upper bit data D [7: 3]. Based on this, one gradation voltage is output as the output voltage DACBOUT from among the gradation voltages V0B to V31BA of the 32 switching signal lines.

The source line drive circuit 60 includes output circuits OUT 1 to OUT N provided for each output line. Each output circuit generates a drive signal for the source line (drives the source line) based on the output voltage DACAOUT of the voltage selection circuit from the first DAC 58A or the output voltage DACBOUT of the voltage selection circuit from the second DAC 58B. . More specifically, after the output voltage DACAOUT of the voltage selection circuit from the first DAC 58A is once set as the input voltage of each output circuit, the output voltage DACBOUT of the voltage selection circuit from the second DAC 58B is set as the input voltage. Is set.

  Thereby, the fluctuation of the input voltage of the output circuit is suppressed, the fluctuation of the voltage supplied to the source line is also reduced, and high gradation accuracy can be realized.

  FIG. 7 shows a configuration main part per output of the source driver of FIG.

  7, the same parts as those in FIG. 6 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. FIG. 7 shows only a portion for driving the source line SL1 in the configuration of FIG.

  In FIG. 7, each gradation signal line is directly electrically connected to each divided node provided in the resistance circuit of the first gradation voltage generating circuit 56A. In addition, each switching signal line is directly electrically connected to each divided node provided in the resistance circuit of the second gradation voltage generating circuit 56B. In this way, the voltage applied to the gradation signal line and the voltage applied to the switching signal line can be set with high accuracy.

The output circuit OUT 1 includes an operational amplifier AMP 1 (output buffer in a broad sense) connected to a voltage follower, first and second DAC output switches DSWA 1 and DSWB 1 , a buffer drive switch BDSW 1, and a DAC And a driving switch DDSW 1 .

The first end of the DAC output switch DSWA 1, output voltage DACAOUT supply from the voltage selection circuit DEC 1 A of the first DAC58A, the other end of the first DAC output switch DSWA 1 includes an operational amplifier AMP 1 Is electrically connected to the non-inverting input terminal. The first DAC output switch DSWA 1 is ON / OFF controlled (switch controlled) by a control signal DACA_ENB generated in a control circuit (not shown) of the source driver 30.

One end of the second DAC output switch DSWB 1 is supplied with the output voltage DACBOUT from the voltage selection circuit DEC 1 B of the second DAC 58B, and the other end of the second DAC output switch DSWB 1 is the operational amplifier AMP 1. Is electrically connected to the non-inverting input terminal. The second DAC output switch DSWB 1 is on / off controlled (switch controlled) by a control signal DACB_ENB generated in a control circuit (not shown) of the source driver 30.

At one end of the buffer drive switch BDSW 1, it is supplied the output voltage of the operational amplifier AMP 1 is to the other end of the buffer drive switch BDSW 1, is connected to an output line electrically connected to the source line SL1 . The buffer drive switch BDSW 1 is on / off controlled (switch controlled) by a control signal OPAMP_ENB generated in a control circuit (not shown) of the source driver 30.

At one end of the DAC drive switch DDSW 1, calculating the input voltage of the amplifier AMP 1 is supplied to the other end of the DAC drive switch DDSW 1, is connected to an output line electrically connected to the source line SL1 . The DAC drive switch DDSW 1 is on / off controlled (switch controlled) by a control signal DAC_ENB generated in a control circuit (not shown) of the source driver 30.

  When the number of switching signal lines is smaller than the number of gradation signal lines, as shown in FIG. 8, for the purpose of quickly stabilizing the input voltage of the operational amplifier AMP1, 32 switching signals are used. At least one of the signal lines may be driven by an operational amplifier (buffer circuit in a broad sense) connected in a voltage follower.

  In this case, since the voltage of the divided node of the resistor circuit is supplied as it is to the gradation signal line, the voltage of the gradation signal line can be set with high accuracy. Since the voltage of the switching signal line is driven by the operational amplifier, the voltage of the switching signal line can be set at a high speed, and the number of operational amplifiers can be reduced compared to the case where the operational amplifier is provided for each gradation signal line. It is possible to suppress a significant increase in layout area.

  7 and 8 show only the portion for driving the source line SL1, the same applies to the portion for driving the source lines SL2 to SLN.

7 and 8, the first and second DAC output switches DSWA 1 and DSWB 1 have been described as being included in the output circuit OUT 1 , but the present embodiment is not limited to this. The first and second DAC output switches DSWA 1 and DSWB 1 may be included in the first or second DAC 58A and 58B, for example.

  FIG. 9 shows an example of the timing of various control signals in FIG.

  In the present embodiment, a buffer output period is provided in the first half of the drive period within one horizontal scanning period, and a DAC output period is provided in the second half of the drive period. A control circuit (not shown) controls the control signal OPAMP_ENB to be H level during the buffer output period and the control signal DAC_ENB to be H level during the DAC output period. The control signals OPAMP_ENB and DAC_ENB do not become H level at the same time.

Thus, the buffer output period, the operational amplifier AMP 1 drives the source lines SL1, the DAC output period, the input voltage of the operational amplifier AMP 1 is supplied to the source line SL1. That is, within one horizontal scanning period, the source line is driven by the operational amplifier AMP 1 during the buffer output period, and the input voltage of the operational amplifier AMP 1 is supplied to the source line during the DAC output period after the buffer output period.

As a result, the voltage of the source line SL1 is set early in the buffer output period. At this time, an offset or the like of the operational amplifier AMP 1, the accuracy of the voltage level of the source line SL1 is not as high as the accuracy of the voltage level of the first gray-scale voltage generating circuit generated gray voltage 56A. Therefore, in the DAC output period, the gradation voltage generated by the DAC 58 is set to the source line SL1 as it is. Thereby, the voltage of the source line SL1 can be set with high accuracy in the DAC output period.

In the present embodiment, as the input voltage of the source line driver circuit 60 (operational amplifier AMP 1 ), the grayscale voltage from the second DAC 58B is once supplied, and then the grayscale voltage from the first DAC 58A is supplied. To do. That is, the source line driving circuit 60 drives the source line based on the output of the first DAC 58A after driving the source line based on the output of the second DAC 58B within one horizontal scanning period.

  Therefore, a control circuit (not shown) first sets the control signal DACB_ENB to H level during the driving period within one horizontal scanning period, and then sets the control signal DACA_ENB to H level. The control signals DACA_ENB and DACB_ENB do not become H level at the same time.

More specifically, the control circuit generates the control signals OPAMP_ENB and DACB_ENB so that the buffer output period overlaps with the period in which the source line driver circuit 60 drives the source line SL1 based on the output of the second DAC 58B. To do. Thereby, in the buffer output period, since the operational amplifier AMP 1 drives the source line based on the output voltage of the second DAC 58B, the voltage of the source line can be stabilized at an early voltage level with coarse accuracy. .

  Further, the control circuit generates the control signals DAC_ENB and DACA_ENB so that the DAC output period starts after the start timing of the period in which the source line driver circuit 60 drives the source line SL1 based on the output of the first DAC 58A. To do. Thereby, in the DAC output period, the gradation voltage from the first DAC 58A is supplied to the source line SL1, and the voltage of the source line can be set with a highly accurate voltage level.

  As described above, according to the present embodiment, the grayscale voltage from the second DAC 58B is once supplied as the input voltage of the source line driving circuit 60, and then the grayscale voltage from the first DAC 58A is supplied. As a result, voltage fluctuations of the source line driven by the source line driving circuit 60 can be suppressed.

The configuration of the present embodiment is not limited to the configuration of FIG. 9, and may be a configuration in which the DAC drive switch DDSW 1 is omitted.

  FIG. 10 is an explanatory diagram of this embodiment.

FIG. 10 schematically shows a main part of FIG. 7 or FIG. 8, and the same parts as those of FIG. 7 or FIG. In FIG. 10, it is assumed that the first and second DAC output switches DSWA 1 and DSWB 1 are provided outside the output circuit OUT 1 for convenience of explanation.

In FIG. 10, the voltage of one gradation signal line selected by the first DAC 58A based on the gradation data is selected by the second DAC 58B based on the gradation voltage V A and the upper bit data of the gradation data. one voltage switching signal lines is assumed to be gray-scale voltage V B. The parasitic capacitance of the gradation signal line to which the gradation voltage V A is supplied is C A , and the parasitic capacitance of the switching signal line to which the gradation voltage V B is supplied is C B, and the output of the source line driver circuit 60 Let C 1 be the parasitic capacitance of the input node of the circuit OUT 1 (operational amplifier AMP 1 ).

Here, it is assumed that the drive voltage of the source line SL1 in the horizontal scanning period immediately before the horizontal scanning period is V1. As a comparative example of this embodiment, in the horizontal scanning period, simply, when driving a source line in the selected voltage by the first DAC58A, it changes the voltage of the input node of the output circuit OUT 1 from V1 to V A To do. That is, in this comparative example, charge and discharge corresponding to (V1−V A ) are performed. At this time, when this voltage change has a large amplitude due to polarity inversion driving or the like, a large amount of charge is charged and discharged between the input node and the gradation signal line, and the voltage level of the input node and the gradation signal line is increased. The situation that does not converge immediately occurs.

On the other hand, in the present embodiment, this voltage level variation is absorbed by the switching signal line connected to the second DAC 58B. Thereafter, charge and discharge between the grayscale signal line connected to the first DAC 58A and the input node of the output circuit OUT 1 is performed, so that the charge charge and discharge amount can be significantly reduced as compared with the above case. As a result, the voltage levels of the input node and the gradation signal line can be immediately converged.

That is, first, when a gradation voltage of the second DAC58B is supplied to the input node of the output circuit OUT 1, charge and discharge of electric charges between the parasitic capacitance C 1, C B is performed.

Thereafter, when a gradation voltage of the first DAC58A is supplied to the input node of the output circuit OUT 1, charge and discharge of electric charges between the parasitic capacitance C 1, C A is performed. At this time, charges corresponding to the voltage V B close to the voltage V A are accumulated in the parasitic capacitance C 1 . Therefore, only a small discharge of the charge when the gradation voltage of the first DAC58A is supplied to the input node of the output circuit OUT 1.

Further, in the present embodiment, as shown in FIG. 9, one switching signal line (by the second DAC 58B) in the period t B in which the source line driving circuit 60 drives the source line based on the output of the second DAC 58B. The impedance of one selected switching signal line) is Z B , and one gradation signal line (first line) in the period t A in which the source line driving circuit 60 drives the source line based on the output of the first DAC 58A. When the impedance of one gradation signal line selected by one DAC 58A is Z A , a control circuit (not shown) controls the control signal DACA_ENB, so that t A / t B becomes Z A / Z B , It is desirable to generate DACB_ENB.

  Here, the impedance of the switching signal line corresponds to the sum of the resistance component of the switching signal line itself and the on-resistance component of the switch element of the second DAC 58B. The impedance of the gradation signal line corresponds to the sum of the resistance component of the gradation signal line itself and the on-resistance component of the switch element of the first DAC 58A.

The voltage at the input node of the output circuit OUT 1 gradually changes according to a time constant determined by the capacitance component and the resistance component from the gradation voltage generation circuit. Since the capacitance component is mainly determined by the input capacitance of the output circuit OUT 1 , the difference in time constant in the periods t A and t B is caused by the difference in impedances Z A and Z B. Therefore, by generating the control signals DACA_ENB and DACB_ENB as described above, the control signal DACA_ENB can be set to H level for as long as possible without wastefully setting the control signal DACB_ENB to H level. As a result, it is possible to apply the gradation voltage to the input node of the output circuit OUT 1 with high accuracy.

Next, the first and second DAC58A in FIGS. 7 and 8, 58B, exemplary configuration of the operational amplifier AMP 1 is described.

1.2.1 First DAC
FIG. 11 shows a block diagram of a configuration example of the voltage selection circuit DEC 1 A of the first DAC 58A of FIG. 7 or FIG.

In Figure 11, but illustrating a configuration example of the voltage selection circuit DEC 1 A of the voltage select circuit DEC 1 A~DEC N A, similar to other voltage selecting circuit DEC 2 A~DEC N A the voltage selection circuit DEC 1 A It has the composition of.

The voltage selection circuit DEC 1 A has a plurality of voltage selection blocks (128 voltage selection blocks). Each voltage selection block in FIG. 11 has the same configuration. Voltages VDD, VNL, VSSH, VPH, VDDH, data D7 to D1, and inverted data XD7 to XD1, XDA, and XDB are input to the plurality of voltage selection blocks. The inverted data XD7 to XD1 are data obtained by inverting the 7-bit data D7 to D1 excluding the least significant bit among the upper 8 bits of the gradation data. The inversion data XDA becomes H level when the least significant bit data D0 of the gradation data is “1”. The inversion data XDB becomes H level when the least significant bit data D0 of the gradation data is “0”.

  For example, data D7 to D1 are input to the voltage selection block that selects one voltage from the gradation voltages V0A and V1A, and the voltage selection block that selects one voltage from the gradation voltages V2A and V3A. Are inputted with data D7 to D2, inverted data D1,..., Inverted data XD7 to XD1 are inputted to a voltage selection block for selecting one voltage from gradation voltages V254A and V255A.

  In addition, two adjacent gradation voltages among the gradation voltages V0A to V255A are sequentially input to each voltage selection block. Each voltage selection block outputs a voltage SELA from two kinds of gradation voltages.

  FIG. 12 shows an outline of the configuration of the voltage selection block of FIG.

  The voltage selection block 200A includes a decoder 210A, a level shifter 220A, and a selector 230A. The decoder 210A generates a switch control signal based on the inverted data xd7 to xd1, xda, xdb. This switch control signal is converted into a voltage level between the voltage VDDH and the voltage VSSH by the level shifter 220A. The selector 230A outputs the voltage SELA from the voltages GRADA and GRADB based on the switch control signal level-converted by the level shifter 220A.

  FIG. 13 shows a circuit diagram of a configuration example of the voltage selection block of FIG.

  The decoder 210A has two sets of decoder circuits in which eight p-type (first conductivity type) metal oxide semiconductor (hereinafter, MOS) transistors are connected in series. A voltage VDD is supplied to one end of each decoder circuit. An n-type (second conductivity type) MOS transistor is connected to the other end of each decoder circuit. Xd7 to xd1 and xda are supplied to the gate of the p-type MOS transistor of one decoder circuit, and the voltage VNL is supplied to the gate of the n-type MOS transistor. Xd7 to xd1 and xdb are supplied to the gate of the p-type MOS transistor of the other decoder circuit, and the voltage VNL is supplied to the gate of the n-type MOS transistor.

  The voltage VNL is higher than the threshold voltage of the n-type MOS transistor. By generating the drain current of the n-type MOS transistor by this voltage VNL, when all of xd7 to xd1 and xda are at the L level, or when all of xd7 to xd1 and xdb are at the L level, the p-type connected in series A constant current is generated between the source and drain of each of the MOS transistors, and an H level signal can be output to the level shifter 220A.

  The level shifter 220A is a two-element level shifter. Further, the level shifter 220A has a p-type MOS transistor whose gate is supplied with a voltage VPH. The voltage VPH is a voltage having a low potential by at least the threshold voltage of the p-type MOS transistor with respect to the voltage VDD, and is a voltage set so that a drain current which is a constant current is generated in the p-type MOS transistor. is there. Thus, when the n-type MOS transistor constituting the level shifter 220A is turned on, the output of the level shifter 220A is set to the H level, and when the n-type MOS transistor is turned off, the output of the level shifter 220A is set to the L level. it can.

  The selector 230A outputs one of the voltages GRADA and GRADB as the voltage SELA based on the output of the level shifter 220A.

1.2.2 Second DAC
FIG. 14 shows a block diagram of a configuration example of the voltage selection circuit DEC 1 B of the second DAC 58B of FIG. 7 or FIG.

In Figure 14, but illustrating a configuration example of the voltage selection circuit DEC 1 B of the voltage select circuit DEC 1 B~DEC N B, as with the other of the voltage selection circuit DEC 2 B~DEC N B the voltage selection circuit DEC 1 B It has the composition of.

The voltage selection circuit DEC 1 B has a plurality of voltage selection blocks (16 voltage selection blocks). Each voltage selection block in FIG. 14 has the same configuration. Voltages VDD, VNL, VSSH, VPH, VDDH, data D7 to D4, and inverted data XD7 to XD4, XDA, and XDB are input to the plurality of voltage selection blocks. The inverted data XD7 to XD4 are data obtained by inverting the 4-bit data D7 to D4 excluding the least significant bit among the upper 5 bits of the gradation data. The inverted data XDA is at the H level when the least significant bit data D3 of the upper 5 bits of the gradation data is “1”. The inverted data XDB is at the H level when the least significant bit data D3 of the upper 5 bits of the gradation data is “0”.

  For example, data D7 to D4 are input to the voltage selection block that selects one voltage from the gradation voltages V0B and V1B, and the voltage selection block that selects one voltage from the gradation voltages V2B and V3B. The data D7 to D5 and the inverted data XD4 are inputted, and the inverted data XD7 to XD4 are inputted to the voltage selection block for selecting one voltage from the gradation voltages V30B and V31B.

  In addition, two adjacent gradation voltages among the gradation voltages V0B to V31B are sequentially input to each voltage selection block. Each voltage selection block outputs a voltage SELA from two kinds of gradation voltages.

  FIG. 15 shows an outline of the configuration of the voltage selection block of FIG.

  The voltage selection block 200B includes a decoder 210B, a level shifter 220B, and a selector 230B. The decoder 210B generates a switch control signal based on the inverted data xd7 to xd4, xda, xdb. This switch control signal is converted into a voltage level between the voltage VDDH and the voltage VSSH by the level shifter 220B. The selector 230B outputs the voltage SELA from the voltages GRADA and GRADB based on the switch control signal whose level has been converted by the level shifter 220B.

  FIG. 16 shows a circuit diagram of a configuration example of the voltage selection block of FIG.

  The decoder 210B has two sets of decoder circuits in which eight p-type MOS transistors are connected in series. A voltage VDD is supplied to one end of each decoder circuit. An n-type MOS transistor is connected to the other end of each decoder circuit. Xd7 to xd4 and xda are supplied to the gate of the p-type MOS transistor of one decoder circuit, and the voltage VNL is supplied to the gate of the n-type MOS transistor. Xd7 to xd4 and xdb are supplied to the gate of the p-type MOS transistor of the other decoder circuit, and the voltage VNL is supplied to the gate of the n-type MOS transistor.

  The voltage VNL is higher than the threshold voltage of the n-type MOS transistor. By generating the drain current of the n-type MOS transistor by this voltage VNL, when all of xd7 to xd4 and xda are at the L level, or when all of xd7 to xd4 and xdb are at the L level, the p-type connected in series A constant current is generated between the source and drain of each of the MOS transistors, and an H level signal can be output to the level shifter 220B.

  The level shifter 220B is a two-element level shifter. Further, the level shifter 220B has a p-type MOS transistor whose gate is supplied with a voltage VPH. The voltage VPH is a voltage having a low potential by at least the threshold voltage of the p-type MOS transistor with respect to the voltage VDD, and is a voltage set so that a drain current which is a constant current is generated in the p-type MOS transistor. is there. Thus, the output of the level shifter 220B is set to the H level when the n-type MOS transistor constituting the level shifter 220B is turned on, and the output of the level shifter 220B is set to the L level when the n-type MOS transistor is turned off. it can.

  The selector 230B outputs either the voltage GRADA or GRADB as the voltage SELA based on the output of the level shifter 220B.

When the selector 230A in FIG. 13 is compared with the selector 230B in FIG. 16, the size of the transistor constituting the selector 230B in FIG. 16 can be made larger than the size of the transistor constituting the selector 230A in FIG. This is because the number of switching signal lines is smaller than the number of gradation signal lines, and thus the increase in the size of the selector 230B has a small effect on the increase in the overall layout area. Therefore, as compared with the ability of the first DAC58A drives the gradation signal lines shown in FIGS. 11 to 13, higher ability second DAC58B to drive each switch signal lines shown in FIGS. 14 to 16 it can. Thereby, the potential of the switching signal line can be set at high speed without increasing the layout area so much.

1.2.3 Operational Amplifier Next, the configuration of the operational amplifier AMP 1 as a buffer circuit in the present embodiment will be described.

FIG. 17 shows a circuit diagram of a configuration example of the operational amplifier AMP 1 connected to the voltage follower of FIG.

Although FIG. 17 shows a configuration example of the operational amplifier AMP 1 of the output circuit OUT 1 , operational amplifiers of the other output circuits OUT 2 to OUT N have the same configuration.

The operational amplifier AMP 1 includes a differential unit DIF 1 and a drive unit DRV 1 . The differential unit DIF 1 includes first and second differential amplifiers pDIF 1 and nDIF 1 . Each differential amplifier has a differential transistor pair.

The differential transistor pair of the first differential amplifier pDIF 1 is composed of a p-type MOS transistor. The source of the differential transistor pair is connected to a current source transistor to which the reference voltage VREFP is supplied to the gate, and the gate of each MOS transistor constituting the differential transistor pair is configured by an n-type MOS transistor. A current mirror circuit is connected. The DAC output voltage DACOUT, which is the output voltage of the first or second DAC 58A, 58B, is supplied to the gate of one of the MOS transistors constituting the differential transistor pair, and the differential amplifier AMP is supplied to the gate of the other MOS transistor. 1 output voltage is supplied.

The differential transistor pair of the second differential amplifier nDIF 1 is composed of an n-type MOS transistor. A current source transistor to which a reference voltage VREFN is supplied to the gate is connected to the source of the differential transistor pair, and a gate of each MOS transistor constituting the differential transistor pair is configured by a p-type MOS transistor. A current mirror circuit is connected. The DAC output voltage DACOUT, which is the output voltage of the first or second DAC 58A, 58B, is supplied to the gate of one of the MOS transistors constituting the differential transistor pair, and the differential amplifier AMP is supplied to the gate of the other MOS transistor. 1 output voltage is supplied.

The drive unit DRV 1 includes a p-type drive transistor and an n-type drive transistor provided in series between the high potential side power supply voltage AVDDH and the low potential side power supply voltage AVSS. The output voltage of the second differential amplifier nDIF 1 is supplied to the gate of the p-type drive transistor. The output voltage of the first differential amplifier pDIF 1 is supplied to the gate of the n-type drive transistor.

1.2.4 Operation explanatory diagram Next, the operation in the present embodiment will be described.

  First, before describing the operation in the present embodiment, the operation in the comparative example of the present embodiment will be described. In this comparative example, as described above, the source line is simply driven with the voltage selected by the first DAC 58A at the gradation voltage switching timing.

  FIG. 18 shows a timing chart of an example of the operation in the comparative example of the present embodiment.

In Figure 18, 1 horizontal scanning period every grayscale data D [7: 0] are those changes, change in the potential level of the source lines SL1, change in the potential level of the output voltage of the operational amplifier AMP 1, DAC output voltage A change in the potential level of the DACOUT, a change in the potential level of the control signal DACA_ENB, DACB_ENB, DAC_ENB, OPAMP_ENB, the output voltage DACAOUT of the first DAC 58A, and a change in the potential level of the output voltage DACBOUT of the second DAC 58B are shown.

  In FIG. 18, for the purpose of comparison with the present embodiment, the control signal DACB_ENB is always set to the L level to realize the operation of this comparative example.

As shown in FIG. 18, the next horizontal scanning period is started before the potential level of the DAC output voltage DACOUT is stabilized at a desired potential level within one horizontal scanning period. Therefore, the output voltage of the operational amplifier AMP 1, the voltage of the source line SL1 greatly varies.

  FIG. 19 shows a timing chart of an example of the operation in this embodiment.

In Figure 19, similarly to FIG. 18, one horizontal scanning period every grayscale data D [7: 0] is intended to change, change in the potential level of the source line SL1, the potential level of the output voltage of the operational amplifier AMP 1 Change, potential level change of the DAC output voltage DACOUT, control signal DACA_ENB, DACB_ENB, DAC_ENB, OPAMP_ENB, change in potential level of the output voltage DACAOUT of the first DAC 58A, change in potential level of the output voltage DACBOUT of the second DAC 58B Indicates.

In FIG. 19, at the timings TG1 and TG2, the output of the second DAC 58B is switched to the output of the first DAC 58A. Stable to potential level. Therefore, the output voltage of the operational amplifier AMP 1, no voltage variation of the source line SL1, it is possible to achieve high gradation accuracy.

2. Electronic Device Next, an electronic device to which the liquid crystal device 10 (source driver 30) in the present embodiment is applied will be described.

2.1 Projection Display Device As an electronic apparatus configured using the liquid crystal device 10 described above, there is a projection display device.

  FIG. 20 shows a block diagram of a configuration example of a projection display device to which the liquid crystal device 10 according to the present embodiment is applied.

  The projection display device 700 includes a display information output source 710, a display information processing circuit 720, a display drive circuit 730 (display driver), a liquid crystal panel 740, a clock generation circuit 750, and a power supply circuit 760. The display information output source 710 includes a ROM (Read Only Memory) and a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs an image signal, and the like. Based on this, display information such as an image signal in a predetermined format is output to the display information processing circuit 720. The display information processing circuit 720 can include an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, and the like. The display driving circuit 730 includes a gate driver and a source driver, and drives the liquid crystal panel 740. The power supply circuit 760 supplies power to each circuit described above.

  FIG. 21 shows a schematic configuration diagram of a main part of the projection display device.

  The projection display device includes a light source 810, dichroic mirrors 813 and 814, reflection mirrors 815, 816 and 817, an incident lens 818, a relay lens 819, an exit lens 820, liquid crystal light modulators 822, 823 and 824, a cross dichroic prism 825, A projection lens 826 is included. The light source 810 includes a lamp 811 such as a metal halide and a reflector 812 that reflects the light of the lamp. The blue light / green light reflecting dichroic mirror 813 transmits red light of the light flux from the light source 810 and reflects blue light and green light. The transmitted red light is reflected by the reflection mirror 817 and is incident on the liquid crystal light modulation device 822 for red light. On the other hand, of the color light reflected by the dichroic mirror 813, green light is reflected by the dichroic mirror 814 that reflects green light and enters the liquid crystal light modulator 823 for green light. On the other hand, the blue light also passes through the second dichroic mirror 814. For blue light, in order to prevent light loss due to a long optical path, a light guide means 821 including a relay lens system including an incident lens 818, a relay lens 819, and an output lens 820 is provided, through which blue light is blue. The light enters the light liquid crystal light modulator 824. The three color lights modulated by the respective light modulation circuits are incident on the cross dichroic prism 825. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. These dielectric multilayer films combine the three color lights to form light representing a color image. As described above, the projection unit of the projection display apparatus is configured. The light synthesized by this projection means is projected onto the screen 827 by the projection lens 826 which is a projection optical system, and the image is enlarged and displayed.

2.2 Mobile Phone Another example of electronic equipment configured using the liquid crystal device 10 is a mobile phone.

  FIG. 22 is a block diagram showing a configuration example of a mobile phone to which the liquid crystal device 10 according to this embodiment is applied. In FIG. 22, the same parts as those in FIG. 1 or FIG.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies image data captured by the CCD camera to the display controller 38 in the YUV format.

  Mobile phone 900 includes LCD panel 20. The LCD panel 20 is driven by a source driver 30 and a gate driver 32. The LCD panel 20 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels.

  The display controller 38 is connected to the source driver 30 and the gate driver 32, and supplies gradation data in RGB format to the source driver 30.

  The power supply circuit 100 is connected to the source driver 30 and the gate driver 32 and supplies a driving power supply voltage to each driver. Further, the counter electrode voltage Vcom is supplied to the counter electrode of the LCD panel 20.

  The host 940 is connected to the display controller 38. The host 940 controls the display controller 38. The host 940 can supply the gradation data received via the antenna 960 to the display controller 38 after demodulating the modulation / demodulation unit 950. The display controller 38 displays on the LCD panel 20 by the source driver 30 and the gate driver 32 based on the gradation data.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the LCD panel 20 based on operation information from the operation input unit 970.

  In FIG. 22, it can be said that the host 940 or the display controller 38 is means for supplying gradation data.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

1 is a diagram illustrating an outline of a configuration of a liquid crystal device according to an embodiment. FIG. 5 is a diagram illustrating an outline of another configuration of the liquid crystal device according to the present embodiment. FIG. 3 is a block diagram of a configuration example of the gate driver in FIG. 1 or FIG. 2. FIG. 3 is a block diagram of a configuration example of the source driver in FIG. 1 or FIG. 2. FIG. 5 is a block diagram of a configuration example of a gradation voltage generation circuit, a DAC, and a source line driver circuit in FIG. 4. FIG. 6 is an operation explanatory diagram of the gradation voltage generation circuit of FIG. 5. The figure which shows the structure principal part per output of the source driver of FIG. FIG. 7 is a diagram illustrating another example of a configuration main part per output of the source driver in FIG. 6. The figure which shows an example of the timing of the various control signals of FIG. Explanatory drawing of this embodiment. FIG. 9 is a block diagram of a configuration example of a voltage selection circuit of the first DAC of FIG. 7 or FIG. 8. The figure which shows the outline | summary of a structure of the voltage selection block of FIG. FIG. 13 is a circuit diagram of a configuration example of the voltage selection block of FIG. 12. FIG. 9 is a block diagram of a configuration example of a voltage selection circuit of the second DAC of FIG. 7 or FIG. 8. The figure which shows the outline | summary of a structure of the voltage selection block of FIG. The circuit diagram of the structural example of the voltage selection block of FIG. FIG. 8 is a circuit diagram of a configuration example of an operational amplifier connected to the voltage follower in FIG. 7. The timing diagram of an example of the operation | movement in the comparative example of this embodiment. The timing diagram of an example of operation in this embodiment. 1 is a block diagram of a configuration example of a projection display device according to an embodiment. The schematic block diagram of the principal part of a projection type display apparatus. The block diagram of the structural example of the mobile telephone in this embodiment.

Explanation of symbols

10 liquid crystal device, 20 LCD panel, 30 source driver,
32 gate drivers, 38 display controllers, 50 I / O buffers,
52 display memory, 54 line latch, 56 gradation voltage generation circuit,
56A first gradation voltage generation circuit, 56B second gradation voltage generation circuit,
58 DAC, 58A first DAC, 58B second DAC,
60 source line drive circuit, 100 power supply circuit, AMP 1 operational amplifier,
BDSW 1 buffer drive switch,
DAC_ENB, DACA_ENB, DACB_ENB, OPAMP_ENB control signal,
DDSW 1 DAC drive switch,
DEC 1 A to DEC N A, DEC 1 B to DEC N B voltage selection circuit,
DSWA 1 first DAC output switch, DSWB 1 second DAC output switch,
GL1 to GLM gate lines, OUT 1 to OUT N output circuits,
SL1 to SLN source line

Claims (13)

  1. A source driver for driving a source line of an electro-optical device based on gradation data,
    P (P is a positive integer greater than or equal to 2) gradation signal lines, and P gradation signal lines to which the corresponding gradation voltage is supplied to each of the P gradation signal lines. When,
    Q (Q ≦ P, Q is a positive integer) switching signal lines, and Q switching signals are supplied with a corresponding gradation voltage to each of the Q switching signal lines. Lines and,
    A first DAC that outputs one gradation voltage among the P kinds of gradation voltages supplied to the P gradation signal lines based on the gradation data;
    A second DAC that outputs one gradation voltage among the Q kinds of gradation voltages supplied to the Q switching signal lines based on the gradation data;
    A source line driver having an output buffer for driving the source line based on the output of the first or second DAC;
    A first DAC output switch provided between an input of the source line driver and an output of the first DAC;
    A second DAC output switch provided between an input of the source line driver and an output of the second DAC;
    Including
    In the buffer output period within one horizontal scanning period,
    The second DAC output switch is turned on;
    The source line driving unit drives the source line by the output buffer to which an output voltage of the second DAC is input via the second DAC output switch;
    In a period after the buffer output period in one horizontal scanning period,
    The second DAC output switch is turned off, the first DAC output switch is turned on;
    The source line driving unit supplies an output voltage of the first DAC input via the first DAC output switch to the source line to drive the source line ;
    The first DAC has a plurality of first voltage selection blocks,
    The second DAC has a plurality of second voltage selection blocks,
    Two kinds of gradation voltages adjacent to each other among the P kinds of gradation voltages are inputted to each first voltage selection block of the plurality of first voltage selection blocks, and each of the first voltage selection blocks. Has a first selector for selecting one gradation voltage from the two kinds of gradation voltages,
    Two kinds of gradation voltages adjacent to each other among the Q kinds of gradation voltages are inputted to each of the second voltage selection blocks of the plurality of second voltage selection blocks, and each of the second voltage selection blocks. Has a second selector for selecting one gradation voltage from the two kinds of gradation voltages,
    A source driver , wherein a size of a transistor constituting the second selector is larger than a size of a transistor constituting the first selector .
  2. In claim 1 ,
    A DAC driving switch provided between the source line and the input of the source line driving unit;
    A control circuit for performing on / off control of the first DAC output switch, the second DAC output switch, and the DAC driving switch;
    In the buffer output period within one horizontal scanning period,
    The control circuit includes:
    The second DAC output switch is turned on, the source line is driven by the output buffer to which the output voltage of the second DAC is input through the second DAC output switch, and the second DAC is driven. After the output switch is turned off, the first DAC output switch is turned on, and the output buffer to which the output voltage of the first DAC is input via the first DAC output switch is used as the source. Controlling the first DAC output switch, the second DAC output switch so that a line is driven;
    In a period after the buffer output period in one horizontal scanning period,
    The control circuit includes:
    The first DAC output switch and the DAC drive switch are turned on, and the output voltage of the first DAC input through the first DAC output switch is supplied to the source line, and the source line A source driver, wherein the first DAC output switch and the DAC driving switch are controlled so as to be driven.
  3. In claim 1 or 2 ,
    The impedance of one switching signal line in the period tB in which the source line driving unit drives the source line based on the output of the second DAC is ZB, and the source line driving unit is the first DAC. When the impedance of one gradation signal line in the period tA for driving the source line based on the output is ZA,
    A source driver, wherein tA / tB is ZA / ZB.
  4. In any one of Claims 1 thru | or 3 ,
    P is 2K (K is an integer of 2 or more),
    A source driver characterized in that Q is 2K-L (K> L, L is a natural number).
  5. In any one of Claims 1 thru | or 4 ,
    A gradation voltage generating circuit for generating a plurality of gradation voltages obtained by resistance-dividing between two given voltages;
    The gradation voltage generated by the gradation voltage generation circuit is supplied to each gradation signal line,
    At least one of the switching signal lines is driven by a buffer circuit.
  6. Multiple gate lines,
    Multiple source lines,
    Each pixel is a plurality of pixels specified by each gate line and each source line;
    Electro-optical device which comprises a source driver according to any one of claims 1 to 5 for driving the plurality of source lines.
  7. In claim 6 ,
    An electro-optical device comprising a gate driver for scanning the plurality of gate lines.
  8. Electro-optical device characterized in that it comprises a source driver according to any one of claims 1 to 5.
  9. The electro-optical device according to any one of claims 6 to 8 ,
    A light source for entering light into the electro-optical device;
    And a projection means for projecting light emitted from the electro-optical device.
  10. Projection display device which comprises a source driver according to any one of claims 1 to 5.
  11. An electronic apparatus comprising the electro-optical device according to claim 6 .
  12. The electro-optical device according to any one of claims 6 to 8 ,
    Means for supplying gradation data to the electro-optical device.
  13. An electronic apparatus comprising a source driver according to any one of claims 1 to 5.
JP2007327196A 2007-02-23 2007-12-19 Source driver, electro-optical device, projection display device, and electronic device Active JP5374867B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007043309 2007-02-23
JP2007043309 2007-02-23
JP2007327196A JP5374867B2 (en) 2007-02-23 2007-12-19 Source driver, electro-optical device, projection display device, and electronic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007327196A JP5374867B2 (en) 2007-02-23 2007-12-19 Source driver, electro-optical device, projection display device, and electronic device
US12/071,374 US8427415B2 (en) 2007-02-23 2008-02-20 Source driver, electro-optical device, projection-type display device, and electronic instrument

Publications (2)

Publication Number Publication Date
JP2008233863A JP2008233863A (en) 2008-10-02
JP5374867B2 true JP5374867B2 (en) 2013-12-25

Family

ID=39906667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007327196A Active JP5374867B2 (en) 2007-02-23 2007-12-19 Source driver, electro-optical device, projection display device, and electronic device

Country Status (1)

Country Link
JP (1) JP5374867B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5363895B2 (en) * 2009-07-23 2013-12-11 ルネサスエレクトロニクス株式会社 Signal line driving circuit and liquid crystal display device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3276725B2 (en) * 1992-10-07 2002-04-22 株式会社日立製作所 The liquid crystal display device
JP3108293B2 (en) * 1994-11-28 2000-11-13 三洋電機株式会社 The liquid crystal driving circuit
JP2001166741A (en) * 1999-12-06 2001-06-22 Hitachi Device Eng Co Ltd Semiconductor integrated circuit device and liquid crystal display device
GB2362277A (en) * 2000-05-09 2001-11-14 Sharp Kk Digital-to-analog converter and active matrix liquid crystal display
JP2002014644A (en) * 2000-06-29 2002-01-18 Hitachi Ltd Picture display device
JP4437378B2 (en) * 2001-06-07 2010-03-24 株式会社日立製作所 Liquid crystal drive device
JP4372392B2 (en) * 2001-11-30 2009-11-25 ティーピーオー ホンコン ホールディング リミテッド Column electrode drive circuit and display device using the same
JP3661650B2 (en) * 2002-02-08 2005-06-15 セイコーエプソン株式会社 Reference voltage generating circuit, a display drive circuit and a display device
JP3661651B2 (en) * 2002-02-08 2005-06-15 セイコーエプソン株式会社 Reference voltage generating circuit, a display drive circuit and a display device
JP2003241716A (en) * 2002-02-14 2003-08-29 Fujitsu Ltd Circuit for driving liquid crystal display panel
JP4082398B2 (en) * 2004-09-07 2008-04-30 セイコーエプソン株式会社 Source driver, electro-optical device, electronic apparatus, and driving method
KR100745339B1 (en) * 2005-11-30 2007-08-02 삼성에스디아이 주식회사 Data Driver and Driving Method of Organic Light Emitting Display Using the same

Also Published As

Publication number Publication date
JP2008233863A (en) 2008-10-02

Similar Documents

Publication Publication Date Title
KR100536871B1 (en) Display driving device and display using the same
US7477227B2 (en) Method and driving circuit for driving liquid crystal display, and portable electronic device
US6873312B2 (en) Liquid crystal display apparatus, driving method therefor, and display system
US7079127B2 (en) Reference voltage generation circuit, display driver circuit, display device, and method of generating reference voltage
US8044902B2 (en) Method of driving a color liquid crystal display and driver circuit for driving the display as well as portable electronic device with the driver circuit
DE60313066T2 (en) Reference voltage circuit
US7656419B2 (en) Drive circuit for display apparatus and display apparatus
US6909413B2 (en) Display device
US7102610B2 (en) Display system with frame buffer and power saving sequence
JP3661650B2 (en) Reference voltage generating circuit, a display drive circuit and a display device
US6778163B2 (en) Liquid crystal display device, driving circuit, driving method, and electronic apparatus
US6784898B2 (en) Mixed mode grayscale method for display system
US6943766B2 (en) Display apparatus, display system and method of driving apparatus
US7298352B2 (en) Apparatus and method for correcting gamma voltage and video data in liquid crystal display
KR100532722B1 (en) Display driver circuit, display panel, display device, and display drive method
KR100642112B1 (en) Grayscale voltage generation circuit, driver circuit, and electro-optical device
JP3687648B2 (en) Power supply method and a power supply circuit
EP1335344B1 (en) Reference voltage generation method and circuit, display drive circuit and display device with gamma correction and reduced power consumption
US7812805B2 (en) Driver circuit and display device
KR101037554B1 (en) Active matrix display device and driving method of the same
US7864170B2 (en) Liquid crystal display device, method of controlling the same, and mobile terminal
JP4887657B2 (en) Active matrix display device and driving method thereof
EP0767449B1 (en) Method and circuit for driving active matrix liquid crystal panel with control of the average driving voltage
US8111227B2 (en) Liquid crystal display system capable of improving display quality and method for driving the same
KR100478577B1 (en) Driver circuit of electro-optical device, driving method, D/A converter, signal driver, electro-optical panel, projection display, and electronic device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20101217

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120717

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120807

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121009

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130604

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130731

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130827

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130909

R150 Certificate of patent or registration of utility model

Ref document number: 5374867

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250