JP3108293B2 - LCD drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving circuit having a bias voltage supply circuit for driving a liquid crystal.

[0002]

2. Description of the Related Art Generally, a liquid crystal driving circuit having a built-in bias voltage generating circuit is constituted by a circuit as shown in FIG. 2, and this figure shows a case of a 1/3 duty and 1/3 bias system. ing. 2, reference numeral 1 denotes a clock input terminal for inputting a clock signal CL sent from a system controller such as a microcomputer (not shown), 2 denotes a data input terminal for inputting display data DI sent as serial data from the system controller, and 3 denotes a data input terminal. The display data input to the data input terminal 2 is transmitted to the clock input terminal 1
, A latch circuit for latching the contents of the shift register 3 by a latch pulse L from a latch signal generation circuit 5, 6 a segment driver output waveform control circuit 7 and a segment driver output. A segment driver which comprises a waveform generation circuit 8 and supplies output waveforms from output terminals 9a, 9b,..., 9n to segments of the liquid crystal panel;
Reference numeral 10 denotes a common driver output waveform control circuit 11 and a common driver output waveform generation circuit 12, and an output terminal 13
The common driver supplies an output waveform from a, 13b, and 13c to the common of the liquid crystal panel. Reference numeral 15 denotes a resistance dividing circuit including three resistors having the same resistance value R1, and includes three levels of bias voltages V1 (= VDD) and V
2, a bias voltage generating circuit for supplying the segment driver 6 and the common driver 10 with V3 and the ground voltage VSS.

Therefore, when display data and a clock signal are sent from the system controller, the display data is latched in the shift register 3 in synchronization with the clock, and when the latch is completed, the display data is latched by the latch pulse L. Latched by circuit 4. The latched display data is applied to the segment driver output waveform control circuit 7 of the segment driver 6 every three bits. Here, four segment drivers corresponding to the display data are synchronized with a timing signal generated from the timing generation circuit 14. An output waveform control signal is generated.

The lines 151, 152, 153 and 154 for supplying the bias voltages V1, V2 and V3 and the ground voltage VSS of the bias voltage generating circuit 15 are connected to the respective segment output terminals 9a and 9a via four transmission gates 8. 9b,..., 9n. The four segment driver output waveform control signals from each segment driver output waveform control circuit 7 control the opening and closing of these four transmission gates 8 to produce segment driver output waveforms. Is formed. The segment driver output waveform is output to output terminals 9a, 9b,.
n and applied to the liquid crystal panel.

On the other hand, in the common driver 10, each common driver output waveform control circuit 11 generates four common driver output waveform control signals in synchronization with a timing signal generated from the timing generation circuit 14. Bias voltages V1 and V of bias voltage generation circuit 15
2, V3 and the line 15 for supplying the ground voltage VSS, respectively.
1, 152, 153 and 154 are segment drivers 6
As in the case of the above, each of the common output terminals 13a, 13b, 13 via four transmission gates 12
The common driver output waveform is formed by controlling the opening and closing of the four transmission gates 12 by four common driver output waveform control signals from each common driver output waveform control circuit 11. The output waveform of the common driver is output to the output terminals 13a and 13a.
Output from 13b and 13c is applied to the liquid crystal panel.

By the above operation, three common driver output waveforms COM1 and CO3 as shown in FIGS.
M2, COM3 and the segment driver output waveform Sn are formed. As the segment driver output waveform, only a waveform corresponding to the common driver output waveform COM1 is shown. By the way, the segment output terminals 9a,
9b,..., 9n and common output terminals 13a, 13
When the load on the liquid crystal panel connected to b and 13c is large, the amount of current supplied from these output terminals to the liquid crystal panel increases. In such a case, if the resistance value R1 of the bias generation circuit 15 is large, the common and segment output waveforms are distorted, leading to early deterioration of the liquid crystal panel and deterioration of display quality.

Therefore, conventionally, the resistance value R1 of the bias generation circuit 15 has been set to a small value so that the life and display quality can be guaranteed for all of the liquid crystal panels having a small load to the liquid crystal panels having a large load. Also IC
As shown in FIG. 3, in the built-in bias voltage generating circuit 16, the resistance value R2 of the resistance dividing circuit is set to be large, and the resistance value of the small resistance value R3 is provided outside the IC. An external bias voltage generating circuit 17 composed of a divided circuit can be connected in parallel with the bias voltage generating circuit 16, and in the case of a liquid crystal panel having a large load, the external bias voltage generating circuit 17 is used. There were also things.

[0008]

In the circuit shown in FIG.
Since the resistance value R1 of the bias voltage generating circuit 15 is set to be small, the current consumption increases. Therefore, when driving a liquid crystal panel with a small load, there is a problem that a useless current is consumed. . In addition, the circuit of FIG. 3 requires an external resistor according to the liquid crystal panel to be used, so that the number of external components increases, and even when the IC stops operating, the external resistor is required. However, the current was consumed, and it was not suitable for reducing the current.

[0009]

SUMMARY OF THE INVENTION The present invention provides a timing generation circuit for generating a timing signal for display control, a segment driver for forming a segment driver output waveform based on display data and the timing signal, and A common driver for forming a common driver output waveform in response to the bias voltage for driving the liquid crystal to the segment driver and the common driver, a plurality of bias voltage generating circuits having different current supply amounts, and selecting data. The above object is achieved by configuring a liquid crystal drive circuit including a selection circuit for selecting any one of the plurality of bias voltage generation circuits in response.

Further, the present invention is characterized by further comprising a shift register for inputting the display data and the selection data, and a latch circuit for latching the contents of the shift register. Further, in the present invention, the display data is input as serial data, and the selection data is data input as a series of serial data with the display data.

[0011]

In the present invention, a bias voltage generating circuit with a small current supply is used for a liquid crystal panel with a small load only by inputting selection data, and a current supply with a small amount is supplied for a liquid crystal panel with a large load. A large bias voltage generation circuit can be used. Further, since the selection data is display data and a series of serial data, the data input terminal can also be used as the display data, and the circuit configuration such as the shift register and the latch circuit can be handled only by increasing the number of bits.

[0012]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. All the components shown are incorporated in an LSI. 2 and 3 are denoted by the same reference numerals. Here, a 1-bit selection data SD is sent out as a series of serial data from a system controller (not shown) immediately after the display data DI. For this reason, the shift register 21 and the latch circuit 22 use the conventional shift register. 3 and latch circuit 4
The configuration is such that the number of bits is larger by one bit. In the latch circuit 22, the latch 23 at the last bit position is a latch for the selected data.

The bias voltage generating circuit includes a first bias voltage generating circuit 34 in which the current supply amount is increased by setting the resistance value R4 of the resistance dividing circuit to a small value, and a resistance value R5 of the resistance dividing circuit. Is set to a large value to reduce the current supply amount, and a second bias voltage generating circuit 36 is provided. In each of the bias voltage generating circuits 34 and 36, first transmission gates 35a and 37a are provided between the power supply potential VDD and the first resistor.
The second transmission gates 35b and 37b are provided between the first voltage dividing point A and the output line 152, and the third transmission gates 35c and 37c are provided between the second voltage dividing point B and the output line 153. Each is inserted. Output line 1
Reference numerals 51 and 154 are directly connected to the power supply potentials VDD and VSS of the bias voltage generation circuit 34, respectively.

The output of the latch 23 is input to each transmission gate 35a, 35b, 35c of the first bias voltage generating circuit 34 as a control signal.
Each transmission gate of the bias voltage generation circuit 36
The inverted outputs of the latch 23 are input to the gates 37a, 37b, and 37c as control signals. Next, the operation of this embodiment will be described in detail.

Serial data consisting of display data and selection data is input to a data terminal 2 and a clock signal CL
Is input to the clock terminal 1, the shift register 21
The display data and the selection data are captured in synchronization with the clock. After the capture, when the latch signal L is applied, the display data and the selection data of the shift register 21 are latched by the latch circuit 22. Specifically, the selection data is latched by the latch 23 in the latch circuit 22.

If the selection data SD is "1", the inverted selection data of "0" is input to the second bias voltage generating circuit 36, so that the transmission gate 37 is provided.
b and 37c are turned off, the bias voltage is not supplied to the output lines 152 and 153, and the transmission gate 37a is turned off. Consumption will not occur.

On the other hand, in the bias voltage generating circuit 34, since the transmission gates 35a, 35b and 35c are all turned on, the bias voltages V2 and V3 are supplied from the bias voltage generating circuit 34 to the output lines 152 and 153, and Lines 151 and 154 have power supply voltages VDD and VSS
Is supplied. In the bias voltage generation circuit 34, since the resistance value R4 is small, a large amount of current is supplied to the segment and common drivers 6 and 10, and therefore, when a liquid crystal panel with a large load is connected, the output waveform is changed. Optimal driving can be performed without distortion. The operations of forming the segment and common output waveforms in the segment and common drivers 6 and 10 are as described in the conventional example.

When the selection data SD is "0",
Since all three transmission gates 35a, 35b, and 35c of the bias voltage generation circuit 34 are turned off, no bias voltage is supplied from here, and no current is consumed. However, the bias voltage generation circuit 36
Then, three transmission gates 37a, 37
b, 37c are all turned on, so that the output lines 152, 1
53 are supplied with bias voltages V2 and V3. In the bias voltage generating circuit 36, since the resistance value R5 is large, only a small amount of current is supplied to the segment and common drivers 6 and 10. Therefore, when a liquid crystal panel with a small load is connected, there is no waste. Optimal driving can be performed without consuming a large amount of current.

As described above, a bias voltage generating circuit having a current supply amount corresponding to the load of the liquid crystal panel to be connected can be selected according to the selection data. Next, a second embodiment will be described with reference to FIG. Here, the selection data SD is composed of two bits SD1 and SD2.
When both SD1 and SD2 are "1", the two bias voltage generating circuits 34 and 36 are selected together, and SD1 and SD2 are selected.
Is "1,0", only the bias voltage generation circuit 34 is selected, and when SD1 and SD2 are "0,1", only the bias voltage generation circuit 36 is selected.

That is, when the load of the liquid crystal panel to be connected is large, the two bias voltage generating circuits 34 and 36 are connected in parallel between the power supply voltages, so that the resistance value becomes smaller and a larger current is applied to the liquid crystal panel. It can be supplied to the panel. When the load of the liquid crystal panel to be connected is medium, an appropriate current can be supplied by the bias voltage generation circuit 34. When the load of the liquid crystal panel to be connected is small, useless current is consumed by the bias voltage generation circuit 36. Optimum driving can be performed without any problem.

In the embodiment described above, two bias voltage generating circuits are provided. However, the number may be increased as necessary, and the number of bits of the selected data may be increased accordingly. . Further, as a driving method, 1/3
Naturally, the present invention can be applied not only to the duty / 1/3 bias method but also to other methods.

[0022]

According to the present invention, an optimum amount of current can be supplied from the bias voltage generation circuit according to the load of the liquid crystal panel to be connected.
The service life and display quality of the liquid crystal panel can be guaranteed. In addition, since the selection data is display data and a series of serial data, an increase in the number of terminals can be suppressed, and the above effect can be obtained with only a slight circuit change.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

FIG. 3 is a block diagram showing a configuration of another conventional example.

FIG. 4 is a waveform diagram showing driver output waveforms of common and segment.

FIG. 5 is a block diagram showing a main part of another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Clock input terminal 2 Data input terminal 3, 21 Shift register 4, 22 Latch circuit 6 Segment driver 7 Segment driver output waveform control circuit 8 Segment driver output waveform generation circuit 9a, 9b, ..., 9n Segment output terminal 10 Common driver 11 common driver output waveform control circuit 12 common driver output waveform generation circuit 13a, 13b, 13c common output terminal 14 timing generation circuit 15, 16, 17, 34, 36 bias voltage generation circuit 35a, 35b, 35c transmission gate 37a, 37b, 37c transmission gate

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-88494 (JP, A) JP-A-6-214530 (JP, A) JP-A-2-79019 (JP, A) 2322 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/133 520 G02F 1/133 505 G09G 3/36

Claims (4)

(57) [Claims] 1. A timing generation circuit for generating a timing signal for display control, a segment driver for forming a segment driver output waveform based on display data and the timing signal, and a common driver output waveform in response to the timing signal A bias driver for driving a liquid crystal to the segment driver and the common driver, a plurality of bias voltage generating circuits having different current supply amounts, and the plurality of bias voltage generating circuits according to selection data. A liquid crystal drive circuit comprising: a selection circuit for selecting any one of the circuits. 2. A timing generating circuit for generating a timing signal for display control, a segment driver for forming a segment driver output waveform based on display data and the timing signal, and forming a common driver output waveform in response to the timing signal. A bias driver for driving a liquid crystal to the segment driver and the common driver, a plurality of bias voltage generating circuits having different current supply amounts, and the plurality of bias voltage generating circuits according to selection data. And a selection circuit for selecting one or more of the circuits. 3. The liquid crystal drive circuit according to claim 1, wherein
The liquid crystal driving circuit further comprises a shift register for inputting the display data and the selection data, and a latch circuit for latching the contents of the shift register. 4. The liquid crystal drive circuit according to claim 3, wherein the display data is input as serial data, and the selection data is data input as a series of serial data with the display data.