TWI386897B - Source driver, electro-optical device, and electronic instrument - Google Patents

Description

Source driver, optoelectronic device, and electronic device

The present invention relates to a source driver, an optoelectronic device, an electronic device, and the like.

A liquid crystal panel (optoelectronic device) used in an electronic device such as a mobile phone is known as a liquid crystal panel of a simple matrix type, and an active matrix method using a switching element such as a thin film transistor (hereinafter referred to as TFT). LCD panel.

The advantage of the simple matrix method is that it is easier to consume power than the active matrix method, and the disadvantage is that it is difficult to multicolor and display animation. In addition, the advantage of the active matrix method is that it is suitable for multi-colorization and animation display, and the disadvantage is that it is difficult to reduce power consumption.

In recent years, portable electronic devices such as mobile phones have increased the demand for multi-color and animated displays in order to provide high-quality images. Therefore, an active matrix type liquid crystal panel is used instead of the simple matrix type liquid crystal panel used in the past. In the active matrix type liquid crystal panel, the transmittance of the pixel is changed by writing a signal to the source line selected in the pixel selected via the gate line.

In recent years, as the screen size of the liquid crystal panel has increased and the number of pixels has increased, the number of source lines of the liquid crystal panel has increased, and it is required to impart high precision to the voltages of the respective source lines. Further, as the electronic device that requires the battery driving of the liquid crystal panel is required to be light and compact, it is also required to reduce the power consumption of the source driver for driving the source line of the liquid crystal panel and to reduce the size of the wafer of the source driver. Therefore, the source driver must be simple and highly functional.

As disclosed in Patent Document 1 and Patent Document 2, a rail-to-rail operation capable of driving an output circuit of a source line of a source driver can be performed, and a voltage to a source line can be supplied with high precision.

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2005-175811

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2005-175812

However, the techniques disclosed in Patent Document 1 and Patent Document 2 are such that each output circuit controls the driving capability by mounting an auxiliary circuit to realize the rail-to-rail operation. Therefore, it is necessary to mount an auxiliary circuit as an additional circuit, and the circuit scale of the source driver becomes large. Further, in order to suppress variations in the voltage applied to the source line, the size of the transistor is increased.

Furthermore, in order to supply the voltage to the source line with high precision, it is necessary to supply the voltage from the DAC which generates the gray scale voltage to the source line without correspondingly corresponding to the gray scale data. Therefore, when the number of gray scales is increased, the number of gray scale voltage signal lines must also be increased, and there is a problem that the wafer size becomes large.

In addition, general op amps need to consider variations in the output voltage. Therefore, it is necessary to increase the size of the transistors constituting the operational amplifier to suppress variations in the output voltage.

One aspect of the present invention provides a source driver, an optoelectronic device, and an electronic device that can supply a voltage to a source line with high accuracy by using a track-to-rail action.

In addition, the other aspects of the present invention provide a circuit with a small circuit scale, which can suppress fluctuations in output voltage, and supply voltage to the source driver of the source line with high precision. Photoelectric devices and electronic devices.

Furthermore, other aspects of the present invention provide a source driver, an optoelectronic device, and an electronic device that supply a voltage to a source line with high accuracy even when the number of gray levels is increased.

In order to solve the above problem, the source driver of the present invention is used to drive a source line of an optoelectronic device, and includes: a gray scale voltage generating circuit that outputs first and second gray scale voltages corresponding to gray scale data. Each of the gray scale voltages and the source line driving circuit drives the source lines according to the first and second gray scale voltages; the source line driving circuit includes a flip type sample and hold circuit, which is An output gray scale voltage between the first gray scale voltage and the aforementioned second gray scale voltage is output to the source line.

Here, the source driver may also output a voltage having the same potential as the first gray scale voltage, and may also output a voltage having the same potential as the second gray scale voltage as the output gray scale voltage.

According to the present invention, since the output gray scale voltage between the first and second gray scale voltages is generated by the flip type sample-and-hold circuit, the structure is very simple, and the output circuit can generate a complex gray scale voltage. As a result, the type of gray scale voltage to be generated can be greatly reduced. Thereby, the number of gray scale voltage signal lines can be deleted, and the circuit scale of the gray scale voltage generating circuit can be greatly reduced. In general, the gray scale voltage generating circuit needs to increase the size of the transistor in order to supply a high voltage, and the circuit scale of the gray scale voltage generating circuit is deleted, which greatly contributes to the source driving. The wafer size of the actuator is reduced.

Further, by the flip type sampling and holding circuit, the rail-to-rail operation can be performed without adding an auxiliary circuit or the like, and it is not necessary to increase the size of the transistor in order to suppress variations. Thus, it contributes to the reduction in the size of the wafer of the source driver.

Furthermore, according to the present invention, it is not necessary to output the gray scale voltage generated by the gray scale voltage generating circuit to the source line in order to set the gray scale voltage applied to the source line, and the structure of the gray scale voltage generating circuit can be miniaturized. Further, with the present invention, the gray scale voltage can be generated with high precision only by the output circuit. As a result, the structure of the gray scale voltage generating circuit can be simplified.

Further, in the source driver of the present invention, the flip-type sample-and-hold circuit includes: an operational amplifier circuit; and a plurality of capacitive elements connected to one end of the input of the operational amplifier circuit; during the sampling, electrically interrupting the foregoing And electrically connecting the input and the output of the operational amplifier circuit in an output of the operational amplifier circuit and the source line, and storing the charge corresponding to the first or second gray scale voltage in each of the capacitive elements of the plurality of capacitive components And electrically interrupting an input and an output of the operational amplifier circuit during a hold period after the sampling period, and supplying an output of the operational amplifier circuit obtained by outputting the charge stored in the complex capacitive element to an output of the operational amplifier circuit The voltage is output to the aforementioned source line.

Further, in the source driver of the present invention, The flip type sampling and holding circuit includes: an operational amplifier circuit that supplies a given voltage to the non-inverting input terminal; and a feedback switch that is inserted between the inverting input terminal of the operational amplifier circuit and the output of the operational amplifier circuit One end is connected to the first to jth (j is an integer of 2 or more) capacitive elements of the inverting input terminal; the first to jth inverting switches are p (1≦p≦j, p is an integer) a flip switch is inserted between the other end of the p-th capacitive element and an output of the operational amplifier circuit; a first to jth input switch, one end of the pth input switch is connected to the other end of the p-th capacitive element; An output switch inserted between the output of the operational amplifier circuit and the source line; the first or second gray scale voltage is supplied to the other end of each of the first to jth input switches; during sampling Supplying the first and second ash at the other end of the first to jth capacitive elements while disconnecting the first to jth inverting switches, turning on the feedback switch, and turning off the output switch Order voltage Any one of the first gray-scale voltages obtained by turning on the first to j-th flipping switches, turning off the feedback switch, and turning on the output switch, during the holding period after the sampling period. The output gray scale voltage between the aforementioned second gray scale voltages is output to the aforementioned source line.

According to any of the above inventions, since the charge stored in the plurality of capacitive elements is moved to the output side of the operational amplifier circuit, the input offset voltage of the operational amplifier circuit is not affected, and the output can be generated with high accuracy. Gray scale voltage. Further, according to the present invention, the first and second gray scale voltages can be supplied to the first to jth capacitive elements with a simple configuration.

Further, in the source driver of the present invention, when the output potential of the output gray scale voltage is lower than the lowest potential voltage of the voltage output to the source line, the gray scale voltage generating circuit follows the potential. Outputting the first and second gray scale voltages in a high order; when the output gray scale voltage is closer to the lowest potential voltage than the highest potential voltage, the gray scale voltage generating circuit may output the first and second in order of low potential Gray scale voltage.

Further, in the source driver of the present invention, when the output gray scale voltage is closer to the highest potential voltage than the lowest potential voltage, the gray scale voltage on the high potential side is supplied to the first one in the first and second gray scale voltages. In the state of any one of the capacitive elements of the jth capacitive element, the first to the jth input switches may be performed by supplying a gray scale voltage on the low potential side to any one of the first to jth capacitive elements. Switch control.

Further, in the source driver of the present invention, when the output gray scale voltage is closer to the lowest potential voltage than the highest potential voltage, the gray scale voltage on the low potential side is supplied to the first one in the first and second gray scale voltages. In the state of any one of the capacitive elements of the jth capacitive element, the first to the jth input switches may be performed by supplying a gray scale voltage on the high potential side to any one of the first to jth capacitive elements. Switch control.

According to any of the above inventions, since leakage of the first to jth inversion switches can be suppressed, it is possible to avoid a situation in which the voltage level of the output gray scale voltage fluctuates.

Further, in the source driver of the present invention, the capacitance values of the respective capacitance elements of the first to jth capacitive elements may be equal.

With the present invention, the output gray scale voltage between the first and second gray scale voltages can be accurately and easily generated.

Further, the source driver of the present invention may include an auxiliary capacitance element that supplies a predetermined voltage to one end and an inverting input terminal of the operational amplifier circuit to the other end.

According to the present invention, the voltage fluctuation of the inverting input terminal of the operational amplifier circuit can be suppressed, and the output gray scale voltage can be further stabilized.

Further, in the source driver of the present invention, the auxiliary capacitance element may also be used as a dummy capacitance element formed in the capacitance element formation region.

In addition, in the source driver of the present invention, each of the source driver blocks driving the source lines of the optoelectronic device includes a plurality of source driver blocks including the gray scale voltage generating circuit and the source line driving circuit. Each of the source driver blocks has a capacitive element forming region forming the first to jth capacitive elements and the auxiliary capacitive element in a direction crossing the arrangement direction of the plurality of source driver blocks; and the auxiliary capacitive element may be At the boundary of the aforementioned capacitive element forming region The middle portion is formed along a boundary opposite to a direction intersecting the arrangement direction.

According to the present invention, the capacitance values of the first to jth capacitive elements can be accurately formed, and the auxiliary capacitance element can be formed without wasting the layout area.

Further, in the source driver of the present invention, the operational amplifier circuit may perform an A-stage amplification operation during the sampling period, and perform an AB-stage amplification operation during the retention period.

Further, in the source driver of the present invention, the operational amplifier circuit may include: an operational amplifier that amplifies a difference value between an input of the operational amplifier circuit and an output of the operational amplifier circuit; and a first drive transistor of the first conductivity type And being disposed on the first power supply side, controlling the gate electrode according to the voltage of the output node of the operational amplifier; and the second driving transistor of the second conductivity type is disposed in series with the first driving transistor a second power supply side; a capacitor for capacitively coupling a gate electrode of the first driving transistor and a gate electrode of the second driving transistor; and a charge supply circuit for supplying a charge during the sampling period The gate electrode to the second driving transistor stops supplying electric charge to the gate electrode of the second driving transistor during the holding period.

Further, in the source driver of the present invention, the charge supply circuit includes: a current generating circuit; a switching circuit inserted between the current generating circuit and one of the capacitors and the gate electrode of the second driving transistor; the switching circuit can also be turned on during the sampling period and disconnected during the holding period Switch control.

Further, in the source driver of the present invention, the current generating circuit includes a current source transistor that supplies a current to the drain thereof and the diode is connected; the switching circuit may also be inserted into the gate electrode of the current source transistor and the capacitor. One end is between the gate electrode of the aforementioned second driving transistor.

Here, the general flip type sample-and-hold circuit has no change in output load regardless of the sampling period or the holding period. In the source driver of any of the above inventions, it is necessary to drive the load of the source line of the photovoltaic device during the holding period. Therefore, according to any of the above inventions, since the flip type sample-and-hold circuit drives the output of the low load during the sampling period and drives the output of the high load during the sustain period, the source driver can be provided with the optimum source line driving circuit. Without affecting the function of the flip-type sample-and-hold circuit, the circuit scale of the flip-type sample-and-hold circuit can be greatly reduced.

In addition, the photovoltaic device of the present invention comprises: a plurality of scan lines; a plurality of source lines; and a plurality of pixels, wherein the pixels are specified by respective scan lines of the plurality of scan lines and respective source lines of the plurality of source lines; Driving any of the above-described source drivers for the plurality of source lines.

According to the present invention, it is possible to provide an optoelectronic device including a source driver having a small circuit scale and capable of supplying a voltage to a source line with high accuracy by rail-to-rail operation. Further, according to the present invention, it is possible to provide an optoelectronic device including a source driver having a small circuit scale and omitting an input offset voltage, and supplying a voltage to a source line with high accuracy. Furthermore, with the present invention, it is possible to provide an optoelectronic device including a source driver capable of supplying a voltage to a source line with a high degree of accuracy of a few gray scale voltage signal lines even when the number of gray levels is increased.

Further, the electronic machine of the present invention includes any of the above-described source drivers.

Further, the electronic apparatus of the present invention comprises the above-described photovoltaic device.

According to any of the above inventions, it is possible to provide an electronic device which can set a gray scale voltage with high accuracy on a source line and is lightweight and miniaturized.

Hereinafter, embodiments of the present invention will be described in detail using the drawings. Further, the embodiments described below are not intended to unduly limit the scope of the invention described in the claims. Further, all the configurations described below are not limited to the essential constituent elements of the present invention.

1. Liquid crystal device

Fig. 1 shows an outline of the configuration of an active matrix type liquid crystal device of the present embodiment. Here, the active matrix type liquid crystal device will be described, but the display driver of the present embodiment can be applied to other liquid crystal devices.

The liquid crystal device 10 includes a liquid crystal display (LCD) panel (in a broad sense, a display panel, and more generally, an optoelectronic device) 20 . The LCD panel 20 is an amorphous germanium liquid crystal panel, for example, formed on a glass substrate. in The glass substrate is provided with gate lines (scanning lines) GL1 to GLM (M is an integer of 2 or more) which are arranged in the Y direction and extend in the X direction, and are arranged in the X direction and extend in the Y direction. Source line (data line) SL1~SLN (N is an integer of 2 or more). Further, a pixel region (pixel) is provided corresponding to the intersection of the gate line GLm (1≦m≦M, m is an integer, the same applies hereinafter) and the source line SLn (1≦n≦N, n is an integer, the same below). A thin film transistor (hereinafter referred to as TFT) 22 mn is disposed in the pixel region.

The gate of the TFT 22 mn is connected to the gate line GLm. The source of the TFT 22 mn is connected to the source line SLn. The drain of the TFT 22 mn is connected to the pixel electrode 26 mn. A liquid crystal (generally, a photovoltaic device) is sealed between the pixel electrode 26 mn and the counter electrode 28 mn opposed thereto to form a liquid crystal capacitor (in a broad sense, a liquid crystal element) 24 mn. The transmittance of the pixel changes depending on the applied voltage between the pixel electrode 26 mn and the opposite electrode 28 mn . The counter electrode voltage Vcom is supplied to the counter electrode 28 mn.

Such an LCD panel 20 is formed by laminating a first substrate on which a pixel electrode and a TFT are formed and a second substrate on which a counter electrode is formed, and sealing a liquid crystal as a photovoltaic material between the substrates.

Therefore, the LCD panel 20 may include a pixel electrode connected to a source line via a TFT as a switching element. Further, the LCD panel 20 may include a plurality of source lines, a plurality of switching elements, and a plurality of pixel electrodes each of which is connected to each of the switching elements via the source lines.

The liquid crystal device 10 includes a display driver (broadly speaking, a driving circuit) 90 that drives the LCD panel 20. Display driver 90 includes a source driver 30. source The pole driver 30 drives the source lines of the source lines SL1 to SLN of the LCD panel 20 in accordance with the gray scale data corresponding to the respective source lines. Display driver 90 can include a gate driver (broadly speaking, a scan driver) 32. The gate driver 32 scans the gate lines GL1 G GLM of the LCD panel 20 during one vertical scanning period. The display driver 90 may be configured by omitting at least one of the source driver 30 and the gate driver 32.

The liquid crystal device 10 can include a power supply circuit 94. The power supply circuit 94 generates a necessary voltage when driving the source line, and supplies the source driver 30 to the source. The power supply circuit 94 generates voltages of the power supply voltages VDDH, VSSH and the logic of the source driver 30 required to drive the source lines of the source drivers 30.

Further, the power supply circuit 94 generates a voltage required to scan the gate line and supplies it to the gate driver 32.

Furthermore, the power supply circuit 94 generates a relative electrode voltage Vcom. The power supply circuit 94 outputs the counter electrode voltage Vcom of the periodic high potential side voltage VCOMH and the low potential side voltage VCOML to the opposite electrode of the LCD panel 20 in accordance with the timing of the polarity inversion signal POL generated by the source driver 30.

The liquid crystal device 10 can include a display controller 38. The display controller 38 controls the source driver 30, the gate driver 32, and the power supply circuit 94 in accordance with contents set by a host (such as a central processing unit (CPU) which is not shown in the drawing). The display controller 38 sets an operation mode to the source driver 30 and the gate driver 32, and supplies a vertical synchronizing signal and a horizontal synchronizing signal generated internally.

In addition, FIG. 1 includes a power supply circuit 94 or display control in the liquid crystal device 10. The controller 38 is configured. However, at least one of these may be provided outside the liquid crystal device 10. Alternatively, the liquid crystal device 10 may include a host.

In addition, the source driver 30 may also include at least one of the gate driver 32 and the power circuit 94.

Further, part or all of the source driver 30, the gate driver 32, the display controller 38, and the power supply circuit 94 may be formed on the LCD panel 20. As shown in FIG. 2, a display driver 90 (a source driver 30 and a gate driver 32) is formed on the LCD panel 20. As such, the LCD panel 20 can include: a plurality of source lines, a plurality of gate lines, a plurality of switching elements connected to the gate lines of the plurality of gate lines and the source lines of the plurality of source lines, and a plurality of driving elements The source line of the source line is formed. A plurality of pixels are formed in the pixel formation region 80 of the LCD panel 20.

FIG. 3 shows an example of the structure of the gate driver 32 of FIG. 1 or 2.

The gate driver 32 includes a shift register 40, a level shifter 42, and an output buffer 44.

The shift register 40 includes a plurality of flip-flops that are respectively connected to the respective gate lines and are sequentially connected to each of the flip-flops. The shift register 40 is synchronized with the clock signal CPV, and when the start pulse signal STV is held in the flip-flop, the start pulse signal STV is sequentially shifted to the adjacent flip-flop in synchronization with the clock signal CPV. The clock signal CPV input here is a horizontal synchronizing signal, and the start pulse signal STV is a vertical synchronizing signal.

The level shifter 42 shifts the voltage level from the shift register 40 to a voltage level corresponding to the transistor capability of the liquid crystal cell of the LCD panel 20 and the TFT. quasi. This voltage level requires a high voltage level of 20 V to 50 V.

The output buffer 44 buffers the scan voltage shifted by the level shifter 42 and outputs it to the gate line to drive the gate line. The high potential side of the pulse-shaped scanning voltage is a selection voltage, and the low potential side of the scanning voltage is a non-selection voltage.

Alternatively, as shown in FIG. 3, the gate driver 32 may scan the gate lines without using the shift register to scan the gate lines by selecting the gate lines corresponding to the decoding results of the address decoder.

4 is a block diagram showing a configuration example of the source driver 30 of FIG. 1 or 2.

The source driver 30 includes an I/O buffer 50, a display memory 52, a line latch 54, a gray scale voltage generating circuit 58, and a DAC (digital/analog converter) (in a broad sense, a gray scale voltage generating circuit) 60 and source line drive circuit 62.

In the source driver 30, gray scale data D is input as from the display controller 38. The gray scale data D is input in synchronization with the dot clock signal DCLK and buffered in the I/O buffer 50. The dot clock signal DCLK is supplied from the display controller 38.

The I/O buffer 50 is accessed by the display controller 38 or a host not shown. The gray scale data buffered by the I/O buffer 50 is written in the display memory 52. Further, the gray scale data read from the display memory 52 is buffered by the I/O buffer 50, and output to the display controller 38 or the like.

The display memory 52 includes a plurality of memory cells provided with respective memory cells corresponding to respective output lines connected to the respective source lines. Each memory cell is specified by a column address and a row address. In addition, each memory cell of one scan line portion is provided by a line address And specific.

The address control circuit 66 generates a column address, a row address, and a line address for the memory cells in the display memory 52. The address control circuit 66 generates a column address and a row address when writing gray scale data to the display memory 52. That is, the gray scale data buffered by the I/O buffer 50 is written into the memory cells of the display memory 52 specified by the column address and the row address.

Column address decoder 68 decodes the column address and selects the memory cells of display memory 52 corresponding to the column address. The row address decoder 70 decodes the row address and selects the memory cell of the display memory 52 corresponding to the row address.

When the grayscale data is read from the display memory 52 and output to the line latch 54, the address control circuit 66 generates a line address. That is, the line address decoder 72 decodes the line address and selects the memory cell of the display memory 52 corresponding to the line address. Then, the gray scale data of one horizontal scanning portion read from the memory cell specified by the line address is output to the line latch 54.

When the address control circuit 66 reads the gray scale data from the display memory 52 and outputs it to the I/O buffer 50, a column address and a row address are generated. That is, the grayscale data of the memory cells of the display memory 52 held by the column address and the row address are read by the I/O buffer 50. The gray scale data read by the I/O buffer 50 is taken out by the display controller 38 or a host not shown.

Therefore, the column address decoder 68, the row address decoder 70, and the address control circuit 66 in FIG. 4 function as a write control circuit that controls the writing of gray scale data to the display memory 52. In addition, in FIG. 4, the line address decoder 72, the row address decoder 70, and the address control circuit 66 are read as control from the display memory 52. Take the function of reading control circuit of gray scale data.

The line latch 54 latches the gray scale data of one horizontal scanning portion read from the display memory 52 by specifying the timing of the change of the latch pulse LP during one horizontal scanning period. The line latch 54 includes a plurality of registers in which each register holds gray scale data of one dot portion. The gray scale data of one dot portion read from the display memory 52 is placed in each of the registers of the plurality of registers of the line latch 54.

The gray scale voltage generating circuit 58 generates a complex gray scale voltage corresponding to each gray scale data for each gray scale voltage (reference voltage). More specifically, the gray scale voltage generating circuit 58 generates a complex gray scale voltage corresponding to each gray scale data for each gray scale voltage in accordance with the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH.

Each source output of DAC 60 produces a gray scale voltage corresponding to gray scale data from one horizontal scanning portion of line latch 54. More specifically, the DAC 58 is selected from the gray scale data of the one line portion of the line latch 54 from among the complex gray scale voltages generated by the gray scale voltage generating circuit 58, corresponding to the respective sources The grayscale voltage of the grayscale data corresponding to the line, and outputs the selected grayscale voltage. Such a DAC 60 includes voltage selection circuits DEC ₁ ~ DEC _{N for} each source output setting. Each of the voltage selection circuits outputs a gray scale voltage corresponding to each gray scale data from a plurality of gray scale voltages from the gray scale voltage generating circuit 58.

The source line driving circuit 62 includes output circuits OP ₁ to OP _N . Each of the output circuits OP ₁ to OP _N includes an operational amplifier circuit and performs impedance conversion using output gray scale voltages from respective voltage selection circuits of the DAC 60 to drive the source lines.

2. Structure example of source driver

In the present embodiment, in order to reduce the circuit scale of the source driver block provided for each source output, a flip type sample hold circuit is provided in each output circuit of the source line drive circuit 62. Then, the voltage is supplied to the source line by the flip type sample hold circuit. More specifically, the first and second gray scale voltages outputted by the DAC 60 are received, and the flip type sample hold circuit outputs an output gray scale voltage between the first gray scale voltage and the second gray scale voltage to the source line.

Here, an output circuit including the source line driving circuit 62 of such a flip type sample-and-hold circuit will be described.

FIG. 5 shows the source line electrode circuit diagram of a circuit embodiment of the output circuit 62 OP ₁ driving.

Figure 5 is shows the structure of _an output circuit OP, but the other output circuit OP ₂ ~ OP _N also has the same structure of the output circuit OP _1. In addition, FIG. 5 shows an example in which two kinds of output gray scale voltages between the first and second gray scale voltages are generated, but the type of the gray scale voltage is not limited in the present invention.

FIG. 5 is to supply the first and second gray scale voltages from the DAC 60 as the input voltage Vin, and supply the output gray scale voltage Vout to the source line.

The types of gray scale voltages generated by the gray scale voltage generating circuit 58 can be eliminated by the number of types of output gray scale voltages generated in the output circuit. Therefore, the number of gray scale voltage signal lines can be greatly reduced, and the circuit scale of the DAC 60 can be greatly reduced. If the source driver 30 drives the source line according to the gray level data of 6 bits, the original gray scale voltage generating circuit needs to generate 64 (= 2 ⁶ ) gray scale voltages. However, since each output circuit of the source line driving circuit 62 shown in FIG. 5 can generate two kinds of gray scale voltages, the gray scale voltage generating circuit 58 only needs to generate 32 kinds of gray scale voltages. Therefore, the number of gray scale voltage signal lines only needs to be 32, and the wiring area of the gray scale voltage signal lines can be halved. Further, actually, in the present embodiment, since the output circuit generates voltages for dividing the first and second gray scale voltages, 33 gray scale voltage signal lines are required.

Such an output circuit includes a flip type sample hold circuit. The operation of the flip type sample-and-hold circuit differs between the sampling period set in the first half of the horizontal scanning period (1H) and the holding period in the second half. That is, the flip type sample hold circuit supplies the charge stored during the sampling period to the output side thereof during the hold period.

The output circuit includes an operational amplifier circuit and a plurality of capacitive elements connected to one end of the operational amplifier circuit. Then, during the sampling period, the output circuit is electrically connected to the input and output of the operational amplifier circuit in the state of electrically interrupting the output and the source line of the operational amplifier circuit, and the storage of the capacitive elements of the plurality of capacitive components corresponds to The charge of the first or second gray scale voltage. That is, the output of the operational amplifier circuit and the source line are electrically interrupted without changing the voltage of the source line during the sampling period. Then, charges corresponding to any one of the first and second gray scale voltages are stored at one end of the plurality of capacitive elements, and charges are supplied to the other end of the plurality of capacitive elements by operating the driving portion of the output section of the amplifying circuit.

Next, during the subsequent hold period, the output circuit electrically blocks the input and output of the operational amplifier circuit, and supplies the charge stored in the complex capacitive element to the output of the operational amplifier circuit. At this time, the output of the operational amplifier circuit and the source line are electrically connected. That is, during the hold, in order to supply on the source line The gray scale voltage is output, and the output and the source line of the operational amplifier circuit are electrically connected. Then, the input and output of the operational amplifier circuit are electrically interrupted, and the charge stored in the plurality of capacitive components is supplied to the output of the operational amplifier circuit. In this way, by the virtual short-circuit function on the input side of the operational amplifier circuit whose input voltage and output voltage are equal to each other, the charge and discharge of the driving portion of the operational amplifier circuit are performed, and the output gray-scale voltage can be changed.

More specifically, the output circuit OP ₁ may include: an operational amplifier circuit OPC ₁ , first to jth (j is an integer of 2 or more) capacitive elements C1 to Cj, and first to jth flip switches S3-1 ~S3-j and output switch S4. In the operational amplifier OPC non-inverting input of _an analog ground AGND supply (voltage designated) terminal. When the high-potential side power supply voltage of the operational amplifier circuit OPC ₁ is VDD and the low-potential side power supply voltage is VSS, the analog ground AGND can be (VDD + VSS)/2. A first capacitive element C1 ~ of the ~ j Cj one end is connected to operational amplifier inverting input terminal of _an OPC. The capacitance values of the first to jth capacitive elements C1 to Cj are equal. Of p (1 ≦ p ≦ j, p is an integer) of the p-inverted insertion of the capacitive element Cp switches S3-p with the other end of the operational amplifying circuit between the output of _an OPC. Output switch S4 is inserted into the output of the operational amplifier OPC _1, and between the output line and the source line SL1 is electrically connected to it. By supplying the first and second gray scale voltages to the first to jth capacitive elements C1 to Cj, 2 ^(j-1) kinds of output gray scale voltages between the first and second gray scale voltages can be generated.

In addition, the output circuit OP ₁ may further include first to jth input switches. One end of the input switch of the pth (1≦p≦j, p is an integer) is connected to the other end of the capacitive element Cp of the pth. Then, the first or second gray scale voltage is time-divisionally supplied to the other end of each of the input switches of the first to jth input switches.

Next, a more specific structure and operation will be described by taking the case of FIG. 5 as an example. Figure 5 shows the case of j series 2. The first input switch S0 performs switching control (on/off control) by the switch control signal SC0. The second input switch S1 is switched and controlled by the switch control signal SC1. The feedback switch S2 is switched and controlled by the switch control signal SC2. The first and second inversion switches S3-1 and S3-2 are switched and controlled by the switch control signal SC3. The output switch S4 is switched and controlled by the switch control signal SC4. Such switching control signals SC0 ~ SC4 system (not shown) is generated in the control circuit of the output circuit OP _1.

Figure 6 shows the output circuit of FIG. 5 OP ₁ is a first operation explanatory diagram of the embodiment.

During the sampling period, the first gray scale voltage Vin1 and the second gray scale voltage Vin2 are supplied time divisionally. During the supply of the first gray scale voltage Vin1, the first input switch S0 is turned on, and the subsequent sampling period and the holding period are turned off to perform switching control. Further, the second input switch S1 is switched and controlled in such a manner as to be turned on at least during the supply of the second gray scale voltage Vin2. Further, the second input switch S1 is switched on in such a manner as to be turned on during the sampling period and turned off during the holding period.

The feedback switch S2 performs switching control in such a manner that it is turned on during sampling and turned off during the holding period. The first and second inversion switches S3-1 and S3-2 are switched on during the sampling period and are turned on during the holding period. The output switch S4 is turned off during sampling, and is turned on and off during the hold period.

That is, during the sampling period, in the state in which the first to jth flip switches are turned off, the feedback switch S2 is turned on, and the output switch S4 is turned off, the other ends of the first and second capacitive elements C1 and C2 are turned off. Supply first and second gray scale voltages One of Vin1 and Vin2. Then, during the hold period after the sampling period, by turning on the first to jth flip switches, turning off the feedback switch S2, and turning on the output switch S4, the first gray scale voltage Vin1 and the second gray are The output gray scale voltage Vout between the step voltages Vin2 is output to the source line.

More specifically, in FIG. 6, during sampling, the charge corresponding to the first gray scale voltage Vin1 is stored at one end of the first capacitive element C1 via the first input switch S0. Further, a charge corresponding to the second gray scale voltage Vin2 is stored at one end of the second capacitive element C2 via the second input switch S1. During this period, because the feedback switch S2 is turned on, the OPC by the operational amplifier imaginary short of _a function, the arithmetic circuit voltage of the operational amplifier OPC ₁ of node NEG inverting input terminal of the amplifier circuit ₁ OPC analog output voltage becomes Ground AGND.

Therefore, during sampling, the charge Qs represented by the following formula is stored on the node NEG. At this time, since the output switch S4 is turned off, the voltage of the source line SL1 does not change.

Qs=Vin1×C+Vin2×C.........(1)

Here, Vin1 is the first gray scale voltage, Vin2 is the second gray scale voltage, and the capacitance values of the respective capacitive elements of the first and second capacitive elements C1 and C2 are C.

Next, during the holding period, the first and second input switches S0 and S1 and the feedback switch S2 are turned off, and the first and second inverting switches S3-1 and S3-2 are turned on. As a result, an output corresponding to the first and second capacitive elements C1, C2 in the voltage of the charge stored as operational amplifier circuits OPC output the gray scale voltage _1. At this time, since one ends of the first and second capacitive elements C1, C2 are short-circuited, the output gray scale voltage Vout is expressed by the following formula.

Vout=(Vin1+Vin2)/2.........(2)

FIG 5 FIG. 7 shows the output of the operation circuit OP of the second embodiment of FIG. _{1 will} be described.

6 is supplied to the first and second capacitive elements in the order of the high potential of the first and second gray scale voltages. However, FIG. 7 is supplied to the first in the order of the low potentials of the first and second gray scale voltages. And a second capacitive element.

Also in this case, similarly to FIG. 6, the first and second input switches S0 and S1, the feedback switch S2, and the first and second inversion switches S3-1 and S3-2 and the output switch S4 are switched. Then, the output gray scale voltage Vout expressed by the formula (2) is output during the hold period.

Output shown in Figure 8. Figure 5 of the operation circuit OP of the third embodiment of FIG. _{1 will} be described.

6 and 7 show an example in which the voltage between the first gray scale voltage Vin1 and the second gray scale voltage Vin2 is output and the output gray scale voltage Vout is output, but the present invention is not limited thereto. By setting the first and second gray scale voltages Vin1, Vin2 to the same potential voltage, the output gray scale voltage Vout can be a voltage having the same potential as the first and second gray scale voltages Vin1, Vin2.

Also in this case, similarly to FIG. 6, the first and second input switches S0 and S1, the feedback switch S2, and the first and second inversion switches S3-1 and S3-2 and the output switch S4 are switched. As a result, according to the formula (2), the output gray scale voltage Vout becomes a voltage of the same potential as the first and second gray scale voltages Vin1, Vin2, and the output gray scale voltage Vout is output during the sustain period.

Since the flip-type sample-and-hold circuit described above is used to drive the source line, it is possible to have a very simple structure to generate a complex gray scale voltage with the output circuit. As a result, the gray scale voltage type to be generated by the gray scale voltage generating circuit 58 can be greatly reduced. Thereby, the number of gray scale voltage signal lines can be deleted, and The circuit scale of the DAC 60 is greatly reduced. In general, since the DAC 60 is required to increase the transistor size by supplying a high voltage, the circuit scale of the DAC 60 is reduced, which greatly contributes to the downsizing of the wafer size of the source driver 30.

Further, in the case of the above-described flip type sample-and-hold circuit, the rail-to-rail operation can be performed without adding an auxiliary circuit or the like, and it is not necessary to increase the size of the transistor in order to suppress variations. Thus, the size of the wafer of the source driver 30 is reduced.

Further, since the above sampling and holding circuit of a flip type stored in the system so that the first and second capacitive elements C1, C2 of the charge moving to the operational amplifier OPC ₁ circuit configuration of the output side, it is not the operational amplifier OPC ₁ having the By inputting the influence of the offset voltage, the output gray scale voltage Vout can be generated with high accuracy.

Furthermore, the above-mentioned flip type sample-and-hold circuit does not need to output the gray scale voltage given to the source line to the source line for high precision, and outputs the gray scale voltage generated by the DAC 60 to the source line, and only the output circuit can generate gray with high precision. Order voltage. Therefore, it is not necessary to generate the gray scale voltage with high precision of the DAC 60, the structure of the DAC 60 can be simplified, and the circuit scale of the DAC 60 can be reduced.

2.1 Comparative example

Further, the flip type sample-and-hold circuit having the configuration of the present embodiment is such that the order of the switching control of the first to j-th input switches during the sampling period and the level of the gray-scale voltage input to each of the input switches are as follows. That is, the output gray scale voltage Vout is the lowest potential voltage than the voltage output to the source line, and is close to the highest potential voltage of the voltage output to the source line, as shown in FIG. 6, the DAC 60 (gray scale voltage generation) The circuit must output the first and second gray scale voltages in the order of the potential. Here, as for the 64 gray scale voltages V0~V63, the lowest When the potential voltage is V0, the highest potential voltage is V63, and when the lowest potential voltage is V63, the highest potential voltage is V0.

Further, when the output gray scale voltage Vout is closer to the lowest potential voltage than the highest potential voltage, the DAC 60 (gray scale voltage generating circuit) outputs the first and second gray scale voltages in order of low potential.

Therefore, when the first or second gray scale voltage is supplied to the other end of each of the first to jth input switches, the output gray scale voltage Vout is closer to the highest potential voltage than the lowest potential voltage, in the first and second In the gray scale voltage, when the gray scale voltage on the high potential side is supplied to any one of the first to the jth capacitive elements C1 to Cj, the gray scale voltage on the low potential side is supplied to the first to the jth. The switching control of the first to jth input switches is performed by any one of the capacitive elements C1 to Cj.

Further, in the case where the first or second gray scale voltage is supplied to the other end of each of the first to jth input switches, the output gray scale voltage Vout is closer to the lowest potential voltage than the highest potential voltage, in the first and second In the gray scale voltage, when the gray scale voltage on the low potential side is supplied to any one of the first to the jth capacitive elements C1 to Cj, the gray scale voltage on the high potential side must be supplied to the first to the jth. The switching control of the first to jth input switches is performed by any one of the capacitive elements C1 to Cj.

Hereinafter, the above reasons will be described in comparison with the comparative example of the present embodiment.

9 an explanatory view showing a comparative example of the present embodiment forms the output circuit of the example _of the operation OP.

In FIG. 9, the same portions as those in FIGS. 6 to 8 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. This comparative example is in the first half of the sampling period and is connected to the first loss. When the switch S0 is turned in and the second input switch S1 is turned off, the first gray scale voltage Vin1 is supplied to one end of the first capacitive element C1, and then, in the second half of the sampling period, the first input switch is turned off. In a state where S0 is turned on and the second input switch is turned on, the second gray scale voltage Vin2 is supplied to one end of the second capacitive element C2. The potential of the first gray scale voltage Vin1 of the comparative example is a potential lower than the potential of the second gray scale voltage Vin2.

Fig. 10 is a view showing the operation of this comparative example.

In FIG. 10, the same portions as those in FIG. 5 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. Fig. 10 shows a state in which the first input switch S0 is turned off and the second input switch S1 is turned on during sampling.

The first gray scale voltage Vin1 (SQ1) of FIG. 9 is supplied to the first capacitive element C1 in a state where the first input switch S0 is turned on and the second input switch S1 is turned off. At this time, the electric charge corresponding to the first gray scale voltage Vin1 is stored in the first capacitive element C1. Next, as shown in FIG. 10, in a state where the first input switch S0 is turned off and the second input switch S1 is turned on, the second gray scale voltage Vin2 of FIG. 9 is supplied to the second capacitive element C2 (Vin1<Vin2). (SQ2). At this time, the electric charge corresponding to the second gray scale voltage Vin2 is stored in the second capacitive element C2.

Here, with the application of the second gray scale voltage Vin2, the voltage level fluctuation of the node NEG (the other end of the second capacitive element C2) corresponding to the electric charge of the first gray scale voltage Vin1 is stored. Since the other end of the first capacitive element C1 and the other end of the second capacitive element C2 are electrically connected, the fluctuation of the voltage level of the node NEG is transmitted as a fluctuation in the voltage level of one end of the first capacitive element C1 capacitively coupled.

At this time, the voltage fluctuation of the node NEG is transmitted via the first capacitive element C1, and is a fluctuation of the voltage level of one of the first inversion switches S3-1, and the voltage level becomes a potential higher than the power supply voltage VDD (SQ4). This indicates that leakage occurs because the source (drain) of the P-type MOS transistor constituting the switch and the diode connection portion between the substrates forming the transistor are in the positive direction. Therefore, the voltage level of the output gray scale voltage Vout which should be output during the hold period fluctuates.

Therefore, in the second capacitive element C2, the first gray scale voltage Vin1 on the high potential side is first supplied, and then the second gray scale voltage Vin2 on the low potential side is supplied to the second capacitive element C2. The way to switch control. Thereby, the case where the fluctuation of the voltage level of the second capacitive element C2 is transmitted to the node NEG can be avoided.

That is, when the output gray scale voltage Vout is closer to the highest potential voltage than the lowest potential voltage, the gray scale voltage on the high potential side is supplied to the first to jth capacitive elements C1 to Cj in the first and second gray scale voltages. In the state of any one of the capacitive elements, switching control of the first to jth input switches is performed such that the gray scale voltage on the low potential side is supplied to any one of the first to jth capacitive elements C1 to Cj.

9 and 10 illustrate a case where the output gray scale voltage Vout is closer to the highest potential voltage than the lowest potential voltage, but even when the output gray scale voltage Vout is closer to the lowest potential voltage than the highest potential voltage, the same applies. Produces a leakage of the input switch. Therefore, when the output gray scale voltage Vout is closer to the lowest potential voltage than the highest potential voltage, the gray scale voltage on the low potential side is supplied to the first to jth capacitive elements C1 to Cj in the first and second gray scale voltages. In the state of any one of the capacitive elements, the gray on the high potential side The step voltage is supplied to any one of the first to jth capacitive elements C1 to Cj, and the first to the jth input switches are switched.

Here, in order to determine, by a simple structure, that the output gray scale voltage Vout is close to the highest potential voltage of the gray scale voltage or close to the lowest potential voltage, it may be determined based on the highest order bit of the gray scale data.

Fig. 11 is an explanatory view showing the output order of the gray scale voltage in the present embodiment.

For example, the gray-scale voltage corresponding to the uppermost bit of the gray-scale data is “0”, which is higher than the gray-scale voltage corresponding to the highest-order bit being “1”. In this case, when the highest order bit of the gray scale data is "0", the gray scale voltage of the high potential side of the first and second gray scale voltages is supplied to the first capacitive element C1, and the gray of the low potential side is applied. The step voltage is supplied to the second capacitive element C2. In addition, when the highest order bit of the gray scale data is "1", the gray scale voltage of the low potential side of the first and second gray scale voltages is supplied to the first capacitive element C1, and the gray of the high potential side is applied. The step voltage is supplied to the second capacitive element C2. Thereby, no leakage occurs in the first and second inversion switches S3-1 and S3-2, and it is possible to avoid the case where the output gray scale voltage Vout cannot generate the target voltage.

2.2 Structure of the important part of the source driver

Next, a configuration example of an important portion of the source driver 30 in the present embodiment will be described.

Fig. 12 is a block diagram showing a configuration example of a source driver block of the source driver 30 in the present embodiment. In FIG. 12, the same portions as those in FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate. In addition, the following grayscale data is 6-bit.

FIG. 12 shows only the structure of the source driver block of the driving source line SL1. The source driver block for driving the source line SL1 includes an adding circuit 80 ₁ , an adding control logic 82 ₁ , a voltage selecting circuit DEC _{1 ,} and an output circuit OP ₁ .

In this embodiment, the first and second gray scale voltages are supplied to the output circuit OP ₁ for time division, and the gray scale data D[5:0] is output from the display memory 52, and the gray scale data is incremented. The data of the gray scale data is supplied to the voltage selection circuit DEC ₁ . At this time, the adding circuit 80 ₁ controls the addition control signal ADD_BIT from the addition control logic 82 ₁ to output the data of the incremental gray scale data or output the gray scale data without change.

More specifically, the data D[5:1] of the upper 5 bits of the grayscale data D[5:0] is input to the adding circuit 80 ₁ . Further, the data of the uppermost bit D[5] of the grayscale data D[5:0] and the data of the lowermost bit D[0] are input to the addition control logic 82 ₁ . The addition control logic 82 ₁ inputs the addition timing signals AD1, AD2 generated in the control circuit not shown, and generates addition according to the data of the gray scale data D[5], D[0] and the addition timing signals AD1, AD2. Control signal ADD_BIT.

An explanatory diagram of the addition timing signals AD1, AD2 of Fig. 12 is shown in Fig. 13.

During the adder AD1 timing signal is H level, the period corresponding to the first supply input of switch S0 is turned on in the gray scale voltage output circuit OP ₁ of the first capacitive element C1. During timing signal adder AD2 is H level, the period corresponding to the supply input switch S1 turns on the second gray scale voltage of the output circuit of the second capacitive element C2 of OP _1.

The operation description of the addition control logic 82 ₁ of Fig. 12 is shown in Table 1.

In Table 1, when the grayscale data [5:0] is "000000", the grayscale voltage is the highest potential, and when the grayscale data [5:0] is "111111", the grayscale voltage is the lowest potential.

Addition control logic ₈₂₁ in order of the most gray data bit D [5] of the data lines is "0", at the timing of the timing signal of the adder AD2 adder for adding control circuits _801. At this time, when the data of the lowest order bit D[0] of the gray scale data is "0", the adding circuit 80 ₁ outputs the data of the gray scale data D[5:1] to the voltage selecting circuit DEC ₁ without change. . In addition, when the data of the lowest order bit D[0] of the gray scale data is "1", the adding circuit 80 ₁ will be the data of the incremental gray scale data D[5:1] (in the gray scale data D[ 5: 1] to add "1" of the data) is output to the voltage select circuit DEC _1.

Further, when the addition control logic 82 _{1 is} in the data system "1" of the uppermost bit D[5] of the gray scale data, the addition control of the addition circuit 80 ₁ is performed at the timing of the addition timing signal AD1. At this time, when the data of the lowest order bit D[0] of the gray scale data is "0", the adding circuit 80 ₁ outputs the data of the gray scale data D[5:1] to the voltage selecting circuit DEC ₁ without change. . Further, when the data line "1" in the lowermost gray order bit data D [0] of the adder circuit ₈₀₁ will increment the grayscale data D [5: 1] The data output to the voltage selection circuit DEC _1.

In Fig. 12, the output of the adding circuit 80 ₁ thus controlled by the addition control logic 82 ₁ is input to the voltage selecting circuit DEC ₁ as gray scale data. Gray-scale voltage selecting circuit DEC ₁ based on the grayscale data from the addition circuit _801, by the grayscale voltage generating circuit 58 generates an output of any of V0 ~ V32 to the output circuit OP _1. The output circuit OP ₁ has the structure of FIG.

2.3 auxiliary capacitor components

In this embodiment, as shown in FIG. 5, the auxiliary capacitance element CCS is connected to the node NEG. One end of the auxiliary capacitive element CCS is supplied with a ground power supply voltage VSS or an analog ground AGND, and the other end is connected to a node NEG. Thereby, the voltage fluctuation of the inverting input terminal of the operational amplifier circuit OPC ₁ can be suppressed, and the output gray scale voltage Vout can be further stabilized.

Further, since the auxiliary capacitance element CCS is intended to suppress potential fluctuation, it is not necessary to compare the first and second capacitance elements C1 and C2, and the capacitance value is accurately formed. Therefore, in the capacitive element forming region where the auxiliary capacitive element CCS and the first and second capacitive elements C1 and C2 are formed, the auxiliary capacitive element CCS must be formed in the first and second capacitive elements C1 and C2, formed by etching or the like. The area where the capacitive element is difficult to control. Therefore, the auxiliary capacitance element CCS must also be used as a dummy capacitance element formed in the capacitance element formation region in the source driver.

14(A) and 14(B) are explanatory views showing the auxiliary capacitance element CCS.

FIG. 14(A) shows a layout image of the source driver 30. The source driver 30 is arranged in parallel with the source driver blocks SB1 to SBN in the direction in which the output pads (Pads) of the source lines are arranged. Each source driver block includes: gray scale voltage generation The circuit, the voltage selection circuit, and the source line driver circuit have the same layout configuration of each source driver block.

Fig. 14(B) shows an image of the capacitance element forming region of the source driver block SBn. The source driver block SBn has a first capacitive element C1 and a second capacitive element C2 formed in a direction perpendicular to the direction in which the source driver blocks SB1 SB SBN are arranged (the direction in which the output pads are arranged). The capacitive element of the auxiliary capacitive element CCS forms a region CEA. At this time, the auxiliary capacitance element CCS is formed along one of the boundary portions of the two boundary portions facing the direction perpendicular to the arrangement direction (the direction intersecting) in the boundary of the capacitance element formation region CEA. In general, a virtual capacitance element in a region where a capacitor element is formed is formed in the boundary portion. 14(B), when the arrangement direction of the source driver blocks SB1 to SBN is referred to as DR1, the two sides of the boundary portion of the source driver block SBn which is opposed to the direction DR2 which is perpendicular to the arrangement direction DR1 are formed. One of the sides EDn forms the auxiliary capacitive element CCS.

Thereby, the edges of the first and second capacitive elements C1, C2 (ends) and the edge of the auxiliary capacitive element CCS of the source driver block, and the first and second capacitive elements of the adjacent source driver block The edges of C1 and C2 are adjacent. Therefore, since the gaps Δd1 to Δd4 between the respective edges can be formed at substantially the same etching speed, the first and second capacitive elements C1 and C2 can be formed with high precision. In addition, the edges of the auxiliary capacitive element CCS are not adjacent to the edges of the other capacitive elements. Therefore, regarding the edge of the auxiliary capacitance element CCS, such as the etching speed from the output pad arrangement region side, since the etching speeds from the first and second capacitance elements C1 and C2 sides are different, the first and second electrodes are Compared with the capacitive elements C1 and C2, the capacitive element cannot be accurately formed.

As shown in FIG. 14(B), by forming the respective capacitance elements, the capacitance values of the first and second capacitance elements C1, C2 can be accurately formed, and the layout area is not wasted, and the auxiliary capacitance element CCS can be formed.

2.4 operational amplifier circuit

The circuit scale of the flip type sample-and-hold circuit in this embodiment must be small. Therefore, the flip-type sample-and-hold circuit of the present embodiment focuses on the discrete operation during the sampling period and the holding period, and the operational amplifier circuit applied to the inverted-type sample-and-hold circuit must have the following configuration.

In the flip type sample-and-hold circuit of the present embodiment, the output switch S4 is turned off during the sampling period, the output of the low load is driven, and the output switch S4 is turned on during the hold period to drive the output of the high load. Therefore, in the operational amplifier circuit of the flip-type sample-and-hold circuit of the present embodiment, the class A amplification operation can be performed during the sampling period, and the AB-stage amplification operation can be performed during the sustain period. Therefore, the operational amplifier circuits OPC ₁ to OPC _{N of the} present embodiment can adopt the following configurations.

Fig. 15 is a circuit diagram showing a configuration example of the operational amplifier circuit OPC ₁ of Fig. 5.

Fig. 15 shows an example of the configuration of the operational amplifier circuit OPC ₁ , but the other operational amplifier circuits OPC ₂ to OPC _N have the same configuration.

The operational amplifier circuit OPC ₁ includes a differential amplifier 110 (in a broad sense, an operational amplifier), an output unit 120, a capacitor CCP, and a charge supply circuit 130. The differential amplifier 110 amplifies a difference value between the input voltage VIN and the output voltage VOUT. The output unit 120 includes a P-type driving transistor (first driving transistor of the first conductivity type) PTR1 according to a voltage of an output node NDD of the differential amplifier 110 provided on the first power supply side to which the analog power supply voltage AVDD is supplied. And controlling the gate electrode thereof; and an N-type driving transistor (second driving transistor of the second conductivity type) NTR1, which is provided in series with the P-type driving transistor PTR1 on the second power supply side to which the analog ground AGND is supplied. The capacitor CCP is provided in such a manner as to capacitively couple the gate electrode of the P-type driving transistor PTR1 and the gate electrode of the N-type driving transistor NTR1.

The charge supply circuit 130 supplies electric charge to the gate electrode of the N-type drive transistor NTR1 during the sampling period, and stops supplying the charge to the gate electrode of the N-type drive transistor NTR1 during the sustain period. Thereby, during the sampling period, the P-type driving transistor PTR1 and the N-type driving transistor NTR1 are operated according to the voltage of the output node NDD of the differential amplifier 110, so that the output voltage VOUT of the operational amplifier circuit 100 can be on the high potential side or The low potential side changes. Further, during the holding period, the output voltage VOUT is output depending on the voltage of the gate electrode of the P-type driving transistor PTR1. Therefore, the configuration of the operational amplifier circuit OPC ₁ that performs the class A amplification operation during the sampling period and performs the AB amplification operation during the holding period can be simplified.

Fig. 16 is a circuit diagram showing a configuration example of the operational amplifier circuit OPC ₁ of Fig. 15.

The same portions as those in Fig. 15 are denoted by the same reference numerals, and the description thereof will be appropriately omitted.

The differential amplifier 110 includes a current mirror circuit CM1, a differential pair DIF1, and a current source CS1. The current mirror circuit CM1 includes P-type transistors PTR10, PTR11 that supply an analog power supply voltage AVDD at its source. A gate electrode of the P-type transistor PTR10 and a gate electrode of the P-type transistor PTR11 are connected. P type The crystal PTR11 is connected to its gate electrode and drain.

The differential pair DIF1 includes N-type transistors NTR10 and NTR11. The source of the N-type transistor NTR10 and the source of the N-type transistor NTR11 are connected. The drain of the N-type transistor NTR10 is connected to the drain of the P-type transistor PTR10. The drain of the N-type transistor NTR11 is connected to the drain of the P-type transistor PTR11. An analog ground AGND is supplied to one end of the current source CS1, and the other end of the current source CS1 is connected to the sources of the N-type transistors NTR10 and NTR11.

The differential amplifier 110 supplies an input voltage VIN to the gate electrode of the N-type transistor NTR10, and supplies an output voltage VOUT to the gate electrode of the N-type transistor NTR11. Then, the connection node connecting the drain of the P-type transistor PTR10 and the drain of the N-type transistor NTR10 becomes the output node NDD of the differential amplifier 110. The output node is connected to the gate electrode of the P-type driving transistor PTR1 of the output portion 120.

The charge supply circuit 130 includes: a current source transistor CTR that supplies a diode to the drain of the drain thereof; and a gate electrode that is connected to the current source transistor CTR at one end thereof, and the other end of which is connected to one end of the capacitor CCP and the N type A switching circuit SWT that drives a gate electrode of the transistor NTR1. The switching circuit SWT is switched and controlled by the switching control signal STC. The charge supply circuit 130 may further include a current source CS2 connected to the drain of the current source transistor CTR to generate a steady current.

Fig. 17 is a view showing the operation of the switching control signal of the sample-and-hold circuit to which the operational amplifier circuit of Fig. 16 is applied.

Figure 17 is a diagram showing the first and second input switches S0, S1, the feedback switch S2, the first and second inversion switches S3-1, S3-2, and the output switch S4. An example of the operation of the switching circuit SWT of 16. As shown in Fig. 17, the switch circuit SWT of Fig. 16 is switched on during the sampling period by the switch control signal STC generated by the control circuit (not shown), and is turned off during the hold period.

The operational amplifier circuit OPC ₁ of Fig. 16 changes the gate electrode of the N-type drive transistor NTR1 in response to the change of the gate electrode of the P-type drive transistor PTR1 via the capacitor CCP. The charge supply circuit 130 turns on the switch circuit SWT during sampling, and stores the charge in the gate electrode of the N-type drive transistor NTR1 by the current source transistor CTR, and simultaneously drives the gate electrode of the P-type drive transistor PTR1. The voltage change is transmitted to the gate electrode of the N-type driving transistor NTR1. Further, the charge supply circuit 130 turns off the switching circuit SWT during the holding period, and transmits the voltage change of the gate electrode of the P-type driving transistor PTR1 to the gate electrode of the N-type driving transistor NTR1.

In the differential amplifier 110 of the operational amplifier circuit OPC ₁ of such a configuration, the case where the input voltage VIN is higher than the output voltage VOUT is considered. At this time, the voltage of the output node NDD drops, and the drain voltage of the N-type transistor NTR11 increases. As a result, the voltage of the gate electrode of the P-type driving transistor PTR1 drops, and the P-type driving transistor PTR1 faces the direction of turn-on. Here, when the voltage of the gate electrode of the P-type driving transistor PTR1 drops, the voltage of the gate electrode of the N-type driving transistor NTR1 also decreases.

Further, the case where the input voltage VIN is lower than the output voltage VOUT is considered in the differential amplifier 110. At this time, the voltage of the output node NDD rises, and the drain voltage of the N-type transistor NTR11 decreases. As a result, the voltage of the gate electrode of the P-type driving transistor PTR1 rises, and the P-type driving transistor PTR1 faces off. The direction of opening. Here, when the voltage of the gate electrode of the P-type driving transistor PTR1 rises, the voltage of the gate electrode of the N-type driving transistor NTR1 also rises.

As a result of the above operation, the operational amplifier circuit OPC ₁ shifts to an equilibrium state in which the input voltage VIN and the output voltage VOUT are substantially the same potential.

In addition, the operational amplifier circuit OPC _{1 of} FIG. 15 is not limited to the structure of FIG. As shown in FIG. 15, it is considered that the first power supply is supplied with the power supply of the analog ground AGND, and the second power supply is supplied with the power supply of the analog power supply voltage AVDD. When the first conductivity type is N type and the second conductivity type is P type, the following configuration is as follows. .

Fig. 18 is a circuit diagram showing another configuration example of the operational amplifier circuit of Fig. 15.

At this time, the output unit 120 includes an N-type driving transistor NTR2 that controls its gate electrode according to the voltage of the output node of the differential amplifier 110 provided on the first power supply side, and a P-type driving transistor PTR2. It is provided in series with the N-type driving transistor NTR2 on the second power supply side.

The differential amplifier 110 of the operational amplifier circuit shown in FIG. 18 includes a current mirror circuit CM10, a differential pair DIF10, and a current source CS10. The current mirror circuit CM10 includes N-type transistors NTR40 and NTR41 which are supplied with an analog ground AGND in their sources. A gate electrode of the N-type transistor NTR40 and a gate electrode of the N-type transistor NTR41 are connected. And connected to the gate electrode and the drain of the N-type transistor NTR41.

The differential pair DIF 10 includes P-type transistors PTR40 and PTR41. The source of the P-type transistor PTR40 and the source of the P-type transistor PTR41 are connected. The drain of the P-type transistor PTR40 is connected to the drain of the N-type transistor NTR40. The drain of the P-type transistor PTR41 is connected to the drain of the N-type transistor NTR41. At current One end of the source CS10 is supplied with an analog supply voltage AVDD, and the other end of the current source 10 is connected to the source of the P-type transistors PTR40, PTR41.

The differential amplifier 110 supplies an input voltage VIN to the gate electrode of the P-type transistor PTR40, and supplies an output voltage VOUT to the gate electrode of the P-type transistor PTR41. Then, the connection node connecting the drain of the N-type transistor NTR 40 and the drain of the P-type transistor PTR 40 becomes the output node NDD of the differential amplifier 110. The output node is connected to the gate electrode of the N-type driving transistor NTR2 of the output portion 120.

The charge supply circuit 130 includes a current source transistor CTR10 which supplies a current on its drain and a diode connection, and a switch circuit SWT which is connected at one end thereof to the gate electrode of the current source transistor CTR10, and at the other end thereof. One end of the capacitor CCP and the gate electrode of the P-type driving transistor PTR2. The charge supply circuit 130 may further include a current source CS20 connected to the drain of the current source transistor CTR10 to generate a steady current.

Since the _arithmetic operation such as shown in FIG. 18 of the amplification circuit configuration of OPC, the operational amplifier circuit shown in FIG. 17 of the same OPC operation _1, the description thereof will be omitted.

2.5 Modifications of the output circuit

In the present embodiment, the output circuit of the source line driving circuit 62 generates two kinds of gray scale voltages between the first and second gray scale voltages. However, the variation of the embodiment generates the first and second gray scales. Four gray scale voltages between voltages. That is, in the description of Fig. 5, a configuration example in which j is 4 is the configuration of the present modification.

Example 19 shows the structure of a circuit diagram of the output of the source line modification of the present embodiment forms the driving circuit 62 is a circuit OP _1.

The same portions as those in Fig. 5 in Fig. 19 are denoted by the same reference numerals, and the description is omitted as appropriate. In addition, FIG. 19 sets the first to fourth input switches SI1 to SI4, and sets the first to fourth inversion switches S3-1 to S3-4. The capacitance values of the first to fourth capacitive elements C1 to C4 are equal.

FIG 20 (A), the output 19 of the operation circuit OP of the first embodiment of _{FIG. 1} explained shown in Figure 20 (B).

Fig. 20(A) and Fig. 20(B) show the first and the first when the data D[1:0] of the lower order 2 bits of the gray level data D[5:0] is "00" is output. An example of an output gray scale voltage between two gray scale voltages. As shown in FIG. 20(A), during the sampling period, the first gray scale voltage Vin1 is given 4.0 V, and when the second gray scale voltage Vin2 is given 3.8 V, the first to fourth input switches SI1 to SI4 are used. All of the first to fourth capacitive elements C1 to C4 are supplied at 4.0 V. Then, as shown in FIG. 20(B), during the holding period, the output gray scale voltage Vout of 4.0 V can be output by supplying the electric charge to the output side via the first to fourth inversion switches S3-1 to S3-4. .

FIG 21 (A), FIG. 19 FIG. 21 outputs the second operation circuit OP ₁ explanatory diagram of a display (B),.

Fig. 21(A) and Fig. 21(B) show the first and the first when the data D[1:0] which outputs 3.95 V as the gray level data D[5:0] is "01". An example of an output gray scale voltage between two gray scale voltages. As shown in FIG. 21(A), during the sampling period, the first gray scale voltage Vin1 is given 4.0 V, and when the second gray scale voltage Vin2 is given 3.8 V, the first to fourth input switches SI1 to SI4 are used. Three of the first to fourth capacitive elements C1 to C4 are supplied with 4.0 V, and 3.8 V is supplied to the remaining one of the capacitive elements. Then, as shown in Figure 21 (B) In the holding period, the first to fourth inverting switches S3-1 to S3-4 are supplied with electric charge to the output side, and an output gray scale voltage Vout of 3.95 V can be output according to the law of charge storage.

FIG. 22 (A), FIG. 19 of FIG. 22 outputs an operation circuit OP of the third embodiment of _{FIG. 1} explained displayed in (B).

Fig. 22(A) and Fig. 22(B) show the first and the first when the data D[1:0] outputting 3.90 V as the lower order 2 bits of the grayscale data D[5:0] is "10" An example of an output gray scale voltage between two gray scale voltages. As shown in FIG. 22(A), during the sampling period, the first gray scale voltage Vin1 is given 4.0 V, and when the second gray scale voltage Vin2 is given 3.8 V, the first to fourth input switches SI1 to SI4 are used. Two of the first to fourth capacitive elements C1 to C4 are supplied with 4.0 V, and 3.8 V is supplied to the other two of the capacitive elements. Then, as shown in FIG. 22(B), during the holding period, the charge is supplied to the output side via the first to fourth inversion switches S3-1 to S3-4, and 3.90 V can be output according to the law of charge storage. The output gray scale voltage Vout.

FIG 23 (A), FIG. 19 of FIG. 23 outputs an operation circuit OP fourth explanatory diagram of a display ₁ in (B).

Fig. 23(A) and Fig. 23(B) show the first and the first when the data D[1:0] with the output of 3.85 V as the gray level data D[5:0] is "11". An example of an output gray scale voltage between two gray scale voltages. As shown in FIG. 23(A), during the sampling period, the first gray scale voltage Vin1 is given 4.0 V, and when the second gray scale voltage Vin2 is given 3.8 V, the first to fourth input switches SI1 to SI4 are used. One of the first to fourth capacitive elements C1 to C4 is supplied with 4.0 V, and the remaining three of the capacitive elements are supplied with 3.8 V. Then, as shown in Figure 23(B) In the holding period, the first to fourth inverting switches S3-1 to S3-4 are supplied with electric charge to the output side, and an output gray scale voltage Vout of 3.85 V can be output according to the law of charge storage.

3. Variation of source driver

The flip type sample-and-hold circuit of the present embodiment can also be applied to an output circuit of a so-called multi-drive source driver.

Fig. 24 is a block diagram showing a configuration example of a source driver in a modification of the embodiment. In FIG. 24, the same portions as those in FIG. 4 are denoted by the same reference numerals, and the description thereof will be appropriately omitted.

The source driver in the present modification differs from the source driver in the embodiment shown in FIG. 4 in that a multiplexer circuit 56 and a separation circuit 64 are provided, and a voltage selection circuit and a constituent source constituting the DAC 60 are provided. In the output circuit of the polar line driving circuit 62, each source output is time-divisionally supplied with gray scale data and gray scale voltage.

In FIG. 24, the multiplexing circuit 56 is provided between the line latch 54 and the DAC 60. The separation circuit 64 is provided on the output side of the source line drive circuit 62.

The multiplexer circuit 56 includes multiplexers MPX ₁ to MPX _k (k is a positive integer), and each multiplexer generates gray scale data of one horizontal scanning portion to be latched by the line latch 54 to q (q) It is a positive integer, wherein each source of the q×k=N) strip outputs time-divided and multiplexed multiplexed data.

FIG. 25 is a view showing the operation of the multiplexer circuit 56 of FIG.

The k in Fig. 25 is 240. At this time, each multiplexer generates multiplexed data that divides the gray scale data corresponding to each source output by 240 times each source output time division multiplex. The gray scale data GD ₁ to GD _{240 for} the first to 240th source outputs to be placed by the line latch 54 are multiplexed by the multiplexer MPX ₁ of the multiplexer circuit 56. The multiplex control signals SEL1 to SEL240 that specify the time division timing are input to the multiplexers of the multiplexers MPX ₁ to MPX _k . Such multiplexer control signals SEL1 to SEL240 are generated in a control circuit (not shown) of the source driver 30. The control circuit generates the multiplex control signals SEL1 to SEL240 in a horizontal scanning period such that any one of the multiplex control signals SEL1 to SEL240 sequentially becomes the H level. During the period when the multiplex control signals are H level, the gray scale data corresponding to the source output of the multiplex control signal is output as the multiplexed data.

The multiplex circuit 56 can also have a plurality of pixel units of a plurality of pixels, and the gray scale data can be time-division multiplexed, and can also constitute a complex point unit of the same color component of each pixel, and the gray-scale data unit is time-divided. Multiple workers. When the pixel is composed of three points of RGB, it is possible to generate multiplexed data in which the gray scale data of each of the two pixel portions is time-division multiplexed. In addition, if the pixel is composed of 3 points of RGB, the multiplexed data of the gray scale data of the R component of the pixels P1 to P6, the multiplexed data of the gray scale data of the G component, and the gray scale of the B component may be respectively generated. Data multiplexed data.

The separation circuit 64 of Fig. 24 includes multiplexers DMPX ₁ to DMPX _k , and each multiplexer performs the opposite operation to the multiplexer corresponding to the multiplexer 56 of the multiplexer. That is, each multiplexer separates the multiplexed gray scale voltages from the respective output circuits of the source line drive circuit 62 and outputs them to the q source outputs. The separation operation timing of the multiplexer is synchronized with the time division timing of each of the multiplexers of the multiplexer circuit 56.

4. Electronic machine

Fig. 26 is a block diagram showing a configuration example of the electronic device in the embodiment. Here, the electronic device displays a block diagram of a configuration example of a mobile phone. In FIG. 26, the same portions as those in FIG. 1 or 2 are denoted by the same reference numerals, and the description thereof will be appropriately omitted.

The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera, and the image data captured by the CCD camera is supplied to the display controller 38 in the YUV format.

The mobile phone 900 includes an LCD panel 20. The LCD panel 20 is driven by a source driver 30 and a gate driver 32. The LCD panel 20 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels.

The display controller 38 is connected to the source driver 30 and the gate driver 32, and supplies the source driver 30 with gray scale data in RGB format.

The power supply circuit 94 is connected to the source driver 30 and the gate driver 32, and supplies a power supply voltage for driving to each driver. Further, a counter electrode voltage Vcom is supplied on the opposite electrode of the LCD panel 20.

Host 940 is coupled to display controller 38. Host 940 controls display controller 38. Further, the host 940 can demodulate the gray scale data received via the antenna 960 by the modulation/demodulation unit 950 and supply it to the display controller 38. The display controller 38 is displayed on the LCD panel 20 by the source driver 30 and the gate driver 32 in accordance with the gray scale data.

The host 940 can instruct the grayscale data generated by the camera module 910 to be modulated by the modulation and demodulation unit 950, and then transmitted to other communication devices via the antenna 960.

The host 940 performs: transmission and reception processing of grayscale data, imaging of the camera module 910, and an LCD panel according to operation information from the operation input unit 970. 20 display processing.

In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention. The present invention is not limited to the driver applied to the liquid crystal display panel described above, and is also applicable to the driving of electroluminescence and plasma display devices.

Further, in the present invention, in the invention of the dependent request item, a part of the constituent elements of the request item of the dependent object may be omitted. In addition, important parts of the invention of one independent claim of the present invention may also be subordinate to other independent claims.

10‧‧‧Liquid device

20‧‧‧LCD panel

22 mn‧‧‧thin film transistor (TFT)

24 mn‧‧‧Liquid Crystal Capacitor (Liquid Crystal Element)

26 mn‧‧‧pixel electrode

28 mn‧‧‧relative electrodes

30‧‧‧Source Driver

32‧‧‧gate driver

38‧‧‧Display controller

40‧‧‧Shift register 40

42‧‧‧ position shifter

44‧‧‧Output buffer

50‧‧‧I/O buffer

52‧‧‧ Display memory

54‧‧‧Wire latch

56‧‧‧Multiworking circuit

58‧‧‧ Gray scale voltage generating circuit

60‧‧‧DAC

62‧‧‧Source line drive circuit

64‧‧‧Separation circuit

66‧‧‧ address control circuit

68‧‧‧ column address decoder

70‧‧‧ row address decoder

72‧‧‧Wire Address Decoder

80 ₁ ‧‧‧Addition circuit

82 ₁ ‧‧‧Additional Control Logic

90‧‧‧ display driver

94‧‧‧Power circuit

110‧‧‧Differential Amplifier (Operational Amplifier)

120‧‧‧Output Department

130‧‧‧Charged supply circuit

900‧‧‧Mobile Phone

910‧‧‧ camera module

940‧‧‧Host

950‧‧‧Transformation and Demodulation Department

960‧‧‧Antenna

970‧‧‧Operation Input Department

AGND‧‧‧ analog grounding

C1‧‧‧First capacitive element

C2‧‧‧second capacitive element

CCS‧‧‧Auxiliary Capacitor Components

DEC ₁ ~ DEC _N ‧‧‧ voltage selection circuit

GL1~GLM‧‧‧ gate line

NEG‧‧‧ node

OP ₁ ~OP _N ‧‧‧Output circuit

OPC ₁ ‧‧‧Operation Amplifier

S0‧‧‧first input switch

S1‧‧‧second input switch

S2‧‧‧ feedback switch

S3-1‧‧‧First flip switch

S3-2‧‧‧second flip switch

S4‧‧‧ output switch

SC0~SC4‧‧‧ switch control signal

SL1~SLN‧‧‧ source line

Vout‧‧‧ output gray scale voltage

Fig. 1 is a view showing an example of the structure of a liquid crystal device in the embodiment.

Fig. 2 is a view showing another example of the configuration of the liquid crystal device of the embodiment.

Fig. 3 is a block diagram showing a configuration example of the source driver of Fig. 1.

4 is a block diagram showing a configuration example of the source driver of FIG. 1 or 2.

Fig. 5 is a circuit diagram showing a configuration example of an output circuit of the source line driving circuit of Fig. 4.

Fig. 6 is an explanatory diagram showing a first operation example of the output circuit of Fig. 5.

Fig. 7 is an explanatory diagram showing a second operation example of the output circuit of Fig. 5.

Fig. 8 is an explanatory diagram showing a third operation example of the output circuit of Fig. 5.

Fig. 9 is an explanatory diagram showing a fourth operation example of the output circuit of Fig. 5.

Fig. 10 is an explanatory view of the operation of the comparative example.

Fig. 11 is an explanatory diagram showing the output order of the gray scale voltage in the embodiment.

Fig. 12 is a block diagram showing a configuration example of a source driver block of the source driver in the embodiment.

Figure 13 is an explanatory diagram of the addition timing signal of Figure 12.

14(A) and 14(B) are explanatory views of the auxiliary capacitance element CCS.

Fig. 15 is a circuit diagram showing a configuration example of the operational amplifier circuit of Fig. 5.

Fig. 16 is a circuit diagram showing a configuration example of the operational amplifier circuit of Fig. 15.

Fig. 17 is a view for explaining the operation of the switch control signal of the sample-and-hold circuit to which the operational amplifier circuit of Fig. 16 is applied.

Fig. 18 is a circuit diagram showing another configuration example of the operational amplifier circuit of Fig. 15.

Fig. 19 is a circuit diagram showing an example of the configuration of an output circuit of a source line driving circuit according to a modification of the embodiment.

20(A) and 20(B) are explanatory views showing a first operation example of the output circuit of Fig. 19.

21(A) and 21(B) are explanatory views showing a second operation example of the output circuit of Fig. 19.

22(A) and 22(B) are explanatory views showing a third operation example of the output circuit of Fig. 19.

23(A) and 23(B) are explanatory views showing a fourth operation example of the output circuit of Fig. 19.

Fig. 24 is a block diagram showing a configuration example of a source driver in a modification of the embodiment.

Fig. 25 is a view showing the operation of the multiplexer circuit of Fig. 24.

Fig. 26 is a block diagram showing a configuration example of an electronic device in the embodiment.

AGND‧‧‧ analog grounding

C1‧‧‧First capacitive element

C2‧‧‧second capacitive element

CCS‧‧‧Auxiliary Capacitor Components

NEG‧‧‧ node

OP ₁ ‧‧‧Output circuit

OPC ₁ ‧‧‧Operation Amplifier

S0‧‧‧first input switch

S1‧‧‧second input switch

S2‧‧‧ feedback switch

S3-1‧‧‧First flip switch

S3-2‧‧‧second flip switch

S4‧‧‧ output switch

SC0~SC4‧‧‧ switch control signal

Vin‧‧‧Input voltage

Vout‧‧‧ output gray scale voltage

Claims (17)

A source driver for driving a source line of an optoelectronic device, and characterized by: a gray scale voltage generating circuit corresponding to gray scale data, and outputting gray scales of the first and second gray scale voltages And a source line driving circuit for driving the source line according to the first and second gray scale voltages; the source line driving circuit includes a Flip Around type sample and hold circuit, which is Output gray scale voltage between the first gray scale voltage and the second gray scale voltage is output to the source line; the flip type sample and hold circuit converts the first and second grays according to the order bit data of the gray scale data The voltage between the step voltages or the first gray scale voltage is output as the output gray scale voltage to the source line. The source driver of claim 1, wherein the flip type sampling and holding circuit comprises: an operational amplifier circuit; and a plurality of capacitive elements connected to an input of the operational amplifier circuit at one end; and electrically interrupting the operation during sampling a state in which the output of the amplifier circuit and the source line are electrically connected to the input and output of the operational amplifier circuit, and a charge corresponding to the first or second gray scale voltage is stored in each of the capacitor elements of the plurality of capacitor elements; During the holding period after the sampling period, the input and output of the operational amplifier circuit are electrically interrupted, and are stored and stored in the complex capacitive element. The output voltage of the operational amplifier circuit obtained by the charge to the output of the operational amplifier circuit is output to the source line. The source driver of claim 1, wherein the flip type sampling and holding circuit comprises: an operational amplifier circuit that supplies a given voltage to the non-inverting input terminal; and a feedback switch that is inserted into the inverting input terminal of the operational amplifier circuit Between the output of the operational amplifier circuit and the first to jth (j is an integer of 2 or more) capacitive element, one end of which is connected to the inverting input terminal; and the first to jth inverting switch, which is the p (1≦p≦j, p is an integer) the inverting switch is inserted between the other end of the p-th capacitive element and the output of the operational amplifier circuit; the first to jth input switches are connected at one end of the pth input switch The other end of the p-th capacitive element; and an output switch inserted between the output of the operational amplifier circuit and the source line; and the first end of each of the input switches of the first to jth input switches Or a second gray scale voltage; during the sampling period, when the first to jth inversion switches are turned off, the feedback switch is turned on, and the output switch is turned off, in the first to jth capacitive elements another side To any one of said first and second gray scale voltage; during the holding period of the sample, the first turned on by the The jth inverting switch outputs the output gray scale voltage between the first gray scale voltage and the second gray scale voltage obtained by turning off the feedback switch and turning on the output switch to the source line. The source driver of claim 3, wherein the gray scale voltage generating circuit according to the lowest output voltage of the voltage outputted to the source line is close to the highest potential voltage of the voltage output to the source line, The first and second gray scale voltages are sequentially outputted when the potential is high; when the output gray scale voltage is closer to the lowest potential voltage than the highest potential voltage, the gray scale voltage generating circuit outputs the first and second in order of low potential Gray scale voltage. In the source driver of claim 4, wherein the output gray scale voltage is closer to the highest potential voltage than the lowest potential voltage, the gray scale voltage on the high potential side is supplied to the first portion in the first and second gray scale voltages. In the state of any one of the first to jth capacitive elements, the first to jth input switches are performed by supplying the gray scale voltage on the low potential side to any one of the first to jth capacitive elements. Switch control. In the source driver of claim 4, wherein the output gray scale voltage is closer to the lowest potential voltage than the highest potential voltage, the gray scale voltage on the low potential side is supplied to the first portion in the first and second gray scale voltages. In the state of any one of the first to jth capacitive elements, the first to jth input switches are performed by supplying the gray scale voltage on the high potential side to any one of the first to jth capacitive elements. Switch control. The source driver of any one of claims 3 to 6, wherein the capacitance values of the respective capacitance elements of the first to jth capacitive elements are equal. The source driver according to any one of claims 2 to 6, wherein the auxiliary capacitor element is provided with one end supplied with a given voltage and the other end connected to the inverting input terminal of the operational amplifier circuit. The source driver of claim 8, wherein the auxiliary capacitance element is used as a dummy capacitance element formed in the capacitance element formation region. The source driver of claim 8, wherein each of the source driver blocks driving the source lines of the optoelectronic device comprises a plurality of source driver blocks, wherein the gray scale voltage generating circuit and the source line driving circuit are included Each of the source driver blocks has a capacitive element forming region forming the first to jth capacitive elements and the auxiliary capacitive element in a direction crossing the arrangement direction of the plurality of source driver blocks; the auxiliary capacitive element is as described above The boundary between the capacitive element forming regions is formed along a boundary opposite to a direction intersecting the aforementioned alignment direction. The source driver of claim 9, wherein each of the source driver blocks driving the source lines of the optoelectronic device comprises a plurality of source driver blocks, wherein the gray scale voltage generating circuit and the source line driving circuit are included Each of the source driver blocks has a capacitance element forming region forming the first to jth capacitive elements and the auxiliary capacitive element in a direction crossing the arrangement direction of the plurality of source driver blocks; The auxiliary capacitance element is formed along a boundary of a direction intersecting the arrangement direction in a boundary between the capacitance element formation regions. The source driver according to any one of claims 2 to 6, wherein the operational amplifier circuit performs an A-stage amplification operation during the sampling period, and performs an AB-stage amplification operation during the retention period. The source driver of any one of claims 2 to 6, wherein the operational amplifier circuit comprises: an operational amplifier that amplifies a difference value between an input of the operational amplifier circuit and an output of the operational amplifier circuit; a first driving transistor, which is disposed on the first power source side, controls a gate electrode according to a voltage of an output node of the operational amplifier; and a second driving transistor of a second conductivity type, which is coupled to the first driving power a crystal is disposed in series on the second power supply side; a capacitor is used for capacitively coupling the gate electrode of the first driving transistor and the gate electrode of the second driving transistor; and a charge supply circuit, which is sampled in the foregoing The electric charge is supplied to the gate electrode of the second driving transistor during the period, and the supply of electric charge to the gate electrode of the second driving transistor is stopped during the holding period. The source driver of claim 13, wherein the foregoing charge supply circuit comprises: a current generating circuit; and a switching circuit inserted into the current generating circuit and the capacitor One end is connected between the gate electrodes of the second driving transistor; and the switching circuit is switched on and off during the sampling period and is turned off during the holding period. The source driver of claim 14, wherein the current generating circuit comprises a current source transistor that supplies current to the drain thereof and the diode is connected; the switching circuit is inserted into the gate electrode of the current source transistor and one of the capacitors And between the gate electrodes of the foregoing second driving transistor. An optoelectronic device, comprising: a plurality of scan lines; a plurality of source lines; a plurality of pixels, wherein each of the scan lines of the plurality of scan lines and the source lines of the plurality of source lines are specific pixels; and driving The plurality of source lines are used as the source driver of any one of claims 1 to 15. An electronic device, comprising: the source driver according to any one of claims 1 to 15, a display panel driven by the source driver, and a power supply circuit for supplying a power source for driving the source driver Voltage.