KR100943774B1 - Source driver, electro-optical device, and electronic instrument - Google Patents

Abstract

It provides a source driver, an electro-optical device, and an electronic device capable of supplying a voltage to a source line with high accuracy by a small circuit size and rail-to-rail operation. The source driver for driving the source line of the electro-optical device includes a gradation voltage generation circuit corresponding to gradation data and outputting gradation voltages of the first and second gradation voltages, and based on the first and second gradation voltages. And a source line driver circuit for driving the source line. The source line driving circuit includes a flip-around sample hold circuit for outputting an output gray voltage between the first gray voltage and the second gray voltage to the source line.

LCD device, display driver, power circuit, gate driver, LCD panel, display controller, source driver

Description

Source drivers, electro-optical devices and electronics {SOURCE DRIVER, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT}

The present invention relates to a source driver, an electro-optical device, an electronic device and the like.

Background Art Conventionally, as a liquid crystal panel (electro-optical device) used for electronic devices such as mobile phones, an active liquid crystal panel using a simple matrix system and a switching element such as a thin film transistor (hereinafter referred to as TFT) are used. Matrix liquid crystal panels are known.

While the simple matrix method has the advantage of lowering power consumption compared to the active matrix method, it has a disadvantage in that it is difficult to multicolorize and display moving images. On the other hand, the active matrix system has the advantage of being suitable for multicoloring and moving picture display, but has the disadvantage of being difficult to reduce power consumption.

In recent years, in portable electronic devices such as mobile phones, demands for multicoloring and moving picture display have become stronger in order to provide high quality images. For this reason, the liquid crystal panel of the active matrix system has been used instead of the liquid crystal panel of the simple matrix system which has been used until now. In an active matrix liquid crystal panel, a signal supplied to a source line is written to a pixel selected by a gate line, thereby changing the transmittance of the pixel.

In recent years, the number of source lines of a liquid crystal panel increases while the screen size of a liquid crystal panel increases and the number of pixels increases, and the precision of the voltage applied to each source line is calculated | required. In addition, due to the demand for the weight reduction and miniaturization of battery-driven electronic devices incorporating liquid crystal panels, there is also a demand for lowering power consumption of source drivers for driving source lines of liquid crystal panels and reducing chip sizes of the source drivers. Therefore, the source driver is expected to have a simple structure and a high function.

For example, Patent Literature 1 and Patent Literature 2 disclose configurations for enabling rail-to-rail operation of an output circuit for driving a source line of a source driver, and supplying a voltage to the source line with high accuracy. have.

Patent Document 1: Japanese Patent Application Laid-Open No. 2005-175811

Patent Document 2: Japanese Patent Application Laid-Open No. 2005-175812

However, in the techniques disclosed in Patent Documents 1 and 2, each output circuit is equipped with an auxiliary circuit to control the driving capability to realize rail-to-rail operation. Therefore, it is necessary to mount an auxiliary circuit as an additional circuit, and there existed a problem that the circuit scale of a source driver became large. In addition, the size of the transistor has to be increased in order to suppress the variation in the voltage applied to the source line.

In addition, in order to supply the voltage with high accuracy to the source line, it was necessary to supply the source line with the voltage from the DAC which generates the gradation voltage corresponding to the gradation data as it is. For this reason, when the number of gradations increases, the number of gradation voltage signal lines also needs to be increased, resulting in a problem that the chip size increases.

In addition, in the general operational amplifier, it is necessary to consider the variation of the output voltage. Therefore, it was necessary to increase the size of the transistors constituting the operational amplifier and to suppress fluctuations in the output voltage.

One aspect of the present invention provides a source driver, an electro-optical device, and an electronic device having a small circuit scale and capable of supplying a voltage to a source line with high accuracy by rail-to-rail operation.

Another aspect of the present invention provides a source driver, an electro-optical device, and an electronic device having a small circuit scale and capable of supplying a voltage to a source line with high accuracy while suppressing fluctuations in an output voltage.

Further, another aspect of the present invention provides a source driver, an electro-optical device, and an electronic device capable of supplying a voltage to a source line with high precision, even though the number of gradation voltage signals is small even when the number of gradations increases.

MEANS TO SOLVE THE PROBLEM In order to solve the said subject, the present invention is a source driver for driving the source line of an electro-optical device, The gradation voltage generation circuit which responds to gradation data and outputs each gradation voltage of a 1st and 2nd gradation voltages, And a source line driver circuit for driving the source line based on the first and second gray voltages, wherein the source line driver circuit is configured to output an output gray voltage between the first gray voltage and the second gray voltage. The present invention relates to a source driver including a flip-around sample hold circuit output to a source line.

Here, the source driver may output the first gray voltage and the voltage on the coin as the output gray voltage, or may output the second gray voltage and the voltage on the coin.

According to the present invention, since the flip-around sample hold circuit is configured to generate an output gray voltage between the first and second gray voltages, a plurality of gray voltages can be generated in the output circuit with a very simple configuration. do. As a result, the kind of gradation voltage to generate | occur | produce can be reduced significantly. Thereby, the number of gradation voltage signal lines can be reduced, and the circuit scale of a gradation voltage generation circuit can also be reduced significantly. Since the gray scale voltage generating circuit is generally supplied with a high voltage, it is necessary to increase the transistor size, and the reduction in the circuit scale of the gray scale voltage generating circuit can greatly contribute to the reduction in the chip size of the source driver.

In addition, according to the flip-around sampling and hold circuit, the rail-to-rail operation can be performed without adding an auxiliary circuit or the like, so that the variation can be suppressed, so that the size of the transistor does not need to be increased. Therefore, it can contribute to reduction of the chip size of a source driver.

Further, according to the present invention, it is not necessary to output the gradation voltage generated by the gradation voltage generation circuit to the source line in order to set the gradation voltage applied to the source line, so that the configuration of the gradation voltage generation circuit can be miniaturized. In addition, according to the present invention, the gray scale voltage can be generated with high accuracy only by the output circuit. As a result, the configuration of the gradation voltage generation circuit can be simplified.

Further, in the source driver according to the present invention, the flip-around type sample hold circuit includes an operational amplifier circuit and a plurality of capacitive elements connected at one end thereof to an input of the operational amplifier circuit. In the state in which the output of the circuit and the source line are electrically cut off, the input and output of the operational amplifier circuit are electrically connected to each other to correspond to the first or second gray voltage to each of the capacitors of the plurality of capacitors. The operational amplification obtained by accumulating charge, electrically interrupting the input and output of the operational amplifier circuit in the hold period after the sampling period, and supplying the charge accumulated in the plurality of capacitors to the output of the operational amplifier circuit. The output voltage of the circuit can be output to the source line.

In the source driver according to the present invention, the flip-around type sample hold circuit includes an operational amplifier circuit to which a given voltage is supplied to a non-inverting input terminal, and between an inverting input terminal of the operational amplifier circuit and an output of the operational amplifier circuit. An inserted feedback switch, first to jth capacitors (j is an integer of 2 or more), one end of which is connected to the inverting input terminal, and a flip-around switch of p (1 ≦ p ≦ j, p is an integer) First to j th flip-around switches inserted between the other end of the p-th capacitive element and the output of the operational amplifier circuit, and the first to the first ends of the p-th input switch connected to the other end of the p-th capacitive element. and an output switch inserted between the j input switch and the output of the operational amplifier circuit and the source line, wherein the other end of each input switch of the first to jth input switches includes the first or the second switch. 2 gray-level voltages are supplied, and in the sampling period, the first to j th flip-around switches are turned off, the feedback switch is turned on, and the output switch is turned off. The one obtained by supplying any one of the first and second gray scale voltages, turning on the first to j th flip-around switch, turning off the feedback switch, and turning on the output switch in the hold period after the sampling period. An output gray voltage between the first gray voltage and the second gray voltage can be output to the source line.

According to any one of the inventions described above, since the charge accumulated in the plurality of capacitors is moved to the output side of the operational amplifier circuit, the output gray scale voltage can be accurately adjusted without being affected by the input offset voltage of the operational amplifier circuit. You can create it. Further, according to the present invention, the first and second gray scale voltages can be supplied to the first to j th capacitive elements in a simple configuration.

In the source driver according to the present invention, when the output gradation voltage is closer to the highest potential voltage of the voltage output to the source line than the lowest potential voltage of the voltage output to the source line, the gradation voltage generation circuit is configured to perform the operation. When the first and second gray voltages are output in the order of high potential, and the output gray voltage is closer to the lowest potential voltage than the highest potential voltage, the gray voltage generation circuit generates the first and second gray voltages. Can be output in descending order of potential.

In the source driver according to the present invention, when the output gray voltage is closer to the highest potential voltage than the lowest potential voltage, the gray level voltage at the high potential side of the first and second gray voltages is the first to jth. Switch control of the first to j th input switches such that the gray level voltage on the low potential side is supplied to any one of the first to j th capacitance elements while being supplied to any one of the capacitors. Can be done.

In the source driver according to the present invention, when the output gradation voltage is closer to the lowest potential voltage than the highest potential voltage, the gradation voltage on the low potential side of the first and second gradation voltages is the first to jth. Switch control of the first to j th input switches is performed such that the gray level voltage of the high potential side is supplied to any one of the first to j th capacitance elements while being supplied to one of the capacitors. I can do it.

According to any one of the above inventions, since the occurrence of leakage of the first to j-th flip-around switches can be suppressed, it is possible to avoid a situation where the voltage level of the output gradation voltage fluctuates.

In the source driver according to the present invention, the capacitance values of the respective capacitor elements of the first to j-th capacitors may be the same.

According to the present invention, it is possible to generate the output gray voltage between the first and second gray voltages with high accuracy and easily.

In addition, the source driver according to the present invention may include a storage capacitor device, to which a given voltage is supplied at one end and an inverting input terminal of the operational amplifier circuit is connected at the other end.

According to the present invention, the voltage variation of the inverting input terminal of the operational amplifier circuit can be suppressed to further stabilize the output gray voltage.

In the source driver according to the present invention, the auxiliary capacitor may be used as a dummy capacitor formed in the capacitor element formation region.

In the source driver according to the present invention, each source driver block for driving each source line of the electro-optical device includes a plurality of source driver blocks including the gradation voltage generating circuit and the source line driving circuit. The source driver block has a capacitor element forming region in which the first to j-th capacitors and the storage capacitors are formed in a direction that intersects an arrangement direction of the plurality of source driver blocks, and the storage capacitors include: It may be formed along the boundary which opposes and the direction which cross | intersects the said array direction among the boundary of a capacitor element formation area.

According to the present invention, the capacitance values of the first to j-th capacitive elements can be formed with high accuracy, while the storage capacitors can be formed without reducing the layout area.

In the source driver according to the present invention, the operational amplifier circuit can perform a class A amplification operation in the sampling period and perform an AB class amplification operation in the hold period.

In the source driver according to the present invention, the operational amplifier circuit includes an operational amplifier for amplifying a difference value between an input of the operational amplifier circuit and an output of the operational amplifier circuit, and an operational amplifier provided on the first power supply side. A first driving transistor of a first conductivity type whose gate electrode is controlled based on a voltage of an output node, a second driving transistor of a second conductivity type provided on the second power supply side in series with the first driving transistor, and A capacitor for capacitively coupling the gate electrode of the first driving transistor and the gate electrode of the second driving transistor, the charge is supplied to the gate electrode of the second driving transistor in the sampling period, and the second driving in the hold period. And a charge supply circuit for stopping supply of charge to the gate electrode of the transistor.

In the source driver according to the present invention, the charge supply circuit includes a current generation circuit, a switch circuit inserted between one end of the current generation circuit and the capacitor and a gate electrode of the second driving transistor, and the switch The circuit may be controlled to be switched on in the sampling period and off in the hold period.

In the source driver according to the present invention, the current generating circuit includes a current source transistor in which a current is supplied to a drain thereof and is diode-connected, and the switch circuit includes a gate electrode of the current source transistor, one end of the capacitor, and the It may be inserted between the gate electrode of the second driving transistor.

Here, in the general flip-around sampling hold circuit, the output load does not change even during the sampling period or the hold period. In contrast, in the source driver according to any one of the inventions above, it is necessary to drive the load of the source line of the electro-optical device in the hold period. Therefore, according to any one of the inventions above, the flip-around sampling and hold circuit drives the low load output in the sampling period and the high load output in the hold period, so that the source line is optimal for the source driver. The driving circuit can be provided. The circuit scale of the flip-around sampling hold circuit can be significantly reduced without affecting the function of the flip-around sampling hold circuit.

The present invention also provides a plurality of scan lines, a plurality of source lines, a plurality of pixels each of which is specified by each scan line of the plurality of scan lines and each source line of the plurality of source lines, and the plurality of source lines. An electro-optical device comprising a source driver as set forth in any one of the above.

According to the present invention, an electro-optical device having a small circuit scale and including a source driver capable of supplying a voltage to a source line with high accuracy by rail-to-rail operation can be provided. In addition, according to the present invention, an electro-optical device including a source driver capable of supplying a voltage to a source line with high accuracy while canceling an input offset voltage can be provided. According to the present invention, it is possible to provide an electro-optical device including a source driver capable of supplying a voltage to a source line with a high number of gradation voltage signal lines even when the number of gradations increases.

Moreover, this invention relates to the electronic device containing the source driver as described in any one of the above.

Moreover, this invention relates to the electronic device containing the electro-optical device as described above.

According to any one of the above inventions, an electronic device can be provided with a lighter weight and a smaller size while being able to set a gray scale voltage with high accuracy at a source line.

According to the present invention, the circuit scale is small and the voltage can be supplied to the source line with high accuracy while suppressing the fluctuation of the output voltage.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail using drawing. In addition, embodiment described below does not unduly limit the content of this invention described in the claim. In addition, not all of the structures described below are essential components of the present invention.

1. Liquid crystal device

1, the outline | summary of the structure of the active-matrix type liquid crystal device in this embodiment is shown. Here, the active matrix liquid crystal device will be described. However, the display driver of the present embodiment can be applied to other liquid crystal devices.

The liquid crystal device 10 includes a liquid crystal display (LCD) panel (a wide range of display panels, more broadly an electro-optical device) 20. The LCD panel 20 is an amorphous silicon liquid crystal panel, for example, formed on a glass substrate. On this glass substrate, a plurality of gate lines (scan lines) GL1 to GLM (M is an integer of 2 or more) arranged in a plurality of Y directions and extending in the X direction, and a source line (data arranged in a plurality of X directions and extending in the Y direction, respectively) Line) SL1-SLN (N is an integer of 2 or more) are arrange | positioned. In addition, the pixel region (1 ≤ m ≤ M, where m is an integer, is the same below) and the source line SLn (1 ≤ n ≤ N, n is an integer, is the same below) correspond to the pixel region ( Pixels), and thin film transistors (hereinafter referred to as TFTs) 22mn are disposed in the pixel region.

The gate of the TFT 22mn is connected to the gate line GLn. The source of the TFT 22mn is connected to the source line SLn. The drain of the TFT 22mn is connected to the pixel electrode 26mn. A liquid crystal (broadly an electro-optical element) is enclosed between the pixel electrode 26mn and the counter electrode 28mn which opposes it, and the liquid crystal capacitor (bly liquid crystal element) 24mn is formed. The transmittance of the pixel is changed in accordance with the applied voltage between the pixel electrode 26mn and the counter electrode 28mn. The counter electrode voltage Vcom is supplied to the counter electrode 28mn.

Such an LCD panel 20 is formed by, for example, bonding a first substrate on which a pixel electrode and a TFT are formed, and a second substrate on which an opposite electrode is formed, and encapsulating a liquid crystal as an electro-optic material between both substrates.

Therefore, the LCD panel 20 can be said to have the pixel electrode connected with a source line through TFT as a switch element. In addition, it can be said that the LCD panel 20 has a plurality of source lines, a plurality of switch elements, and a plurality of pixel electrodes to which each pixel electrode is connected through each source line and each switch element.

The liquid crystal device 10 includes a display driver (broadly a drive circuit) 90 for driving the LCD panel 20. The display driver 90 includes a source driver 30. The source driver 30 drives each source line of the source lines SL1 to SLN of the LCD panel 20 based on the grayscale data corresponding to each source line. The display driver 90 may include a gate driver (broadly a scan driver) 32. The gate driver 32 scans the gate lines GL1 to GLM of the LCD panel 20 within one vertical scanning period. The display driver 90 may have a configuration in which at least one of the source driver 30 and the gate driver 32 is omitted.

The liquid crystal device 10 may include a power supply circuit 94. The power supply circuit 94 generates a voltage necessary for driving the source line, and supplies them to the source driver 30. The power supply circuit 94 generates, for example, the power supply voltages VDDH and VSSH required for driving the source line of the source driver 30, and the voltage of the logic portion of the source driver 30.

In addition, the power supply circuit 94 generates a voltage required for scanning the gate line and supplies it to the gate driver 32.

The power supply circuit 94 also generates the counter electrode voltage Vcom. The power supply circuit 94 applies the counter electrode voltage Vcom which periodically repeats the high potential side voltage VCOMH and the low potential side voltage VCOML in accordance with the timing of the polarity inversion signal POL generated by the source driver 30. Output to the opposite electrode.

The liquid crystal device 10 may include a display controller 38. The display controller 38 includes the source driver 30, the gate driver 32, and the power supply circuit in accordance with contents set by a host such as a central processing unit (hereinafter, abbreviated as CPU) not shown. 94). For example, the display controller 38 supplies the source driver 30 and the gate driver 32 with the operation mode set and the internally generated vertical synchronization signal or horizontal synchronization signal.

In addition, in FIG. 1, although the power supply circuit 94 or the display controller 38 is comprised in the liquid crystal device 10, at least one of these may be provided outside the liquid crystal device 10, and may be comprised. . Alternatively, the liquid crystal device 10 may be configured to include a host.

In addition, the source driver 30 may incorporate at least one of the gate driver 32 and the power supply circuit 94.

In addition, some or all of the source driver 30, the gate driver 32, the display controller 38, and the power supply circuit 94 may be formed on the LCD panel 20. For example, in FIG. 2, a display driver 90 (source driver 30 and gate driver 32) is formed on the LCD panel 20. In this way, the LCD panel 20 includes a plurality of source lines, a plurality of gate lines, a plurality of switch elements in which each switch element is connected to each gate line of the plurality of gate lines, and each source line of the plurality of source lines, and a plurality of sources. It can be configured to include a source driver to drive the line. A plurality of pixels is formed in the pixel formation region 80 of the LCD panel 20.

3 shows an example of the configuration of the gate driver 32 of FIG. 1 or FIG. 2.

The gate driver 32 includes a shift register 40, a level shifter 42, and an output buffer 44.

The shift register 40 includes a plurality of flip flops in which each flip flop is provided corresponding to each gate line, and is sequentially connected. The shift register 40 keeps the start pulse signal STV in the flip flop in synchronization with the clock signal CPV, and sequentially shifts the start pulse signal STV to the adjacent flip flops in synchronization with the clock signal CPV. The clock signal CPV input here is a horizontal synchronizing signal, and the start pulse signal STV is a vertical synchronizing signal.

The level shifter 42 shifts the level of the voltage from the shift register 40 to the level of the voltage corresponding to the transistor capability of the liquid crystal element of the LCD panel 20 and the TFT. As this voltage level, the high voltage level of 20V-50V is needed, for example.

The output buffer 44 buffers the scan voltage shifted by the level shifter 42, outputs it to the gate line, and drives the gate line. The high potential side of the pulse-shaped scan voltage is the selection voltage, and the low potential side of the scan voltage is the non-selection voltage.

In addition, the gate driver 32 may scan a plurality of gate lines by selecting a gate line corresponding to the decoding result by the address decoder without scanning the gate lines using the shift register as shown in FIG.

4 is a block diagram of an example of the configuration of the source driver 30 in FIG. 1 or FIG. 2.

The source driver 30 includes an I / O buffer 50, a display memory 52, a line latch 54, a gray voltage generator 58, a digital / analog converter (DAC) (a broadly a gray voltage generator circuit). ), And a source line driver circuit 62.

The gray scale data D is input to the source driver 30 from the display controller 38, for example. The gradation data D is input in synchronization with the dot clock signal DCLK and buffered in the I / O buffer 50. The dot clock signal DCLK is supplied from the display controller 38.

The I / O buffer 50 is accessed by the display controller 38 or a host (not shown). The grayscale data buffered in the I / O buffer 50 is written into the display memory 52. The gray scale data read from the display memory 52 is output to the display controller 38 and the like after being buffered in the I / O buffer 50.

The display memory 52 includes a plurality of memory cells provided in correspondence with each output line to which each memory cell is connected to each source line. Each memory cell is specified by a row address and a column address. Each memory cell for one scan line is specified by a line address.

The address control circuit 66 generates row addresses, column addresses, and line addresses for specifying memory cells in the display memory 52. The address control circuit 66 generates row addresses and column addresses when writing the gray scale data to the display memory 52. That is, the gradation data buffered in the I / O buffer 50 is written into the memory cells of the display memory 52 specified by the row address and column address.

The row address decoder 68 decodes a row address and selects a memory cell of the display memory 52 corresponding to the row address. The column address decoder 70 decodes a column address and selects a memory cell of the display memory 52 corresponding to the column address.

When the gray scale data is read from the display memory 52 and output to the line latch 54, the address control circuit 66 generates a line address. In other words, the line address decoder 72 decodes a line address and selects a memory cell of the display memory 52 corresponding to the line address. The gray level data for one horizontal scan read out from the memory cell identified by the line address is output to the line latch 54.

When the gray scale data is read from the display memory 52 and output to the I / O buffer 50, the address control circuit 66 generates row addresses and column addresses. In other words, the gradation data held in the memory cells of the display memory 52 specified by the row address and column address is read into the I / O buffer 50. The gray scale data read into the I / O buffer 50 is taken out by the display controller 38 or a host (not shown).

Therefore, in FIG. 4, the row address decoder 68, the column address decoder 70, and the address control circuit 66 function as a write control circuit for performing write control of the gray scale data to the display memory 52. As shown in FIG. 4, the line address decoder 72, the column address decoder 70, and the address control circuit 66 function as read control circuits for performing read control of the gray scale data from the display memory 52. As shown in FIG.

The line latch 54 latches gradation data for one horizontal scan read from the display memory 52 at the timing of change of the latch pulse LP that defines one horizontal scan period. The line latch 54 includes a plurality of registers in which each register holds grayscale data for one dot. In each register of the plurality of registers of the line latch 54, one-dot grayscale data read from the display memory 52 is received.

The gray voltage generator circuit 58 generates a plurality of gray voltages in which each gray voltage (reference voltage) corresponds to each gray data. More specifically, the gradation voltage generating circuit 58 generates a plurality of gradation voltages in which each gradation voltage corresponds to the gradation data based on the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH.

The DAC 60 generates a gradation voltage corresponding to the gradation data for one horizontal scan from the line latch 54 for each source output. More specifically, the DAC 58 is a gray level corresponding to each source line among gray level data from the line latch 54 among the plurality of gray voltages generated by the gray voltage generation circuit 58. A gray voltage corresponding to the data is selected, and the selected gray voltage is output. Such a DAC 60 includes voltage selection circuits DEC ₁ to DEC _{N provided} for each source output. Each voltage selection circuit outputs one gray voltage corresponding to each gray data among the plurality of gray voltages from the gray voltage generator circuit 58.

The source line driver circuit 62 includes the output circuits OP ₁ to OP _N. Each output circuit of the output circuits OP ₁ to OP _N includes an operational amplifier circuit, performs impedance conversion using the output gray voltage from each voltage selection circuit of the DAC 60 to drive the source line.

2. Configuration example of the source driver

In this embodiment, in order to reduce the circuit scale of the source driver block provided for each source output, each output circuit of the source line driver circuit 62 is provided with a flip-around sample hold circuit. Then, a voltage is supplied to the source line by the flip-around sample hold circuit. More specifically, receiving the first and second gray voltages output by the DAC 60, the flip-around sample hold circuit outputs an output gray voltage between the first gray voltage and the second gray voltage to the source line. do.

Here, the output circuit of the source line driver circuit 62 including such a flip-around sample hold circuit will be described.

Figure 5 shows a configuration example of a circuit diagram of the output circuit OP ₁ of the source line driving circuit 62, the.

5, the output circuit showing the configuration of OP _1, but with the configuration of another output circuit OP ₂ and OP _N similar to the output circuit 0P _1. In addition, although FIG. 5 shows the example which produces | generates two types of output gray voltage between a 1st and 2nd gray voltage, this invention is not limited to the kind of output gray voltage.

In FIG. 5, the first and second gray voltages are supplied as the input voltage Vin from the DAC 60, and the output gray voltage Vout is supplied to the source line.

By plural kinds of output gradation voltages generated in the output circuit, the kind of gradation voltages generated by the gradation voltage generation circuit 58 can be reduced. Therefore, the number of gradation voltage signal lines can be greatly reduced, and the circuit scale of the DAC 60 can also be significantly reduced. For example, when the source driver 30 drives a source line based on 6-bit grayscale data, the grayscale voltage generating circuit essentially needs to generate 64 (= 2 ⁶ ) kinds of grayscale voltages. . By the way, since each output circuit of the source line driver circuit 62 shown in FIG. 5 can generate two types of gray voltages, the gray voltage voltage generating circuit 58 should just be able to generate 32 types of gray voltages. . Therefore, the number of gray voltage signal lines is also sufficient, for example, 32, so that the wiring area of the gray voltage signal lines can be halved. In fact, in the present embodiment, since the output circuit generates a voltage obtained by dividing the first and second gray voltages, 33 gray voltage signal lines are required.

Such an output circuit includes a flip-around sample hold circuit. The operation of the flip-around sample hold circuit is different in the sampling period set in the first half of the one horizontal scanning period 1H and the hold period set in the second half. That is, the flip-around sample hold circuit supplies the charge accumulated in the sampling period to its output side in the hold period.

Such an output circuit includes an operational amplifier circuit and a plurality of capacitors whose one end is connected to the input of the operational amplifier circuit. The output circuit electrically connects the inputs and outputs of the operational amplifier circuits in a state in which the outputs of the operational amplifier circuits and the source lines are electrically disconnected during the sampling period, thereby connecting the first circuits to the respective capacitors of the plurality of capacitors. Alternatively, charges corresponding to the second gray voltage are accumulated. That is, in the sampling period, the output of the operational amplifier circuit and the source line are electrically cut off so as not to change the voltage of the source line. Charges corresponding to any one of the first and second gray scale voltages are accumulated at one end of the plurality of capacitors, and charges are supplied to the other ends of the plurality of capacitors by the driver of the output terminal of the operational amplifier circuit. do.

Next, in the subsequent hold period, the output circuit electrically cuts off the input and output of the operational amplifier circuit and supplies the charge accumulated in the plurality of capacitors to the output of the operational amplifier circuit. At this time, the output of the operational amplifier circuit and the source line are electrically connected. That is, in the hold period, the output of the operational amplifier circuit and the source line are electrically connected to supply the output gray voltage to the source line. Then, the input and output of the operational amplifier circuit are electrically cut off, and the charge accumulated in the plurality of capacitors is supplied to the output of the operational amplifier circuit. By doing so, the image discharge short function on the input side of the operational amplifier circuit which tries to make the input voltage equal to the output voltage is performed to charge and discharge the charge of the drive section of the operational amplifier circuit, thereby changing the output gray voltage.

More specifically, the output circuit OP ₁ includes the operational amplifier circuit OPC ₁ , the capacitors C1 to Cj of the first to jth (j is an integer of 2 or more), and the switches S3-1 for the first to jth fliparound. To S3-j and an output switch S4. The analog ground AGND (given voltage) is supplied to the non-inverting input terminal of the operational amplifier circuit OPC ₁ . When the high potential supply voltage of the operational amplifier circuit OPC ₁ is set to VDD and the low potential supply voltage is set to VSS, the analog ground AGND can be set to (VDD + VSS) / 2. One end of the first to j th capacitors C1 to Cj is connected to the inverting input terminal of the operational amplifier circuit OPC ₁ . The capacitance values of the first to j th capacitors C1 to Cj are the same. The flip-around switch S3-p of the pth (1 ≦ p ≦ j, p is an integer) is inserted between the other end of the pth capacitor Cp and the output of the operational amplifier circuit OPC ₁ . The output switch S4 is inserted between the output of the operational amplifier circuit OPC _{1 and} the output line electrically connected to the source line SL1. By supplying the first and second gray voltages to the first to j th capacitors C1 to Cj, the output circuit OP ₁ outputs an output gray voltage of the type 2 ^(j-1) between the first and second gray voltages. Can be generated.

In addition, the output circuit OP ₁ may also include first to j th input switches. One end of an input switch of p (1 ≦ p ≦ j, p is an integer) is connected to the other end of the pth capacitive element Cp. Then, the other end of each input switch of the first to jth input switches is supplied with a first or second gray scale voltage by time division.

Next, the case of FIG. 5 is demonstrated to an example about a more specific structure and operation | movement. 5 shows the case where j is two. The first input switch S0 is switched control (on off control) by the switch control signal SC0. The second input switch S1 is switched controlled by the switch control signal SC1. Feedback switch S2 is switched-controlled by switch control signal SC2. The first and second flip-around switches S3-1 and S3-2 are switch controlled by the switch control signal SC3. The output switch S4 is switched controlled by the switch control signal SC4. Such switch control signals SC0 to SC4 are generated by the control circuit of output circuit 0P _{1 (} not shown).

6 is an explanatory diagram of a first operation example of the output circuit OP ₁ of FIG. 5.

In the sampling period, the first gray voltage Vin1 and the second gray voltage Vin2 are supplied in time division. In the period in which the first gradation voltage Vin1 is supplied, the first input switch S0 is turned on, and in the subsequent sampling period and hold period, the switch is controlled to be off. In addition, the second input switch S1 is controlled to be turned on in a period in which at least the second gray voltage Vin2 is supplied. The second input switch S1 is controlled to be switched on in the sampling period and off in the hold period.

Feedback switch S2 is switch-controlled so that it may turn on in a sampling period and off in a hold period. The first and second flip-around switches S3-1 and S3-2 are switch controlled to be turned off in the sampling period and turned on in the hold period. The output switch S4 is controlled to be switched off in the sampling period and on in the hold period.

That is, in the sampling period, the first to second j th flip-around switches are turned off, the feedback switch S2 is turned on, and the output switch S4 is turned off. One of the two gradation voltages Vin1 and Vin2 is supplied. In the hold period after the sampling period, the output gray level between the first gray voltage Vin1 and the second gray voltage Vin2 is turned on by switching on the first to j th flip-around switches, turning off the feedback switch S2, and turning on the output switch S4. The voltage Vout is output to the source line.

More specifically, in FIG. 6, in the sampling period, charges corresponding to the first gradation voltage Vin1 are accumulated at one end of the first capacitor C1 through the first input switch S0. Further, charges corresponding to the second gray voltage Vin2 are accumulated at one end of the second capacitor C2 through the second input switch S1. In this period, since the feedback switch S2 is turned on, the operational amplifier circuit by a virtual short circuit capabilities of OPC _1, the operational amplifier circuits OPC ₁ of the inverting input terminal of the node NEG of the voltage and the operational amplifier circuits OPC ₁ of the output voltage is an analog It becomes ground AGND.

Therefore, in the sampling period, the charge Qs represented by the following expression is accumulated in the node NEG. At this time, since the output switch S4 is off, the voltage of the source line SL1 does not change.

Here, Vin1 is the first gray voltage, Vin2 is the second gray voltage, and the capacitance of each of the first and second capacitors C1 and C2 is C.

Next, in the hold period, the first and second input switches S0 and S1 and the feedback switch S2 are turned off, and the first and second flip-around switches S3-1 and S3-2 are turned on. As a result, the voltage corresponding to the charge accumulated in the first and second capacitors C1 and C2 is output as the output gray voltage of the operational amplifier circuit OPC ₁ . In this case, since one end of the first and second capacitors C1, C2 is short-circuited, the output gray voltage Vout is represented by the following equation.

7 is an explanatory diagram of a second operation example of the output circuit OP ₁ of FIG. 5.

In FIG. 6, the first and second capacitors were supplied to the first and second capacitors in the order of the highest potential among the first and second gray voltages. Supply to the device.

Also in this case, like FIG. 6, switch control of 1st and 2nd input switches S0, S1, feedback switch S2, 1st and 2nd flip-around switches S3-1, S3-2, and output switch S4 is performed. . Then, the output gray voltage Vout represented by the expression (2) is output in the hold period.

8 is an explanatory diagram of a third operation example of the output circuit OP ₁ of FIG. 5.

6 and 7 show an example in which the output gray voltage Vout is output as a voltage between the first gray voltage Vin1 and the second gray voltage Vin2, but the present invention is not limited thereto. By setting the first and second gray voltages Vin1 and Vin2 as the voltage on the coin, the output gray voltage Vout can also be set to the first and second gray voltages Vin1 and Vin2 and the voltage on the coin.

Also in this case, like FIG. 6, switch control of 1st and 2nd input switches S0, S1, feedback switch S2, 1st and 2nd flip-around switches S3-1, S3-2, and output switch S4 is performed. . As a result, from the expression (2), the output gray voltage Vout becomes the voltages of the first and second gray voltages Vin1 and Vin2 and coincidence, and this output gray voltage Vout is output in the hold period.

Since the source line is driven using the flip-around sampling and hold circuit as described above, a plurality of gray voltages can be generated in the output circuit with a very simple configuration. As a result, the type of the gradation voltage to be generated by the gradation voltage generation circuit 58 can be greatly reduced. Thereby, the number of gradation voltage signal lines can be reduced, and the circuit scale of the DAC 60 can also be significantly reduced. Since the DAC 60 is generally supplied with a high voltage, it is necessary to increase the transistor size, and the reduction in the circuit scale of the DAC 60 can greatly contribute to the reduction in the chip size of the source driver 30.

In addition, according to the flip-around sampling and hold circuit, the rail-to-rail operation can be performed without adding an auxiliary circuit or the like, and the variation is suppressed, so that the size of the transistor does not need to be increased. Therefore, it can contribute to reduction of the chip size of the source driver 30.

In addition, the flip-around-type sample-hold circuit of the above, the first and second capacitor C1, since the construction in which the charge stored in the C2 operational amplifier circuit moves to the output side of the OPC _1, the operational amplifier circuits OPC ₁ input offset having The output gradation voltage Vout can be generated with high accuracy without being affected by the voltage.

In addition, in the flip-around sampling and hold circuit described above, the gradation voltage applied to the source line is set with high precision, so that the gradation voltage generated by the DAC 60 does not need to be output to the source line. Can be generated with high precision. For this reason, it is not necessary to generate the gradation voltage with high accuracy in the DAC 60, so that the configuration of the DAC 60 can be simplified and the circuit scale of the DAC 60 can be reduced.

2.1 Comparative Example

By the way, in the flip-around sample hold circuit having the same configuration as in the present embodiment, the order of the switch control of the first to j-th input switches in the sampling period and the level of the gradation voltage input to each input switch are as follows. It is desirable to. That is, when the output gray voltage Vout is closer to the highest potential voltage of the voltage output to the source line than the lowest potential voltage of the voltage output to the source line, the DAC 60 (gradation voltage generation circuit) is shown in FIG. As described above, it is preferable to output the first and second gray voltages in the order of high potential. For example, among the 64 types of gray scale voltages V0 to V63, the highest potential voltage becomes V63 when the lowest potential voltage is set to V0, and the highest potential voltage becomes V0 when the minimum potential voltage is set to V63.

When the output gray voltage Vout is closer to the lowest potential voltage than the highest potential voltage, the DAC 60 (gradation voltage generation circuit) preferably outputs the first and second gray voltages in descending order of potential.

Accordingly, when the output gray voltage Vout is closer to the highest potential voltage than the lowest potential voltage when the first or second gray voltage is supplied to the other end of each input switch of the first to j th input switches, the first and second Among the gray scale voltages, the gray level voltage on the low potential side is among the first to jth capacitors C1 to Cj while the gray level voltage on the high potential side is supplied to any one of the first to j th capacitors C1 to Cj. It is preferable to perform switch control of the first to j-th input switches so as to be supplied to any one of the capacitor elements.

Further, when the first or second gray voltage is supplied to the other end of each input switch of the first to j th input switches, when the output gray voltage Vout is closer to the lowest potential voltage than the highest potential voltage, the first and second Of the gradation voltages, the gradation voltage on the high potential side is among the first to j-th capacitors C1 to Cj while the gradation voltage on the low potential side is supplied to any one of the first to j th capacitors C1 to Cj. It is preferable to perform switch control of the first to j-th input switches so as to be supplied to any one of the capacitive elements.

Here, the said reason is demonstrated, comparing with the comparative example of this embodiment.

9 is an explanatory diagram of an operation example of the output circuit OP ₁ in the comparative example of the present embodiment.

In FIG. 9, the same code | symbol is attached | subjected to the same part as FIG. 6 thru | or 8, and description is abbreviate | omitted suitably. In this comparative example, in the first half of the sampling period, the first gray voltage Vin1 is supplied to one end of the first capacitor C1 while the first input switch S0 is turned on and the second input switch S1 is turned off. In the second half of this sampling period, the second gray scale voltage Vin2 is supplied to one end of the second capacitor C2 with the first input switch S0 off and the second input switch on. In this comparative example, the potential of the first gray voltage Vin1 is lower than the potential of the second gray voltage Vin2.

10 is a view for explaining the operation of this comparative example.

In FIG. 10, the same code | symbol is attached | subjected to the same part as FIG. 5, and description is abbreviate | omitted suitably. In FIG. 10, the state in which the first input switch S0 is off and the second input switch S1 is on in the sampling period is illustrated.

For example, it is assumed that the first gradation voltage Vin1 of FIG. 9 is supplied to the first capacitor C1 while the first input switch S0 is on and the second input switch S1 is off (SQ1). At this time, charges corresponding to the first gradation voltage Vin1 are stored in the first capacitor C1. Next, as shown in FIG. 10, in the state where the first input switch S0 is off and the second input switch S1 is on, the second gray scale voltage Vin2 (Vin1 <Vin2) of FIG. 9 is applied to the second capacitor C2. It is assumed that it is supplied (SQ2). At this time, the charge corresponding to the second gray voltage Vin2 is stored in the second capacitor C2.

Here, with the application of the second gray voltage Vin2, the voltage level of the node NEG (the other end of the second capacitor C2) in which the charge corresponding to the first gray voltage Vin1 is accumulated varies. Since the other end of the first capacitor C1 and the other end of the second capacitor C2 are electrically connected, the change in the voltage level of the node NEG is transmitted as the change in the voltage level of one end of the capacitively coupled first capacitor C1. (SQ3).

In this case, the voltage variation of the node NEG is transmitted as the variation of the voltage level of one end of the first flip-around switch S3-1 through the first capacitor C1, and the voltage level becomes higher than the power supply voltage VDD. There is (SQ4). This means that leakage occurs because the diode connection portion between the source (drain) of the P-type MOS transistor constituting the switch and the substrate on which the transistor is formed is in the forward direction. Therefore, the voltage level of the output gray voltage Vout to be output in the hold period is changed.

Therefore, in this embodiment, after supplying the 1st gray-level voltage Vin1 of the high potential side from the beginning also to 2nd capacitive element C2, for example, the 2nd gray-level voltage Vin2 of the low potential side is supplied to the 2nd capacitor | condenser C2 again. The switch is controlled. By doing in this way, the situation where the fluctuation | variation in the voltage level of the 2nd capacitance element C2 is transmitted to the node NEG can be avoided.

That is, when the output gray voltage Vout is closer to the highest potential voltage than the lowest potential voltage, the gray level voltage on the high potential side of the first and second gray voltages is applied to any one of the first to jth capacitors C1 to Cj. In the supplied state, switch control of the first to j th input switches is performed so that the gray level voltage on the low potential side is supplied to any one of the first to j th capacitance elements C1 to Cj.

In addition, although the case where the output gradation voltage Vout was closer to the highest potential voltage than the lowest potential voltage was demonstrated in FIG. 9 and FIG. 10, the input switch is similarly applied also when the output gradation voltage Vout is closer to the lowest potential voltage than the highest potential voltage. Leak occurs. Therefore, when the output gradation voltage Vout is closer to the lowest potential voltage than the highest potential voltage, the gradation voltage on the low potential side of the first and second gradation voltages is the capacitance of any of the first to j-th capacitors C1 to Cj. In the state supplied to the element, it is preferable to perform the switch control of the first to j th input switches so that the gray level voltage on the high potential side is supplied to any one of the first to j th capacitance elements C1 to Cj.

Here, in order to determine with a simple configuration whether the output gray voltage Vout is close to the highest potential voltage or the lowest potential voltage of the gray voltage, it may be determined based on the most significant bit of the gray scale data.

Fig. 11 shows an explanatory diagram of the output order of the gradation voltages in the present embodiment.

For example, it is assumed that the gradation voltage whose most significant bit of the gradation data corresponds to "0" is higher than the gradation voltage whose most significant bit corresponds to "1". At this time, when the most significant bit of the gray scale data is "0", the gray voltage on the high potential side among the first and second gray voltages is supplied to the first capacitor C1, and then the gray voltage on the low potential side is supplied to the second capacitor C2. To feed. When the most significant bit of the gray scale data is "1", the gray level voltage on the low potential side among the first and second gray voltages is supplied to the first capacitor C1, and then the gray level voltage on the high potential side is supplied to the second capacitor C2. To feed. By doing this, it is possible to avoid a situation in which leakage occurs in the first and second flip-around switches S3-1 and S3-2, and the output gradation voltage Vout cannot generate the target voltage.

2. Composition of main part of 2 source driver

Next, an example of the configuration of main parts of the source driver 30 in the present embodiment will be described.

12 is a block diagram of a configuration example of a source driver block of the source driver 30 in the present embodiment. In FIG. 12, the same code | symbol is attached | subjected to the same part as FIG. 4, and description is abbreviate | omitted suitably. In the following description, it is assumed that grayscale data is 6 bits.

In FIG. 12, only the structure of the source driver block which drives the source line SL1 is shown. The source driver block for driving the source lines SL1, includes an addition circuit (80 _1), the addition control logic (82 _1), the voltage selection circuit DEC _1, output circuit OP _1.

In this embodiment, in order to supply the first and second gray scale voltages to the output circuit OP ₁ in time division, the gray scale data D [5: 0] is output from the display memory 52, and the gray scale data and the gray scale data are output. The incremented data is supplied to the voltage selection circuit DEC ₁ . At this time, the addition circuit (80 _1), the addition control is controlled based on the addition control signal ADD_BIT from the logic (82 _1), the gray-scale data increment allows the output data, as it can be printed or to the gray-scale data It is.

More specifically, the upper five bits of data D [5: 1] of the gradation data D [5: 0] are input to the adding circuit 80 ₁ . Further, the gray-scale data D [5: 0] of the data of the most significant bit D [5] and the least significant bit of the data D [0] is input to the addition control logic (82 _1). In addition control logic _{(82: 1),} added with the timing signal generated by the not-shown control circuit AD1, is AD2 is input, the gray-scale data D [5], on the basis of the data and the addition timing signal AD1, AD2 of D [0] The addition control signal ADD_BIT is generated.

13 is an explanatory diagram of the addition timing signals AD1 and AD2 in FIG. 12.

The period in which the addition timing signal AD1 is at the H level corresponds to the on period of the first input switch S0 supplied with the gray scale voltage to the first capacitor C1 of the output circuit OP ₁ . The period in which the addition timing signal AD2 is at the H level corresponds to the on period of the second input switch S1 supplied with the gray scale voltage to the second capacitor C2 of the output circuit OP ₁ .

In Figure 14 shows an operation explanation view of the added control logic (82 ₁₎ of Fig.

In FIG. 14, it is assumed that the gradation voltage becomes the highest potential when the gradation data [5: 0] is "000000", and the gradation voltage becomes the lowest potential when the gradation data is "111111".

Plus control logic (82 _1), the data of the most significant bit D [5] of the gray-scale data is carried out the addition when the control of the "0" days, added at the timing of the timing signal addition circuit AD2 (80 _1). At this time, when the data of the least significant bit D [0] of the grayscale data is "0", the addition circuit 80 ₁ outputs the data of the grayscale data D [5: 1] to the voltage selection circuit DEC ₁ as it is. In addition, when the data of the least significant bit D [0] of the grayscale data is "1", the addition circuit 80 ₁ increments the grayscale data D [5: 1] (gradation data D [5: 1). ] Is added to the voltage selection circuit DEC ₁ ).

Also, the addition line control of the addition control logic (82 _1), when the data of the most significant bit D [5] of one gray-scale data is "1" added at the timing of the addition signal AD1 timing circuit (80 _1). At this time, when the data of the least significant bit D [0] of the grayscale data is "0", the addition circuit 80 ₁ outputs the data of the grayscale data D [5: 1] to the voltage selection circuit DEC ₁ as it is. In addition, when the data of the least significant bit D [0] of the grayscale data is "1", the addition circuit 80 ₁ outputs the data incrementing the grayscale data D [5: 1] to the voltage selection circuit DEC ₁ . do.

In Figure 12, the output of the adder circuit (80 ₁₎ controlled by the control logic Thus the addition (82 _1), as the gray-scale data voltage selection circuit is input to DEC _1. The voltage selection circuit DEC ₁ outputs any one of the gray voltages V0 to V32 generated by the gray voltage generator circuit 58 to the output circuit OP ₁ based on the gray data from the adder circuit 80 ₁ . The output circuit is OP _1, has a structure of FIG.

2. 3 auxiliary capacitance elements

In this embodiment, as shown in FIG. 5, it is preferable to connect the storage capacitor CCS to the node NEG. For example, the storage capacitor CCS is supplied with a ground power supply voltage VSS or an analog ground AGND at one end thereof, and a node NEG is connected to the other end thereof. In this way, the voltage variation of the inverting input terminal of the operational amplifier circuit OPC ₁ can be suppressed, and further stabilization of the output gradation voltage Vout can be realized.

In addition, since the storage capacitor CCS is intended to suppress potential fluctuations, the capacitance value does not need to be formed with high accuracy as compared with the first and second capacitors C1 and C2. Therefore, in the capacitor element formation region in which the storage capacitor elements CCS and the first and second capacitors C1 and C2 are formed, the storage capacitor element CCS is compared with the first and second capacitors C1 and C2, such as etching. It is preferable to form in the area | region which is difficult to control when forming a capacitor | condenser. Therefore, it is preferable that the storage capacitor element CCS be combined with the capacitor element for dummy formed in the capacitor element formation region in the source driver.

15A and 15B show explanatory diagrams of the storage capacitor CCS.

15A illustrates a layout image of the source driver 30. In the source driver 30, the source driver blocks SB1 to SBN are arranged in the arrangement direction of the output pads on the source line. Each source driver block includes a gradation voltage generation circuit, a voltage selection circuit and a source line driver circuit, and the layout arrangement of each source driver block is the same.

FIG. 15B shows an image of the capacitive element formation region of the source driver block SBn. The source driver block SBn is formed in a direction perpendicular to an array direction (intersection direction of the output pads) of the source driver blocks SB1 to SBN (intersecting direction). It has the capacitance element formation area CEA formed. At this time, it is preferable that the storage capacitor CCS is formed along the boundary of any one of two opposing boundary portions in a direction perpendicular to the arrangement direction (intersecting direction) among the boundaries of the capacitance element formation region CEA. . In general, a dummy capacitor for a dummy in the capacitor element formation region is formed at this boundary. In FIG. 15B, when the arrangement direction of the source driver blocks SB1 to SBN is DR1, one of the two sides EDn constituting the boundary of the source driver block SBn facing as the direction DR2 perpendicular to the array direction DR1 is along the side EDn. The storage capacitor CCS is formed.

In this way, the edges (ends) of the first and second capacitors CS1 and CS2 are the edges of the storage capacitor CCS of the source driver block or the first or second capacitors C1 and C2 of the adjacent source driver block. Adjacent to the edge. Therefore, since the gaps Δd1 to Δd4 between the edges can be formed at almost the same etching rate, the first and second capacitors C1 and C2 can be formed with high accuracy. In contrast, the edge of the storage capacitor CCS is not adjacent to the edge of the other capacitor. Therefore, regarding the edge of the storage capacitor CCS, for example, since the etching rate from the output pad arrangement region side is different from the etching rate from the first or second capacitor elements C1 and C2, the first and the second Capacitive elements cannot be formed with accuracy compared to the two capacitors C1 and C2.

By forming each capacitor as shown in Fig. 15B, the capacitance values of the first and second capacitors C1 and C2 can be formed with high accuracy, while the storage capacitor CCS is not used without any layout area. It can be formed.

2. 4 operational amplifier circuits

It is preferable that the circuit scale of the flip-around sampling hold circuit in this embodiment is small. Therefore, it should be noted that the flip-around sampling and hold circuit in this embodiment performs discrete operations in the sampling period and the hold period, and the operational amplifier circuit applied to the flip-around sampling and hold circuit is described below. It is preferable to employ a configuration.

The flip-around sampling hold circuit in this embodiment drives the output of the low load by turning off the output switch S4 in the sampling period, and drives the output of the high load by turning on the output switch S4 in the hold period. Therefore, the operational amplifier circuit of the flip-around sampling hold circuit in this embodiment may perform the class A amplification operation in the sampling period and the AB class amplification operation in the hold period. Therefore, in this embodiment, the following structures can be adopted as the operational amplifier circuits OPC ₁ to OPC _N.

16, shows a configuration example of a circuit diagram of the operational amplifier OPC ₁ of Fig.

In Figure 16, illustrating the structure of Example ₁ OPC operational amplifier circuit but may also have the same configuration as the other operational amplifier circuits OPC ₂ to OPC _N.

The operational amplifier circuit OPC ₁ includes a differential amplifier 110 (broadly an operational amplifier), an output unit 120, a capacitor CCP, and a charge supply circuit 130. The differential amplifier 110 amplifies the difference between the input voltage VIN and the output voltage VOUT. The output unit 120 is provided on the first power supply side supplying the analog power supply voltage AVDD and the P-type driving transistor whose gate electrode is controlled based on the voltage of the output node NDD of the differential amplifier 110 (of the first conductivity type). The first drive transistor PTR1 and the N-type drive transistor (second drive transistor of the second conductivity type) NTR1 provided on the second power supply side supplying the analog ground AGND in series with the P-type drive transistor PTR1. The capacitor CCP is provided to capacitively couple the gate electrode of the P-type driving transistor PTR1 and the gate electrode of the N-type driving transistor NTR1.

The charge supply circuit 130 supplies charge to the gate electrode of the N-type driving transistor NTR1 in the sampling period, and stops supply of charge to the gate electrode of the N-type driving transistor NTR1 in the hold period. By doing so, in the sampling period, the P driving transistor PTR1 and the N driving transistor NTR1 are operated on the basis of the voltage of the output node NDD of the differential amplifier 110, so that the output voltage VOUT of the operational amplifier circuit 100 is also brought to the high potential side. It can also be changed to the low potential side. In the hold period, the output voltage VOUT is output depending on the voltage of the gate electrode of the P-type driving transistor PTR1. Therefore, the configuration of the operational amplifier circuit OPC ₁ which performs the class A amplification operation in the sampling period and performs the AB class amplification operation in the hold period can be simplified.

17 shows a circuit diagram of an example of the configuration of the operational amplifier circuit OPC ₁ in FIG. 16.

However, in FIG. 17, the same code | symbol is attached | subjected to the same part as FIG. 16, and description is abbreviate | omitted suitably.

The differential amplifier 110 includes a current mirror circuit CM1, a differential pair DIF1, and a current source CS1. The current mirror circuit CM1 includes the P-type transistors PTR10 and PTR11 to which the analog power supply voltage AVDD is supplied to its source. The gate electrode of the P-type transistor PTR10 and the gate electrode of the P-type transistor PTR11 are connected. The gate electrode and the drain of the P-type transistor PTR11 are connected.

The differential pair DIF1 includes the N-type transistors NTR10 and NTR11. The source of the N-type transistor NTR10 and the source of the N-type transistor NTR11 are connected. The drain of the N-type transistor NTR10 is connected to the drain of the P-type transistor PTR10. The drain of the N-type transistor NTR11 is connected to the drain of the P-type transistor PTR11. The analog ground AGND is supplied to one end of the current source CS1, and the other end of the current source CS1 is connected to the sources of the N-type transistors NTR10 and NTR11.

In such a differential amplifier 110, the input voltage VIN is supplied to the gate electrode of the N-type transistor NTR10, and the output voltage VOUT is supplied to the gate electrode of the N-type transistor NTR11. The connection node to which the drain of the P-type transistor PTR10 and the drain of the N-type transistor NTR10 are connected is the output node NDD of the differential amplifier 110. This output node is connected to the gate electrode of the P-type driving transistor PTR1 of the output unit 120.

In the charge supply circuit 130, a current source transistor CTR connected with a diode and connected to a drain thereof is connected to a gate electrode of the current source transistor CTR at one end thereof, and the other end of the capacitor CCP and the N-type driving transistor NTR1 at the other end thereof. And a switch circuit SWT to which the gate electrode is connected. The switch circuit SWT is switched controlled by the switch control signal STC. The charge supply circuit 130 may further include a current source CS2 connected to the drain of the current source transistor CTR and generating a constant current.

18 is a diagram illustrating the operation of the switch control signal of the sampling and holding circuit to which the operational amplifier circuit of FIG. 17 is applied.

In FIG. 18, the operation of the switch circuit SWT of FIG. 17, together with the first and second input switches S0 and S1, the feedback switch S2, the first and second flip-around switches S3-1 and S3-2, and the output switch S4. An example is shown. As shown in FIG. 18, the switch circuit SWT of FIG. 17 is switched-controlled so that it may turn on in a sampling period and off in a hold period by the switch control signal STC produced | generated by the control circuit which is not shown in figure.

In the operational amplifier circuit OPC ₁ of FIG. 17, the voltage of the gate electrode of the N-type driving transistor NTR1 also changes in accordance with the change of the voltage of the gate electrode of the P-type driving transistor PTR1 through the capacitor CCP. In the charge supply circuit 130, the voltage of the gate electrode of the P-type driving transistor PTR1 is changed while the electric charge is accumulated in the gate electrode of the N-type driving transistor NTR1 by the current source transistor CTR while the switch circuit SWT is turned on in the sampling period. Is transferred to the gate electrode of the N-type driving transistor NTR1. In the charge supply circuit 130, the switch circuit SWT is turned off in the hold period, and the change of the voltage of the gate electrode of the P-type driving transistor PTR1 is transmitted to the gate electrode of the N-type driving transistor NTR1.

Consider the case where the input voltage VIN is higher than the output voltage VOUT in the differential amplifier 110 of the operational amplifier circuit OPC _{1 having} such a configuration. In this case, the voltage at the output node NDD is lowered and the voltage at the drain of the N-type transistor NTR11 is increased. As a result, the voltage of the gate electrode of the P-type driving transistor PTR1 is lowered, and the P-type driving transistor PTR1 is turned in the on direction. Here, when the voltage of the gate electrode of the P-type driving transistor PTR1 is lowered, the voltage of the gate electrode of the N-type driving transistor NTR1 is also lowered.

On the other hand, consider the case where the input voltage VIN is lower than the output voltage VOUT in the differential amplifier 110. In this case, the voltage of the output node NDD is increased, and the voltage of the drain of the N-type transistor NTR11 is decreased. As a result, the voltage of the gate electrode of the P-type driving transistor PTR1 becomes high, and the P-type driving transistor PTR1 is turned in the direction of turning off. Here, when the voltage of the gate electrode of the P-type driving transistor PTR1 increases, the voltage of the gate electrode of the N-type driving transistor NTR1 also increases.

As a result of the above operation, the operational amplifier circuit OPC ₁ shifts to an equilibrium state where the input voltage VIN and the output voltage VOUT are almost coincidence.

In addition, the operational amplifier circuit OPC ₁ of FIG. 16 is not limited to the structure of FIG. For example, in Fig. 16, considering a power supply for supplying the analog ground AGND as the first power supply, a power supply for supplying the analog power supply voltage AVDD as the second power supply, an N type as the first conductivity type, and a P type as the second conductivity type. It consists of:

19 is a circuit diagram of another configuration example of the operational amplifier circuit of FIG. 16.

In this case, the output unit 120 is connected in series with the N-type driving transistor NTR2 whose gate electrode is controlled based on the voltage of the output node of the differential amplifier 110 provided on the first power supply side, and the N-type driving transistor NTR2. P type driving transistor PTR2 provided on the second power supply side.

The differential amplifier 110 of the operational amplifier circuit shown in FIG. 19 includes a current mirror circuit CM10, a differential pair DIF10, and a current source CS10. The current mirror circuit CM10 includes the N-type transistors NTR40 and NTR41 to which analog ground AGND is supplied to the source. The gate electrode of the N-type transistor NTR40 and the gate electrode of the N-type transistor NTR41 are connected. The gate electrode and the drain of the N-type transistor NTR41 are connected.

The differential pair DIF10 includes the P-type transistors PTR40 and PTR41. The source of the P-type transistor PTR40 and the source of the P-type transistor PTR41 are connected. The drain of the P-type transistor PTR40 is connected to the drain of the N-type transistor NTR40. The drain of the P-type transistor PTR41 is connected to the drain of the N-type transistor NTR41. An analog power supply voltage VDD is supplied to one end of the current source CS10, and the other end of the current source 10 is connected to the sources of the P-type transistors PTR40 and PTR41.

In such a differential amplifier 110, the input voltage VIN is supplied to the gate electrode of the P-type transistor PTR40, and the output voltage VOUT is supplied to the gate electrode of the P-type transistor PTR41. The connection node to which the drain of the N-type transistor NTR40 and the drain of the P-type transistor PTR40 are connected is the output node NDD of the differential amplifier 110. This output node is connected to the gate electrode of the N-type driving transistor NTR2 of the output unit 120.

The charge supply circuit 130 is connected to a current source transistor CTR10 having a current supplied to its drain and diode-connected, a gate electrode of the current source transistor CTR10 connected to one end thereof, and one end of the capacitor CCP and the other end of the P-type driving transistor PTR2 connected to the other end thereof. And a switch circuit SWT to which the gate electrode is connected. The charge supply circuit 130 may further include a current source CS20 connected to the drain of the current source transistor CTR10 and generating a constant current.

Such operational amplifier circuits OPC operation ₁ of the configuration shown in FIG. 19, a description thereof will be omitted because it is similar to the operation of the operational amplifier circuit OPC ₁ shown in Fig.

2.5 Modifications of the Output Circuit

In the present embodiment, the output circuit of the source line driver circuit 62 has been described as generating two kinds of gray voltages between the first and second gray voltages. Four types of gray voltages are generated between the second gray voltages. That is, in the description of FIG. 5, the configuration example where j is 4 is the configuration of the present modification.

Figure 20 shows a configuration example of a circuit diagram of the output circuit OP ₁ of the present embodiment of the modification of the source line driving circuit 62 on.

In FIG. 20, the same code | symbol is shown in the same part as FIG. 5, and description is abbreviate | omitted suitably. In addition, in FIG. 20, the 1st-4th input switches SI1-SI4 are provided, and the 1st-4th flip-around switches S3-1-S3-4 are provided. The capacitance values of the first to fourth capacitors C1 to C4 are the same.

21A and 21B show explanatory diagrams of a first operation example of the output circuit OP ₁ of FIG. 20.

In FIGS. 21A and 21B, between the first and second gray voltages when the lower two bits of data D [1: 0] of the grayscale data D [5: 0] are "00". An example of outputting 4.0 V as the output gray voltage is shown. As shown in Fig. 21A, in the case of applying 4.0 V as the first gray voltage Vin1 and 3.8 V as the second gray voltage Vin2 in the sampling period, through the first to fourth input switches SI1 to SI4. 4.0V is supplied to all of the first to fourth capacitors C1 to C4. As shown in Fig. 21B, in the hold period, 4.0V is output as the output gradation voltage Vout by supplying electric charge to the output side via the first to fourth flip-around switches S3-1 to S3-4. You can output

FIG. 22A and FIG. 22B show explanatory diagrams of a second operation example of the output circuit OP ₁ of FIG. 20.

In FIGS. 22A and 22B, between the first and second gray voltages when the lower two bits of data D [1: 0] of the grayscale data D [5: 0] are "01". An example of outputting 3.95 V as the output gray voltage is shown. As shown in Fig. 22A, in the case of applying 4.0 V as the first gray voltage Vin1 and 3.8 V as the second gray voltage Vin2 in the sampling period, through the first to fourth input switches SI1 to SI4. , 4.0V is supplied to three of the first to fourth capacitors C1 to C4, and 3.8V is supplied to the other one of the capacitors. And, as shown in Fig. 22B, in the hold period, the electric charge is supplied to the output side through the first to fourth flip-around switches S3-1 to S3-4, and according to the law of charge preservation, 3.95V can be output as an output gray voltage Vout.

FIG. 23A and FIG. 23B show explanatory diagrams of a third operation example of the output circuit OP ₁ of FIG. 20.

In FIGS. 23A and 23B, the first and second gray voltages when the lower two bits of data D [1: 0] of the grayscale data D [5: 0] are “10” The example which outputs 3.90V as an output gray scale voltage in between is shown. As shown in Fig. 23A, in the case of applying 4.0 V as the first gray voltage Vin1 and 3.8 V as the second gray voltage Vin2 in the sampling period, through the first to fourth input switches SI1 to SI4. , 4.0V is supplied to two of the first to fourth capacitors C1 to C4, and 3.8V is supplied to the remaining two capacitors. As shown in Fig. 23B, in the hold period, the electric charge is supplied to the output side through the first to fourth flip-around switches S3-1 to S3-4, according to the law of charge preservation. 3.90 V can be output as an output gray voltage Vout.

24A and 24B are explanatory diagrams of a fourth operation example of the output circuit OP ₁ in FIG. 20.

In FIGS. 24A and 24B, between the first and second gray voltages when the lower two bits of data D [1: 0] of the grayscale data D [5: 0] are "11". An example of outputting 3.85 V as the output gray voltage is shown. As shown in FIG. 24A, when 4.0 V is provided as the first gray voltage Vin1 and 3.8 V is provided as the second gray voltage Vin2 in the sampling period, the first through fourth input switches SI1 through SI4 are used. In addition, 4.0V is supplied to one of the first to fourth capacitors C1 to C4, and 3.8V is supplied to the remaining three capacitors. And, as shown in Fig. 24B, in the hold period, the electric charge is supplied to the output side through the first to fourth flip-around switches S3-1 to S3-4, according to the law of charge preservation. 3.85V can be output as an output gray voltage Vout.

3. Modifications of the source driver

The flip-around sampling and hold circuit in this embodiment can also be applied to the so-called multi-drive source driver output circuit.

25 is a block diagram of a configuration example of a source driver in a modification of the present embodiment. 25, the same code | symbol is attached | subjected to the same part as FIG. 4, and description is abbreviate | omitted suitably.

The source driver in this modification differs from the source driver in the present embodiment shown in FIG. 4 in that the multiplexing circuit 56 and the separating circuit 64 are provided, and constitute the DAC 60. The gradation data and the gradation voltage are supplied in time division for each source output to the output circuit constituting the voltage selection circuit and the source line driver circuit 62.

In FIG. 25, the multiplexing circuit 56 is provided between the line latch 54 and the DAC 60. The separation circuit 64 is provided on the output side of the source line driver circuit 62.

The multiplexing circuit 56 includes multiplexers MPX ₁ to MPX _k (where k is a positive integer), and each multiplexer receives grayscale data for one horizontal scan latched by the line latch 54, and q (q is positive). Generates multiplexed multiplexed data by time division for each integer number of q x k = N) sources.

FIG. 26 shows an operation explanatory diagram of the multiplexing circuit 56 of FIG. 25.

In FIG. 26, k is 240. In this case, each multiplexer generates time-division multiplexed multiplexed data for each 240 source outputs of grayscale data corresponding to each source output. The grayscale data GD ₁ to GD ₂₄₀ for the first to 240th source outputs received at the line latch 54 are multiplexed, for example, in the multiplexer MPX ₁ of the multiplexing circuit 56. Multiplexed control signals SEL1 to SEL240 that define time division timings are input to the multiplexers of the multiplexers MPX ₁ to MPX _k . Such multiplex control signals SEL1 to SEL240 are generated by a control circuit (not shown) of the source driver 30. This control circuit generates the multiplex control signals SEL1 to SEL240 so that, for example, the multiplex control signals of the multiplex control signals SEL1 to SEL240 become H level in order in one horizontal scanning period. During the period when each multiplex control signal is at the H level, grayscale data for source output corresponding to the multiplex control signal is output as multiplexed data.

The multiplexing circuit 56 may time-division-multiplex grayscale data in units of a plurality of pixels in which each pixel has a plurality of dots, and time-division multiplex the grayscale data unit in units of a plurality of dots of the same color component constituting each pixel. You may also do it. For example, when a pixel is composed of three dots of RGB, multiplexing data can be generated by time division multiplexing gray-scale data of each RGB for two pixels. For example, when the pixel is composed of three dots of RGB, the multiplexed data of the grayscale data of the R component of the pixels P1 to P6, the multiplexed data of the grayscale data of the G component, and the multiplexed data of the grayscale data of the B component are respectively generated. You may also do it.

In FIG. 25, the separation circuit 64 includes demultiplexers DMPX ₁ to DMPX _k , and each demultiplexer performs an operation opposite to the multiplexer of the multiplexing circuit 56 corresponding to the demultiplexer. That is, each demultiplexer separates the multiplexed gradation voltages from each output circuit of the source line driver circuit 62 into q source outputs and outputs them. The separation operation timing of the demultiplexer is synchronized with the time division timing of each multiplexer of the multiplexing circuit 56.

4. Electronic appliance

27 is a block diagram of a configuration example of the electronic device according to the present embodiment. Here, the block diagram of the structural example of a mobile telephone as an electronic device is shown. 27, the same code | symbol is attached | subjected to the same part as FIG. 1 or FIG. 2, and description is abbreviate | omitted suitably.

The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies data of an image captured by the CCD camera to the display controller 38 in YUV format.

The cellular phone 900 includes an LCD panel 20. The LCD panel 20 is driven by the source driver 30 and the gate driver 32. The LCD panel 20 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels.

The display controller 38 is connected to the source driver 30 and the gate driver 32, and supplies the gray scale data in RGB format to the source driver 30.

The power supply circuit 94 is connected to the source driver 30 and the gate driver 32, and supplies a driving power supply voltage to each driver. In addition, the counter electrode voltage Vcom is supplied to the counter electrode of the LCD panel 20.

The host 940 is connected to the display controller 38. The host 940 controls the display controller 38. In addition, the host 940 may demodulate the grayscale data received through the antenna 960 by the modulation / demodulation unit 950 and then supply the grayscale data to the display controller 38. The display controller 38 causes the LCD panel 20 to display the source driver 30 and the gate driver 32 based on the grayscale data.

The host 940 may instruct the demodulation unit 950 to modulate the grayscale data generated by the camera module 910, and then instruct transmission to another communication device through the antenna 960.

The host 940 performs transmission / reception processing of grayscale data, imaging of the camera module 910, and display processing of the LCD panel 20 based on the operation information from the operation input unit 970.

In addition, this invention is not limited to embodiment mentioned above, Various deformation | transformation implementation is possible within the scope of the summary of this invention. For example, the present invention is not limited to the above-mentioned driving of the liquid crystal display panel, but can be applied to the driving of an electroluminescence and plasma display device.

In addition, in the invention according to the dependent claims in the present invention, a configuration may be omitted in which a part of the configuration requirements of the dependent claims are omitted. It is also possible to subject the main part of the invention according to the independent claim of the present invention to another independent claim.

1 is a diagram illustrating a configuration example of a liquid crystal device in the present embodiment.

2 is a diagram illustrating another configuration example of the liquid crystal device in the present embodiment.

3 is a block diagram of a configuration example of a gate driver of FIG. 1;

4 is a block diagram of a configuration example of a source driver of FIG. 1 or FIG.

FIG. 5 is a circuit diagram of a configuration example of an output circuit of the source line driver circuit of FIG. 4. FIG.

6 is an explanatory diagram of a first operation example of the output circuit of FIG. 5;

7 is an explanatory diagram of a second operation example of the output circuit of FIG. 5;

8 is an explanatory diagram of a third operation example of the output circuit of FIG. 5;

9 is an explanatory diagram of a fourth operation example of the output circuit of FIG. 5;

10 is an operation explanatory diagram in this comparative example.

11 is an explanatory diagram of an output procedure of a gray voltage in the present embodiment.

12 is a block diagram of a configuration example of a source driver block of the source driver according to the present embodiment.

FIG. 13 is an explanatory diagram of an addition timing signal of FIG. 12. FIG.

14 is an explanatory diagram of the operation of the addition control logic of FIG. 12;

15 (A) and 15 (B) are explanatory diagrams of the storage capacitor CCS.

16 is a circuit diagram of an example of the configuration of the operational amplifier circuit of FIG. 5;

17 is a circuit diagram of an example of the configuration of the operational amplifier circuit of FIG. 16;

18 is an explanatory diagram of the operation of a switch control signal of a sampling hold circuit to which the operational amplifier circuit of FIG. 17 is applied;

19 is a circuit diagram of another configuration example of the operational amplifier circuit of FIG. 16;

20 is a circuit diagram of a configuration example of an output circuit of a source line driver circuit according to a modification of the present embodiment.

21A and 21B are explanatory diagrams of a first operation example of the output circuit of FIG. 20.

22A and 22B are explanatory diagrams of a second operation example of the output circuit of FIG. 20.

23A and 23B are explanatory diagrams of a third operation example of the output circuit of FIG. 20;

24A and 24B are explanatory diagrams of a fourth operation example of the output circuit of FIG. 20.

25 is a block diagram of a configuration example of a source driver in a modification of the present embodiment.

FIG. 26 is an operation explanatory diagram of the multiplexing circuit of FIG. 25;

27 is a block diagram of a configuration example of an electronic apparatus according to the present embodiment.

[Description of Symbols for Main Parts of Drawing]

10: liquid crystal device

20: LCD panel

30: Source Driver

32: gate driver

38: indicator controller

50: I / O buffer

52: display memory

54: line latch

58: gradation voltage generating circuit

60: DAC

62: source line driving circuit

66: address control circuit

68: row address decoder

70: column address decoder

72: line address decoder

80 ₁ : addition circuit

82 ₁ : addition control logic

90: display driver

94: power circuit

AGND: analog ground

CCS: auxiliary capacitor

C1: first capacitor

C2: second capacitive element

DEC _{1 to} DEC _N : voltage selection circuit

GL1 to GLM: gate line

NEG: Node

0PC ₁ : Operational Amplifier Circuit

0P _{1 to} 0P _N : output circuit

SC0 to SC4: switch control signal

SL1 to SLN: source line

S0: first input switch

S1: second input switch

S2: feedback switch

S3-1: switch for first flip-around

S3-2: switch for the second flip-around

S4: output switch

Vout: Output Gradient Voltage

Claims (20)

A source driver for driving a source line of an electro-optical device, A gradation voltage generation circuit corresponding to gradation data and outputting a first gradation voltage and a second gradation voltage; A source line driver circuit driving the source line based on the first gray voltage and the second gray voltage; The source line driving circuit, And a flip-around sample hold circuit for outputting an output gray voltage between the first gray voltage and the second gray voltage to the source line. The method of claim 1, The flip-around sample hold circuit, Operational amplifier circuit, A plurality of capacitors whose one end is connected to an input of said operational amplifier circuit, In the sampling period, while the output of the operational amplifier circuit and the source line are electrically disconnected, the input and the output of the operational amplifier circuit are electrically connected to each other, so that the first gray level is applied to each capacitor of the plurality of capacitors. A charge corresponding to a voltage or the second gray voltage is accumulated, In the hold period after the sampling period, an output voltage of the operational amplifier circuit obtained by electrically blocking inputs and outputs of the operational amplifier circuit and supplying charges accumulated in the plurality of capacitors to the output of the operational amplifier circuit is obtained. And outputting to the source line. The method of claim 1, The flip-around sample hold circuit, An operational amplifier circuit to which a given voltage is supplied to a non-inverting input terminal; A feedback switch inserted between the inverting input terminal of the operational amplifier circuit and the output of the operational amplifier circuit; A first to jth capacitor (j is an integer of 2 or more), one end of which is connected to the inverting input terminal; Flip-around switches of p (1 ≦ p ≦ j, p are integers) of the first to j-th capacitors inserted between the other end of the p-th capacitive element among the first-j capacitor elements and the output of the operational amplifier circuit; j switch for flip-around, First to j-th input switches of which one end of the p-th input switch is connected to the other end of the p-th capacitive element; An output switch inserted between the output of said operational amplifier circuit and said source line, The first gray voltage or the second gray voltage is supplied to the other end of each input switch of the first to j th input switches, In the sampling period, the first gray voltage and the first gray voltage at the other end of the first to jth capacitive elements, with the first to jth flip-around switches off, the feedback switch turned on, and the output switch off. Supply any one of the second gray voltages, In the hold period after the sampling period, an output gray voltage between the first gray voltage and the second gray voltage obtained by turning on the first to j th flip-around switches, turning off the feedback switch, and turning on the output switch. Outputting the source line to the source line. The method of claim 3, When the output gradation voltage is closer to the highest potential voltage of the voltage output to the source line than the lowest potential voltage of the voltage output to the source line, the gradation voltage generation circuit is configured to generate the first gradation voltage and the second gradation voltage. Output voltage in order of high potential, When the output gradation voltage is closer to the lowest potential voltage than the highest potential voltage, the gradation voltage generation circuit outputs the first gradation voltage and the second gradation voltage in descending order of potential; driver. The method of claim 4, wherein When the output gradation voltage is closer to the highest potential voltage than the lowest potential voltage, the gradation voltage on the high potential side of the first gradation voltage and the second gradation voltage is the capacitance of any one of the first to j-th capacitors. A source characterized in that the switch control of the first to j th input switches is performed such that the gray level voltage on the low potential side is supplied to any one of the first to j th capacitive elements while being supplied to the element. driver. The method of claim 4, wherein When the output gradation voltage is closer to the lowest potential voltage than the highest potential voltage, the gradation voltage on the low potential side of the first gradation voltage and the second gradation voltage is one of the first to j-th capacitors. A source characterized in that the switch control of the first to j th input switches is performed such that the gray level voltage on the high potential side is supplied to any one of the first to j th capacitance elements while being supplied to the capacitor. driver. The method according to any one of claims 3 to 6, And a capacitance value of each of the capacitors of the first to j-th capacitors is the same. The method according to any one of claims 2 to 6, And a storage capacitor provided with a voltage supplied at one end thereof and connected to an inverting input terminal of the operational amplifier circuit at the other end thereof. The method of claim 8, The storage capacitor, A source driver, which is used in combination with a capacitor for a dummy formed in the capacitor element forming region. The method according to any one of claims 3 to 6, An auxiliary capacitance element to which an analog ground voltage is supplied at one end and an inverting input terminal of the operational amplifier circuit is connected at the other end thereof; Each source driver block includes a plurality of source driver blocks for driving each source line of the electro-optical device, Each source driver block includes the gradation voltage generating circuit and the source line driving circuit, The first to jth capacitors and the storage capacitors are formed in a direction crossing the array direction of the plurality of source driver blocks; The storage capacitor, It is formed along the boundary of any one of the two boundary which opposes the direction of the said arrangement direction among the boundary of the capacitance element formation area | region where the said 1st thru | or jth capacitance element and the said auxiliary capacitance element are formed, It is characterized by the above-mentioned. Source drivers. The method according to any one of claims 2 to 6, The operational amplifier circuit, And a class A amplification operation during the sampling period, and a class A amplification operation during the hold period. The method according to any one of claims 2 to 6, The operational amplifier circuit, An operational amplifier for amplifying a difference value between an input of the operational amplifier circuit and an output of the operational amplifier circuit; A first driving transistor of a first conductivity type provided on a first power supply side and whose gate electrode is controlled based on a voltage of an output node of the operational amplifier; A second driving transistor of a second conductivity type provided on the second power supply side in series with the first driving transistor; A capacitor for capacitively coupling the gate electrode of the first driving transistor and the gate electrode of the second driving transistor; And a charge supply circuit for supplying charge to the gate electrode of the second driving transistor in the sampling period, and stopping supply of charge to the gate electrode of the second driving transistor in the hold period. . The method of claim 12, The charge supply circuit, With a current generating circuit, A switch circuit inserted between the current generating circuit and one end of the capacitor and the gate electrode of the second driving transistor, The switch circuit, And switch controlled to be on in the sampling period and off in the hold period. The method of claim 13, The current generating circuit, A current source transistor supplied with a current at the drain thereof and diode connected; The switch circuit, And a gate electrode interposed between the gate electrode of the current source transistor and one end of the capacitor and the gate electrode of the second driving transistor. A plurality of scan lines, A plurality of source lines, A plurality of pixels in which each pixel is specified by each scan line of the plurality of scan lines and each source line of the plurality of source lines; An electro-optical device comprising the source driver of any one of claims 1 to 6 for driving the plurality of source lines. An electronic device comprising the source driver of any one of claims 1 to 6. An electronic device comprising the electro-optical device of claim 15. A driver for driving an electro-optical device, A gray voltage generator for generating a first gray voltage and a second gray voltage; A sample hold circuit for supplying the charge accumulated on the input side in the sampling period to the output side in the hold period; The sample hold circuit, Operational amplifier circuit, A first capacitor connected at one end to an input of said operational amplifier circuit, A second capacitor connected to one end of the operational amplifier circuit; A first switch inserted between the other end of the first capacitor and the output of the operational amplifier circuit; A second switch inserted between the other end of the second capacitor and the output of the operational amplifier circuit; A third switch inserted between an input and an output of the operational amplifier circuit, The first gray voltage is supplied to the other end of the first capacitor. The second gray voltage is supplied to the other end of the second capacitor. In the sampling period, the third switch is turned on, the first switch and the second switch are turned off, In the hold period, the third switch is turned off, the first switch and the second switch are turned on, And the signal generated at the output side of the sample hold circuit is a signal supplied to the electro-optical device. delete delete

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