JP5332150B2 - Source driver, electro-optical device and electronic apparatus - Google Patents

Abstract

A source driver that drives a plurality of source lines of an electro-optical device includes a grayscale voltage generation circuit that outputs first and second grayscale voltages corresponding to grayscale data, and a source line driver circuit that drives a source line among the plurality of source lines based on the first and second grayscale voltages. The source line driver circuit includes a flip-around sample/hold circuit that outputs an output grayscale voltage between the first and second grayscale voltages to the source line.

Description

  The present invention relates to a source driver, an electro-optical device, and an electronic apparatus.

  Conventionally, as a liquid crystal panel (electro-optical device) used in an electronic device such as a mobile phone, an active matrix using a simple matrix type liquid crystal panel and a switching element such as a thin film transistor (hereinafter referred to as TFT). A liquid crystal panel of the type is known.

  The simple matrix method has an advantage that the power consumption can be easily reduced as compared with the active matrix method, but has a disadvantage that it is difficult to increase the number of colors and display a moving image. On the other hand, the active matrix method has an advantage that it is suitable for multi-color and moving image display, but has a disadvantage that it is difficult to reduce power consumption.

  In recent years, in portable electronic devices such as mobile phones, there is an increasing demand for multi-color and moving image display in order to provide high-quality images. For this reason, an active matrix type liquid crystal panel has been used instead of the simple matrix type liquid crystal panel used so far. In an active matrix liquid crystal panel, a signal given to a source line is written into a pixel selected by a gate line, thereby changing the transmittance of the pixel.

  In recent years, the number of source lines of a liquid crystal panel has been increased due to an increase in the screen size of the liquid crystal panel and an increase in the number of pixels. Furthermore, due to the demand for lighter and smaller battery-powered electronic devices equipped with a liquid crystal panel, lower power consumption of the source driver that drives the source line of the liquid crystal panel and reduction in the chip size of the source driver are also required. Yes. Therefore, a source driver with a simple configuration and high functionality is desired.

For example, Patent Document 1 and Patent Document 2 disclose a configuration that enables a rail-to-rail operation of an output circuit that drives a source line of a source driver, while supplying a voltage to the source line with high accuracy. Yes.
JP 2005-175811 A JP 2005-175812 A

  However, in the techniques disclosed in Patent Document 1 and Patent Document 2, each output circuit is equipped with an auxiliary circuit to control the driving capability and realize a Rail-to-Rail operation. Therefore, it is necessary to mount an auxiliary circuit as an additional circuit, and there is a problem that the circuit scale of the source driver becomes large. In addition, the size of the transistor has to be increased in order to suppress variations in voltage applied to the source line.

  Furthermore, in order to supply the voltage to the source line with high accuracy, it is necessary to supply the voltage from the DAC that generates the gradation voltage corresponding to the gradation data to the source line as it is. For this reason, when the number of gradations increases, it is necessary to increase the number of gradation voltage signal lines, which increases the chip size.

  In general operational amplifiers, it is necessary to consider variations in output voltage. For this reason, it is necessary to increase the size of the transistors constituting the operational amplifier and suppress variations in output voltage.

  One embodiment of the present invention provides a source driver, an electro-optical device, and an electronic device that have a small circuit scale and can supply a voltage to a source line with high accuracy by a rail-to-rail operation.

  Another embodiment of the present invention provides a source driver, an electro-optical device, and an electronic apparatus that have a small circuit scale and can supply a voltage to a source line with high accuracy while suppressing variations in output voltage.

  Furthermore, another aspect of the present invention provides a source driver, an electro-optical device, and an electronic apparatus that can supply a voltage to a source line with high accuracy while the number of gradation voltage signal lines is small even when the number of gradations is increased.

In order to solve the above problems, the present invention
A source driver for driving a source line of an electro-optical device,
A gradation voltage generation circuit for outputting each gradation voltage of the first and second gradation voltages corresponding to the gradation data;
A source line driving circuit for driving the source line based on the first and second gradation voltages,
The source line driving circuit is
The present invention relates to a source driver including a flip-around sample-and-hold circuit that outputs an output gradation voltage between the first gradation voltage and the second gradation voltage to the source line.

  Here, the source driver may output a voltage having the same potential as the first gradation voltage as the output gradation voltage, or may output a voltage having the same potential as the second gradation voltage.

  According to the present invention, since the output gradation voltage between the first and second gradation voltages is generated by the flip-around type sample and hold circuit, a plurality of gradation voltages can be obtained with a very simple configuration. Can be generated by the output circuit. As a result, the types of gradation voltages to be generated can be greatly reduced. As a result, the number of gradation voltage signal lines can be reduced, and the circuit scale of the gradation voltage generation circuit can be greatly reduced. Since the grayscale voltage generation circuit is generally supplied with a high voltage, it is necessary to increase the transistor size, and the reduction in the circuit scale of the grayscale voltage generation circuit can greatly contribute to the reduction in the chip size of the source driver.

  In addition, the flip-around sampling and holding circuit enables a Rail-to-Rail operation without adding an auxiliary circuit or the like, and eliminates the need to increase the transistor size in order to suppress variations. As a result, the chip size of the source driver can be reduced.

  Furthermore, according to the present invention, it is not necessary to output the gradation voltage generated by the gradation voltage generation circuit to the source line in order to set the gradation voltage to be applied to the source line, and the structure of the gradation voltage generation circuit can be reduced. Can be Further, according to the present invention, it is possible to generate the gradation voltage with high accuracy only by the output circuit. As a result, the configuration of the gradation voltage generation circuit can be simplified.

In the source driver according to the present invention,
The flip-around sample-and-hold circuit is
An operational amplifier circuit;
A plurality of capacitive elements having one end connected to the input of the operational amplifier circuit;
In the sampling period, with the output of the operational amplifier circuit and the source line electrically disconnected, the input and output of the operational amplifier circuit are electrically connected to each capacitive element of the plurality of capacitive elements. A charge corresponding to the first or second gradation voltage is accumulated;
In the hold period after the sampling period, the input and output of the operational amplifier circuit are electrically cut off, and the charge accumulated in the plurality of capacitive elements is supplied to the output of the operational amplifier circuit. The output voltage of the operational amplifier circuit can be output to the source line.

In the source driver according to the present invention,
The flip-around sample-and-hold circuit is
An operational amplifier circuit in which a given voltage is supplied to the non-inverting input terminal;
A feedback switch inserted between the inverting input terminal of the operational amplifier circuit and the output of the operational amplifier circuit;
First to jth (j is an integer of 2 or more) capacitive elements, one end of which is connected to the inverting input terminal;
P-th (1 ≦ p ≦ j, p is an integer) flip-around switch is inserted between the other end of the p-th capacitive element and the output of the operational amplifier circuit. Switches for
First to jth input switches in which one end of the pth input switch is connected to the other end of the pth capacitive element;
An output switch inserted between the output of the operational amplifier circuit and the source line,
The first or second gradation voltage is supplied to the other end of each of the first to jth input switches,
In the sampling period, the first and jth flip-around switches are turned off, the feedback switch is turned on, and the output switch is turned off. Supplying one of the second gradation voltages;
In the hold period after the sampling period, the first gradation voltage and the second gradation voltage obtained by turning on the first to jth flip-around switches, turning off the feedback switch, and turning on the output switch. An output gradation voltage between the two gradation voltages can be output to the source line.

  According to any one of the above inventions, since the charge accumulated in the plurality of capacitive elements is moved to the output side of the operational amplifier circuit, the output level is not affected by the input offset voltage of the operational amplifier circuit. The regulated voltage can be generated with high accuracy. Further, according to the present invention, the first and second gradation voltages can be supplied to the first to jth capacitive elements with a simple configuration.

In the source driver according to the present invention,
When the output gradation voltage is closer to the maximum potential voltage of the voltage output to the source line than the minimum potential voltage of the voltage output to the source line, the gradation voltage generation circuit includes the first and second voltages. Are output in descending order of potential,
When the output gradation voltage is closer to the lowest potential voltage than the highest potential voltage, the gradation voltage generation circuit can output the first and second gradation voltages in order of increasing potential.

In the source driver according to the present invention,
When the output gradation voltage is closer to the highest potential voltage than the lowest potential voltage, the gradation voltage on the high potential side of the first and second gradation voltages is the first to jth capacitive elements. The first to jth inputs so that the low-potential-side grayscale voltage is supplied to any one of the first to jth capacitive elements while being supplied to any one of the capacitive elements. Switch control of the switch can be performed.

In the source driver according to the present invention,
When the output gradation voltage is closer to the lowest potential voltage than the highest potential voltage, among the first and second gradation voltages, the gradation voltage on the low potential side is that of the first to jth capacitive elements. The first to jth inputs so that the high-potential-side gradation voltage is supplied to any one of the first to jth capacitive elements while being supplied to any one of the capacitive elements. Switch control of the switch can be performed.

  According to any one of the above-described inventions, the occurrence of leakage of the first to jth flip-around switches can be suppressed, so that the situation where the voltage level of the output gradation voltage fluctuates can be avoided. Become.

In the source driver according to the present invention,
The capacitance values of the capacitive elements of the first to jth capacitive elements may be equal.

  According to the present invention, an output gradation voltage between the first and second gradation voltages can be generated accurately and easily.

In the source driver according to the present invention,
An auxiliary capacitance element may be included in which a given voltage is supplied to one end and an inverting input terminal of the operational amplifier circuit is connected to the other end.

  According to the present invention, it is possible to suppress the voltage fluctuation of the inverting input terminal of the operational amplifier circuit and realize further stabilization of the output gradation voltage.

In the source driver according to the present invention,
The auxiliary capacitance element is
It may also be used as a dummy capacitor element formed in the capacitor element formation region.

In the source driver according to the present invention,
Each source driver block for driving each source line of the electro-optical device includes a plurality of source driver blocks including the gradation voltage generation circuit and the source line drive circuit,
Each source driver block
A capacitor element forming region in which the first to jth capacitor elements and the auxiliary capacitor element are formed in a direction intersecting an arrangement direction of the plurality of source driver blocks;
The auxiliary capacitance element is
Of the boundaries of the capacitive element forming regions, the capacitor elements may be formed along boundaries that face each other in a direction intersecting the arrangement direction.

  According to the present invention, the capacitance values of the first to jth capacitive elements can be formed with high accuracy, while the auxiliary capacitive element can be formed without wasting the layout area.

In the source driver according to the present invention,
The operational amplifier circuit includes:
A class A amplification operation can be performed during the sampling period, and a class AB amplification operation can be performed during the hold period.

In the source driver according to the present invention,
The operational amplifier circuit includes:
An operational amplifier for amplifying a difference value between an input of the operational amplifier circuit and an output of the operational amplifier circuit;
A first drive transistor of a first conductivity type provided on the first power supply side, the gate electrode of which is controlled based on the voltage of the output node of the operational amplifier;
A second drive transistor of a second conductivity type provided on the second power supply side in series with the first drive transistor;
A capacitor for capacitively coupling the gate electrode of the first driving transistor and the gate electrode of the second driving transistor;
A charge supply circuit that supplies charge to the gate electrode of the second drive transistor in the sampling period and stops supply of charge to the gate electrode of the second drive transistor in the hold period.

In the source driver according to the present invention,
The charge supply circuit comprises:
A current generation circuit;
A switch circuit inserted between the current generation circuit and one end of the capacitor and the gate electrode of the second drive transistor;
The switch circuit is
Switch control may be performed such that the sampling period is turned on and the holding period is turned off.

In the source driver according to the present invention,
The current generating circuit is
A current source transistor that is supplied with current to its drain and is diode-connected,
The switch circuit is
It may be inserted between the gate electrode of the current source transistor and one end of the capacitor and the gate electrode of the second driving transistor.

  Here, in a general flip-around sampling and holding circuit, the output load does not change regardless of the sampling period or the holding period. On the other hand, in the source driver according to any one of the inventions described above, it is necessary to drive the load of the source line of the electro-optical device during the hold period. Therefore, according to any one of the above-described inventions, the flip-around sampling and holding circuit drives a low-load output in the sampling period and drives a high-load output in the hold period. A drive circuit can be provided. The circuit scale of the flip-around sampling and holding circuit can be significantly reduced without affecting the function of the flip-around sampling and holding circuit.

The present invention also provides
A plurality of scan lines;
Multiple source lines,
A plurality of pixels each pixel is specified by each scanning line of the plurality of scanning lines and each source line of the plurality of source lines;
The present invention relates to an electro-optical device including any of the above-described source drivers for driving the plurality of source lines.

  According to the present invention, it is possible to provide an electro-optical device including a source driver having a small circuit scale and capable of supplying a voltage to a source line with high accuracy by a rail-to-rail operation. In addition, according to the present invention, it is possible to provide an electro-optical device including a source driver that has a small circuit scale and can supply a voltage to a source line with high accuracy while canceling an input offset voltage. Furthermore, according to the present invention, it is possible to provide an electro-optical device including a source driver that can supply a voltage to a source line with high accuracy while the number of gradation voltage signal lines is small even when the number of gradations is increased.

The present invention also provides
The present invention relates to an electronic device including any of the source drivers described above.

The present invention also provides
The present invention relates to an electronic apparatus including the electro-optical device described above.

  According to any one of the above inventions, a gradation voltage can be set to the source line with high accuracy, and a lightweight and miniaturized electronic device can be provided.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Liquid Crystal Device FIG. 1 shows an outline of the configuration of an active matrix liquid crystal device according to this embodiment. Here, an active matrix type liquid crystal device will be described, but the display driver in this embodiment can be applied to other liquid crystal devices.

  The liquid crystal device 10 includes a liquid crystal display (LCD) panel (display panel in a broad sense, electro-optical device in a broader sense) 20. The LCD panel 20 is an amorphous silicon liquid crystal panel, and is formed on a glass substrate, for example. On this glass substrate, a plurality of gate lines (scanning lines) GL1 to GLM (M is an integer of 2 or more) arranged in the Y direction and extending in the X direction, and a source line arranged in the X direction and extending in the Y direction, respectively. (Data lines) SL1 to SLN (N is an integer of 2 or more) are arranged. The pixel region corresponds to the intersection position of the gate line GLm (1 ≦ m ≦ M, m is an integer, the same applies hereinafter) and the source line SLn (1 ≦ n ≦ N, n is an integer, the same applies hereinafter). (Pixel) is provided, and a thin film transistor (hereinafter abbreviated as TFT) 22 mn is disposed in the pixel region.

  The gate of the TFT 22mn is connected to the gate line GLn. The source of the TFT 22mn is connected to the source line SLn. The drain of the TFT 22mn is connected to the pixel electrode 26mn. A liquid crystal (electro-optical element in a broad sense) is sealed between the pixel electrode 26mn and a counter electrode 28mn facing the pixel electrode 26mn, thereby forming a liquid crystal capacitor (a liquid crystal element in a broad sense) 24mn. The transmittance of the pixel changes according to the applied voltage between the pixel electrode 26mn and the counter electrode 28mn. The counter electrode voltage Vcom is supplied to the counter electrode 28mn.

  Such an LCD panel 20 includes, for example, a first substrate on which pixel electrodes and TFTs are formed and a second substrate on which counter electrodes are formed, and a liquid crystal as an electro-optical material is interposed between the two substrates. It is formed by enclosing.

  Therefore, it can be said that the LCD panel 20 has a pixel electrode connected to the source line via the TFT as a switch element. Further, it can be said that the LCD panel 20 has a plurality of source lines, a plurality of switch elements, and a plurality of pixel electrodes in which each pixel electrode is connected to each source line via each switch element.

  The liquid crystal device 10 includes a display driver (drive circuit in a broad sense) 90 that drives the LCD panel 20. The display driver 90 includes the source driver 30. The source driver 30 drives each source line of the source lines SL1 to SLN of the LCD panel 20 based on gradation data corresponding to each source line. The display driver 90 can include a gate driver (scan driver in a broad sense) 32. The gate driver 32 scans the gate lines GL1 to GLM of the LCD panel 20 within one vertical scanning period. The display driver 90 may have a configuration in which at least one of the source driver 30 and the gate driver 32 is omitted.

  The liquid crystal device 10 can include a power supply circuit 94. The power supply circuit 94 generates voltages necessary for driving the source lines and supplies them to the source driver 30. The power supply circuit 94 generates, for example, power supply voltages VDDH and VSSH necessary for driving the source line of the source driver 30 and the voltage of the logic unit of the source driver 30.

  The power supply circuit 94 generates a voltage necessary for scanning the gate line and supplies it to the gate driver 32.

  Further, the power supply circuit 94 generates a counter electrode voltage Vcom. The power supply circuit 94 generates a counter electrode voltage Vcom that periodically repeats the high potential side voltage VCOMH and the low potential side voltage VCOML in accordance with the timing of the polarity inversion signal POL generated by the source driver 30. Output to electrode.

  The liquid crystal device 10 can include a display controller 38. The display controller 38 controls the source driver 30, the gate driver 32, and the power supply circuit 94 according to contents set by a host such as a central processing unit (hereinafter abbreviated as CPU) (not shown). For example, the display controller 38 sets an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the source driver 30 and the gate driver 32.

  In FIG. 1, the liquid crystal device 10 includes the power supply circuit 94 or the display controller 38, but at least one of these may be provided outside the liquid crystal device 10. Alternatively, the liquid crystal device 10 may be configured to include a host.

  The source driver 30 may incorporate at least one of the gate driver 32 and the power supply circuit 94.

  Furthermore, some or all of the source driver 30, the gate driver 32, the display controller 38, and the power supply circuit 94 may be formed on the LCD panel 20. For example, in FIG. 2, the display driver 90 (the source driver 30 and the gate driver 32) is formed on the LCD panel 20. As described above, the LCD panel 20 includes a plurality of source lines, a plurality of gate lines, and a plurality of switch elements in which each switch element is connected to each gate line of the plurality of gate lines and each source line of the plurality of source lines. And a source driver for driving a plurality of source lines. A plurality of pixels are formed in the pixel formation region 80 of the LCD panel 20.

  FIG. 3 shows a configuration example of the gate driver 32 of FIG. 1 or FIG.

  The gate driver 32 includes a shift register 40, a level shifter 42, and an output buffer 44.

  The shift register 40 includes a plurality of flip-flops in which each flip-flop is provided corresponding to each gate line and sequentially connected. When the shift register 40 holds the start pulse signal STV in the flip-flop in synchronization with the clock signal CPV, the shift register 40 sequentially shifts the start pulse signal STV to the adjacent flip-flop in synchronization with the clock signal CPV. The clock signal CPV input here is a horizontal synchronizing signal, and the start pulse signal STV is a vertical synchronizing signal.

  The level shifter 42 shifts the voltage level from the shift register 40 to a voltage level corresponding to the liquid crystal element of the LCD panel 20 and the transistor capability of the TFT. As this voltage level, for example, a high voltage level of 20 V to 50 V is required.

  The output buffer 44 buffers the scanning voltage shifted by the level shifter 42 and outputs it to the gate line to drive the gate line. The high potential side of the pulsed scanning voltage is a selection voltage, and the low potential side of the scanning voltage is a non-selection voltage.

  Note that the gate driver 32 scans a plurality of gate lines by selecting a gate line corresponding to the decoding result by the address decoder without scanning the gate line using a shift register as shown in FIG. Also good.

  FIG. 4 shows a block diagram of a configuration example of the source driver 30 of FIG. 1 or FIG.

  The source driver 30 includes an I / O buffer 50, a display memory 52, a line latch 54, a gradation voltage generation circuit 58, a DAC (Digital / Analog Converter) (a gradation voltage generation circuit in a broad sense) 60, and a source line driving circuit 62. including.

  For example, the gradation data D is input to the source driver 30 from the display controller 38. The gradation data D is input in synchronization with the dot clock signal DCLK and buffered in the I / O buffer 50. The dot clock signal DCLK is supplied from the display controller 38.

  The I / O buffer 50 is accessed by the display controller 38 or a host (not shown). The gradation data buffered in the I / O buffer 50 is written in the display memory 52. The gradation data read from the display memory 52 is output to the display controller 38 and the like after being buffered by the I / O buffer 50.

  The display memory 52 includes a plurality of memory cells provided corresponding to the output lines in which the memory cells are connected to the source lines. Each memory cell is specified by a row address and a column address. Each memory cell for one scan line is specified by a line address.

  The address control circuit 66 generates a row address, a column address, and a line address for specifying a memory cell in the display memory 52. The address control circuit 66 generates a row address and a column address when writing gradation data into the display memory 52. That is, the gradation data buffered in the I / O buffer 50 is written into the memory cell of the display memory 52 specified by the row address and the column address.

  The row address decoder 68 decodes the row address and selects a memory cell of the display memory 52 corresponding to the row address. The column address decoder 70 decodes the column address and selects a memory cell of the display memory 52 corresponding to the column address.

  When the gradation data is read from the display memory 52 and output to the line latch 54, the address control circuit 66 generates a line address. That is, the line address decoder 72 decodes the line address and selects a memory cell of the display memory 52 corresponding to the line address. Then, gradation data for one horizontal scan read from the memory cell specified by the line address is output to the line latch 54.

  The address control circuit 66 generates a row address and a column address when reading the gradation data from the display memory 52 and outputting it to the I / O buffer 50. That is, the gradation data held in the memory cell of the display memory 52 specified by the row address and the column address is read to the I / O buffer 50. The gradation data read to the I / O buffer 50 is extracted by the display controller 38 or a host (not shown).

  Therefore, in FIG. 4, the row address decoder 68, the column address decoder 70, and the address control circuit 66 function as a writing control circuit that performs writing control of gradation data to the display memory 52. On the other hand, in FIG. 4, the line address decoder 72, the column address decoder 70, and the address control circuit 66 function as a readout control circuit that performs readout control of gradation data from the display memory 52.

  The line latch 54 latches the grayscale data for one horizontal scan read from the display memory 52 at the change timing of the latch pulse LP that defines one horizontal scan period. The line latch 54 includes a plurality of registers in which each register holds gradation data for one dot. The gradation data for one dot read from the display memory 52 is taken into each of the plurality of registers of the line latch 54.

  The gradation voltage generation circuit 58 generates a plurality of gradation voltages in which each gradation voltage (reference voltage) corresponds to each gradation data. More specifically, the grayscale voltage generation circuit 58 generates a plurality of grayscale voltages in which each grayscale voltage corresponds to each grayscale data based on the high potential side power supply voltage VDDH and the low potential side power supply voltage VSSH. .

The DAC 60 generates a gradation voltage corresponding to gradation data for one horizontal scan from the line latch 54 for each source output. More specifically, the DAC 58 is a level corresponding to each source line in the grayscale data for one line from the line latch 54 among the multiple grayscale voltages generated by the grayscale voltage generation circuit 58. The gradation voltage corresponding to the gradation data is selected, and the selected gradation voltage is output. Such a DAC 60 includes voltage selection circuits DEC _{1 to} DEC _N provided for each source output. Each voltage selection circuit outputs one gradation voltage corresponding to each gradation data from among the plurality of gradation voltages from the gradation voltage generation circuit 58.

The source line driver circuit 62 includes an output circuit _OP 1 _{~OP N.} Each output circuit of the output circuits OP _{1 to} OP _N includes an operational amplifier circuit, performs impedance conversion using the output gradation voltage from each voltage selection circuit of the DAC 60, and drives the source line.

2. Configuration Example of Source Driver In this embodiment, in order to reduce the circuit scale of the source driver block provided for each source output, each output circuit of the source line driving circuit 62 is provided with a flip-around sample hold circuit. Then, a voltage is supplied to the source line by the flip-around sample / hold circuit. More specifically, the first and second gradation voltages output from the DAC 60 are received, and the flip-around sample-and-hold circuit outputs an output level between the first gradation voltage and the second gradation voltage. Output the regulated voltage to the source line.

  Here, an output circuit of the source line driving circuit 62 including such a flip-around sample / hold circuit will be described.

Figure 5 is a circuit diagram showing a configuration example of the output circuit OP ₁ of the source line driver circuit 62.

It shows the arrangement of Figure 5 the output circuit OP ₁ but has the same configuration as the output circuit OP ₁ other output circuit _OP 2 _{~OP N.} FIG. 5 shows an example in which two types of output gradation voltages between the first and second gradation voltages are generated, but the present invention is not limited to the types of output gradation voltages.

  In FIG. 5, the first and second gradation voltages are supplied from the DAC 60 as the input voltage Vin, and the output gradation voltage Vout is supplied to the source line.

By using a plurality of types of output gradation voltages generated in the output circuit, the types of gradation voltages generated by the gradation voltage generation circuit 58 can be reduced. Therefore, the number of gradation voltage signal lines can be greatly reduced, and the circuit scale of the DAC 60 can be greatly reduced. For example, when the source driver 30 drives the source line based on 6-bit grayscale data, the grayscale voltage generation circuit originally needs to generate 64 (= 2 ⁶ ) types of grayscale voltages. . However, since each output circuit of the source line driver circuit 62 shown in FIG. 5 can generate two kinds of gradation voltages, the gradation voltage generation circuit 58 only needs to be able to generate 32 kinds of gradation voltages. For this reason, the number of gradation voltage signal lines is 32, for example, and the wiring area of the gradation voltage signal lines can be halved. Actually, in this embodiment, since the output circuit generates a voltage obtained by dividing the first and second gradation voltages, 33 gradation voltage signal lines are required.

  Such an output circuit includes a flip-around sample and hold circuit. The operation of the flip-around sample / hold circuit is different between the sampling period provided in the first half of one horizontal scanning period (1H) and the hold period provided in the second half. That is, the flip-around sample / hold circuit supplies the charge accumulated in the sampling period to the output side in the hold period.

  Such an output circuit includes an operational amplifier circuit and a plurality of capacitive elements having one ends connected to the input of the operational amplifier circuit. The output circuit electrically connects the input and output of the operational amplifier circuit in a state where the output of the operational amplifier circuit and the source line are electrically cut off during the sampling period. Charge corresponding to the first or second gradation voltage is accumulated in the element. That is, in the sampling period, the output of the operational amplifier circuit and the source line are electrically cut off so as not to change the voltage of the source line. A charge corresponding to one of the first and second gradation voltages is accumulated at one end of the plurality of capacitive elements, and other than the plurality of capacitive elements by the drive unit of the output stage of the operational amplifier circuit. Charge is supplied to the end.

  Next, in the subsequent hold period, the output circuit electrically cuts off the input and output of the operational amplifier circuit, and supplies the charges accumulated in the plurality of capacitive elements to the output of the operational amplifier circuit. At this time, the output of the operational amplifier circuit and the source line are electrically connected. That is, in the hold period, the output of the operational amplifier circuit and the source line are electrically connected to supply the output gradation voltage to the source line. Then, the input and output of the operational amplifier circuit are electrically cut off, and the charges accumulated in the plurality of capacitive elements are supplied to the output of the operational amplifier circuit. In this way, the imaginary short function on the input side of the operational amplifier circuit that attempts to make the input voltage equal to the output voltage causes the charge of the operational amplifier circuit to be charged and discharged, thereby changing the output gradation voltage. be able to.

More specifically, the output circuit OP ₁ includes an operational amplifier circuit OPC ₁ , first to jth capacitive elements C1 to Cj (j is an integer of 2 or more), and first to jth flip-around switches. S3-1 to S3-j and an output switch S4 can be included. An analog ground AGND (given voltage) is supplied to the non-inverting input terminal of the operational amplifier circuit OPC ₁ . When the high potential side power supply voltage of the operational amplifier circuit OPC ₁ is VDD and the low potential side power source voltage is VSS, the analog ground AGND can be set to (VDD + VSS) / 2. One end of the capacitive element C1~Cj the first to j, is connected to the inverting input terminal of the operational amplifier circuit OPC _1. The capacitance values of the first to jth capacitive elements C1 to Cj are equal. The p (1 ≦ p ≦ j, p is an integer) switches S3-p for flip-around is inserted between the output and the other end and the operational amplifier circuit OPC ₁ of the capacitor Cp of the p. Output switch S4 is inserted between the output lines connected operational amplifier circuit OPC ₁ electrically to the output and the source line SL1. By supplying the first and second grayscale voltages to the first to jth capacitive elements C1 to Cj, the output circuit OP ₁ can output 2 ^(j−) between the first and second grayscale voltages. ¹⁾ Various kinds of output gradation voltages can be generated.

The output circuit OP ₁ can further include first to jth input switches. One end of the p-th (1 ≦ p ≦ j, p is an integer) input switch is connected to the other end of the p-th capacitive element Cp. Then, the first or second gradation voltage is supplied to the other end of each of the first to jth input switches in a time division manner.

Next, a more specific configuration and operation will be described by taking the case of FIG. 5 as an example. FIG. 5 shows a case where j is 2. The first input switch S0 is switch-controlled (on / off control) by a switch control signal SC0. The second input switch S1 is switch-controlled by a switch control signal SC1. The feedback switch S2 is switch-controlled by a switch control signal SC2. The first and second flip-around switches S3-1 and S3-2 are switch-controlled by a switch control signal SC3. The output switch S4 is switch-controlled by a switch control signal SC4. Such switch control signal SC0~SC4 is generated in the control circuit of the output circuit OP _1, not shown.

Figure 6 is a diagram for explaining a first operation example of the output circuit OP ₁ in FIG.

  In the sampling period, the first gradation voltage Vin1 and the second gradation voltage Vin2 are supplied in a time division manner. The switch is controlled so that the first input switch S0 is turned on during the period in which the first gradation voltage Vin1 is supplied and turned off during the subsequent sampling period and hold period. Further, the second input switch S1 is switch-controlled so as to be turned on at least during a period in which the second gradation voltage Vin2 is supplied. Further, the second input switch S1 is switch-controlled so that it is turned on in the sampling period and turned off in the hold period.

  The feedback switch S2 is switch-controlled so that it is turned on in the sampling period and turned off in the hold period. The first and second flip-around switches S3-1 and S3-2 are switch-controlled so that they are turned off during the sampling period and turned on during the hold period. The output switch S4 is switch-controlled so that it is turned off during the sampling period and turned on during the hold period.

  That is, in the sampling period, the first to jth flip-around switches are turned off, the feedback switch S2 is turned on, and the output switch S4 is turned off, and the first and second capacitive elements C1 and C2 are connected to the other ends. One of the first and second gradation voltages Vin1 and Vin2 is supplied. In the hold period after the sampling period, the first to jth flip-around switches are turned on, the feedback switch S2 is turned off, and the output switch S4 is turned on, so that the first gradation voltage Vin1 and the second An output gradation voltage Vout between the gradation voltage Vin2 is output to the source line.

More specifically, in FIG. 6, during the sampling period, a charge corresponding to the first gradation voltage Vin1 is accumulated at one end of the first capacitive element C1 via the first input switch S0. In addition, a charge corresponding to the second gradation voltage Vin2 is accumulated at one end of the second capacitive element C2 via the second input switch S1. In this period, since the feedback switch S2 is turned on, the virtual short function of the operational amplifier circuit OPC _1, node NEG voltage of the inverting input terminal of the operational amplifier circuit OPC ₁ and the output voltage of the operational amplifier OPC ₁ analog It becomes the ground AGND.

  Therefore, in the sampling period, the charge Qs expressed by the following equation is accumulated in the node NEG. At this time, since the output switch S4 is OFF, the voltage of the source line SL1 does not fluctuate.

Qs = Vin1 × C + Vin2 × C (1)
Here, Vin1 is the first gradation voltage, Vin2 is the second gradation voltage, and the capacitance value of each of the first and second capacitive elements C1 and C2 is C.

Next, in the hold period, the first and second input switches S0 and S1 and the feedback switch S2 are turned off, and the first and second flip-around switches S3-1 and S3-2 are turned on. As a result, the voltage corresponding to the charge accumulated in the first and second capacitive elements C1, C2 is output as the output gray scale voltage of the operational amplifier circuit OPC _1. In this case, since one end of the first and second capacitive elements C1 and C2 is short-circuited, the output gradation voltage Vout is expressed by the following equation.

Vout = (Vin1 + Vin2) / 2 (2)
Figure 7 is a diagram for explaining a second operation example of the output circuit OP ₁ in FIG.

  In FIG. 6, the first and second capacitor voltages are supplied to the first and second capacitor elements in the descending order of the first and second gradation voltages. In FIG. 7, the first and second gradation voltages have the lowest potential. The first and second capacitor elements are supplied in this order.

  Even in this case, similarly to FIG. 6, the switch control of the first and second input switches S0 and S1, the feedback switch S2, the first and second flip-around switches S3-1 and S3-2, and the output switch S4. Is done. Then, the output gradation voltage Vout expressed by the equation (2) is output during the hold period.

Figure 8 is an explanatory view of a third operation example of the output circuit OP ₁ in FIG.

  6 and 7 show examples in which the output gradation voltage Vout is output as a voltage between the first gradation voltage Vin1 and the second gradation voltage Vin2, the present invention is limited to this. It is not a thing. By setting the first and second gradation voltages Vin1 and Vin2 to the same potential, the output gradation voltage Vout is also set to the same potential as the first and second gradation voltages Vin1 and Vin2. Can do.

  Even in this case, similarly to FIG. 6, the switch control of the first and second input switches S0 and S1, the feedback switch S2, the first and second flip-around switches S3-1 and S3-2, and the output switch S4. Is done. As a result, from the equation (2), the output gradation voltage Vout becomes a voltage having the same potential as the first and second gradation voltages Vin1 and Vin2, and this output gradation voltage Vout is output during the hold period.

  Since the source line is driven using the flip-around sampling and holding circuit as described above, a plurality of gradation voltages can be generated by the output circuit with a very simple configuration. As a result, the types of gradation voltages that should be generated by the gradation voltage generation circuit 58 can be greatly reduced. As a result, the number of gradation voltage signal lines can be reduced, and the circuit scale of the DAC 60 can be greatly reduced. Since the DAC 60 is generally supplied with a high voltage, it is necessary to increase the transistor size, and the reduction in the circuit scale of the DAC 60 can greatly contribute to the reduction in the chip size of the source driver 30.

  In addition, the flip-around sampling and holding circuit described above enables a Rail-to-Rail operation without adding an auxiliary circuit or the like, and eliminates the need to increase the transistor size in order to suppress variations. As a result, the chip size of the source driver 30 can be reduced.

Furthermore, since flip-around sample hold circuit described above is configured to transfer charge accumulated in the first and second capacitors C1, C2 to the output side of the operational amplifier circuit OPC _1, the operational amplifier circuit OPC ₁ The output gradation voltage Vout can be generated with high accuracy without being affected by the input offset voltage of the.

  Further, in the above-described flip-around sampling and holding circuit, it is not necessary to output the gradation voltage generated by the DAC 60 to the source line in order to set the gradation voltage to be applied to the source line with high accuracy. The voltage can be generated with high accuracy. This eliminates the need for the DAC 60 to generate gradation voltages with high accuracy, simplifying the configuration of the DAC 60 and reducing the circuit scale of the DAC 60.

2.1 Comparative Example By the way, in the flip-around type sample-and-hold circuit having the configuration as in the present embodiment, the order of switch control of the first to jth input switches in the sampling period and the level input to each input switch. It is desirable to adjust the level of the regulated voltage as follows. That is, when the output gradation voltage Vout is closer to the maximum potential voltage of the voltage output to the source line than the minimum potential voltage of the voltage output to the source line, the DAC 60 (gradation voltage generation circuit) is shown in FIG. As shown, it is desirable to output the first and second gradation voltages in order of increasing potential. Here, for example, among the 64 types of gradation voltages V0 to V63, when the lowest potential voltage is V0, the highest potential voltage is V63, and when the lowest potential voltage is V63, the highest potential voltage is V0.

  Further, when the output gradation voltage Vout is closer to the lowest potential voltage than the highest potential voltage, it is desirable that the DAC 60 (gradation voltage generation circuit) outputs the first and second gradation voltages in order of increasing potential.

  Accordingly, when the first or second gradation voltage is supplied to the other end of each of the first to jth input switches, the output gradation voltage Vout is closer to the highest potential voltage than the lowest potential voltage. Of the first and second grayscale voltages, the high potential side grayscale voltage is supplied to any one of the first to jth capacitive elements C1 to Cj, and the low potential side It is desirable to perform switch control of the first to jth input switches so that the regulated voltage is supplied to any one of the first to jth capacitive elements C1 to Cj.

  Further, when the first or second gradation voltage is supplied to the other end of each of the first to j-th input switches, the output gradation voltage Vout is closer to the lowest potential voltage than the highest potential voltage. Among the first and second gradation voltages, the low potential side gradation voltage is supplied to any one of the first to jth capacitance elements C1 to Cj, and the high potential side It is desirable to perform switch control of the first to jth input switches so that the regulated voltage is supplied to any one of the first to jth capacitive elements C1 to Cj.

  Here, the reason will be described while comparing with the comparative example of the present embodiment.

Figure 9 shows an explanatory diagram of an operation example of the output circuit OP ₁ in the comparative example of this embodiment.

  9, the same parts as those in FIGS. 6 to 8 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. In this comparative example, in the first half of the sampling period, the first gradation voltage Vin1 is supplied to one end of the first capacitor C1 with the first input switch S0 turned on and the second input switch S1 turned off. Is done. In the second half of the sampling period, the second gradation voltage Vin2 is supplied to one end of the second capacitor C2 with the first input switch S0 off and the second input switch on. In this comparative example, the potential of the first gradation voltage Vin1 is lower than the potential of the second gradation voltage Vin2.

  FIG. 10 is an operation explanatory diagram of this comparative example.

  10, the same parts as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. FIG. 10 shows a state in which the first input switch S0 is off and the second input switch S1 is on during the sampling period.

  For example, it is assumed that the first gradation voltage Vin1 in FIG. 9 is supplied to the first capacitive element C1 in a state where the first input switch S0 is on and the second input switch S1 is off (SQ1). ). At this time, charges corresponding to the first gradation voltage Vin1 are accumulated in the first capacitor element C1. Next, as shown in FIG. 10, in the state where the first input switch S0 is OFF and the second input switch S1 is ON, the second grayscale voltage Vin2 ( It is assumed that Vin1 <Vin2) is supplied (SQ2). At this time, charges corresponding to the second gradation voltage Vin2 are accumulated in the second capacitor element C2.

  Here, with the application of the second gradation voltage Vin2, the voltage level of the node NEG (the other end of the second capacitor element C2) in which charges corresponding to the first gradation voltage Vin1 are accumulated varies. Since the other end of the first capacitive element C1 and the other end of the second capacitive element C2 are electrically connected, a change in the voltage level of the node NEG is caused by one end of the capacitively coupled first capacitive element C1. This is because it is transmitted as a fluctuation in the voltage level (SQ3).

  In this case, the voltage fluctuation at the node NEG is transmitted as a voltage level fluctuation at one end of the first flip-around switch S3-1 via the first capacitive element C1, and the voltage level is higher than the power supply voltage VDD. There may be a potential (SQ4). This means that leakage occurs because the diode connection portion between the source (drain) of the P-type MOS transistor constituting the switch and the substrate on which the transistor is formed is in the forward direction. Therefore, the voltage level of the output gradation voltage Vout to be output during the hold period varies.

  Therefore, in the present embodiment, for example, the first gradation voltage Vin1 on the high potential side is supplied to the second capacitor C2 from the beginning, and then the second gradation voltage Vin2 on the low potential side is changed to the second capacitance element C2. The switches are controlled so as to be supplied to the second capacitive element C2. By doing so, it is possible to avoid a situation in which the fluctuation of the voltage level of the second capacitor C2 is transmitted to the node NEG.

  In other words, when the output gradation voltage Vout is closer to the maximum potential voltage than the minimum potential voltage, the gradation voltage on the high potential side among the first and second gradation voltages is the first to jth capacitive elements C1 to Cj. 1st to jth so that the low-potential-side gradation voltage is supplied to any one of the first to jth capacitive elements C1 to Cj in a state where the first to jth capacitive elements are supplied. Switch control of the input switch.

  9 and 10, the case where the output gradation voltage Vout is closer to the highest potential voltage than the lowest potential voltage has been described. However, the same applies to the case where the output gradation voltage Vout is closer to the lowest potential voltage than the highest potential voltage. The input switch leaks. Therefore, when the output gradation voltage Vout is closer to the lowest potential voltage than the highest potential voltage, the gradation voltage on the low potential side among the first and second gradation voltages is the first to jth capacitive elements C1 to Cj. The first to jth so that the high-potential-side grayscale voltage is supplied to any one of the first to jth capacitive elements C1 to Cj in a state of being supplied to any one of the capacitive elements. It is desirable to perform switch control of the input switch.

  Here, in order to determine whether the output gradation voltage Vout is close to the maximum potential voltage or the minimum potential voltage of the gradation voltage with a simple configuration, it is determined based on the most significant bit of the gradation data. Also good.

  FIG. 11 is an explanatory diagram of the output order of gradation voltages in this embodiment.

  For example, it is assumed that the gradation voltage corresponding to the most significant bit of the gradation data corresponding to “0” is higher than the gradation voltage corresponding to the most significant bit corresponding to “1”. At this time, when the most significant bit of the gradation data is “0”, after the gradation voltage on the high potential side of the first and second gradation voltages is supplied to the first capacitor element C1, the low potential side is supplied. Is supplied to the second capacitor C2. In addition, when the most significant bit of the gradation data is “1”, the gradation voltage on the low potential side of the first and second gradation voltages is supplied to the first capacitor C1, and then the high potential side is supplied. The gradation voltage is supplied to the second capacitor element C2. By doing so, it is possible to avoid a situation in which the output gradation voltage Vout cannot generate the target voltage without causing a leak in the first and second flip-around switches S3-1 and S3-2. become.

2.2 Configuration of Main Part of Source Driver Next, a configuration example of a main part of the source driver 30 in the present embodiment will be described.

  FIG. 12 shows a block diagram of a configuration example of the source driver block of the source driver 30 in the present embodiment. 12, the same parts as those in FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted as appropriate. In the following, it is assumed that the gradation data is 6 bits.

FIG. 12 shows only the configuration of the source driver block that drives the source line SL1. The source driver block for driving the source line SL1 includes an addition circuit 80 ₁ , an addition control logic 82 ₁ , a voltage selection circuit DEC ₁ , and an output circuit OP ₁ .

In the present embodiment, in order to supply to the output circuit OP ₁ by time division first and second grayscale voltages, the gradation data D from the display memory 52 [5: 0] outputs, and grayscale data It supplies the data obtained by incrementing the grayscale data to the voltage selection circuit DEC _1. At this time, the adder circuit 80 ₁ is controlled based on the addition control signal ADD_BIT from the addition control logic 82 _1, and outputs the data obtained by incrementing the gradation data, so the tone data or might output as it ing.

More specifically, the gray-scale data D [5: 0] upper five bits of the data D [5: 1] is inputted to the adder circuit 80 _1. The gradation data D [5: 0] and data of the data and the least significant bit D [0] of the most significant bit D [5] is input to the addition control logic 82 ₁ of the. Added to the control logic 82 _1, is input summing timing signals AD1, AD2, which is generated in the control circuit (not shown), the grayscale data D [5], based on the data and the addition timing signals AD1, AD2 of D [0] An addition control signal ADD_BIT is generated.

  FIG. 13 is an explanatory diagram of the addition timing signals AD1 and AD2 in FIG.

Adding timing signal AD1 is at the H level corresponds to the first on-period of the input switch S0 to the gradation voltage is supplied to the first capacitor C1 of the output circuit OP _1. Adding timing signal AD2 is at the H level corresponds to the ON period of the second input switch S1 to the gray scale voltage is supplied to the second capacitor C2 of the output circuit OP _1.

Figure 14 is a view for explaining an operation of the addition control logic 82 ₁ in FIG. 12.

  In FIG. 14, when the gradation data [5: 0] is “000000”, the gradation voltage has the highest potential, and when the gradation data [5: 0] is “111111”, the gradation voltage has the lowest potential. And

Addition control logic 82 _1, data of the most significant bit D [5] of the tone data eaves "0", performs the addition control of the adding circuit 80 ₁ at the timing of the addition timing signal AD2. At this time, when the data of the least significant bit D [0] of the grayscale data is "0", the adder circuit 80 _1, the grayscale data D: outputs data [5 1] directly to the voltage select circuit DEC ₁ . Further, when the data of the least significant bit D of the gradation data [0] is "1", the adder circuit 80 _1, the grayscale data D [5: 1] incremented data (grayscale data D [5: 1 ] Is added to the voltage selection circuit DEC ₁ .

The addition control logic 82 _1, data of the most significant bit D [5] of the tone data eaves as "1", performs addition control of the adding circuit 80 ₁ at the timing of the addition timing signal AD1. At this time, when the data of the least significant bit D [0] of the grayscale data is "0", the adder circuit 80 _1, the grayscale data D: outputs data [5 1] directly to the voltage select circuit DEC ₁ . Further, when the data of the least significant bit D of the gradation data [0] is "1", the adder circuit 80 _1, the grayscale data D: outputs the data obtained by incrementing the 5 1] to the voltage selection circuit DEC ₁ .

In FIG. 12, the output of the addition circuit 80 ₁ controlled by the addition control logic 82 ₁ in this way is input to the voltage selection circuit DEC ₁ as gradation data. Voltage select circuit DEC _1, based on the grayscale data from the addition circuit 80 _1, and outputs one of the gray scale voltages V0~V32 generated by the gradation voltage generating circuit 58 to the output circuit OP _1. The output circuit OP ₁ has the configuration of FIG.

2.3 Auxiliary Capacitance Element In the present embodiment, it is desirable to connect the auxiliary capacitance element CCS to the node NEG as shown in FIG. For example, the ground power supply voltage VSS or the analog ground AGND is supplied to one end of the auxiliary capacitance element CCS, and the node NEG is connected to the other end. By doing so, it is possible to suppress voltage fluctuation at the inverting input terminal of the operational amplifier circuit OPC ₁ and realize further stabilization of the output gradation voltage Vout.

  Note that since the auxiliary capacitive element CCS is intended to suppress potential fluctuations, it is not necessary that the capacitance value be accurately formed as compared with the first and second capacitive elements C1 and C2. Therefore, in the capacitive element formation region where the auxiliary capacitive element CCS and the first and second capacitive elements C1 and C2 are formed, the auxiliary capacitive element CCS is etched compared to the first and second capacitive elements C1 and C2. It is desirable that the capacitor is formed in a region that is difficult to control when forming a capacitive element. Therefore, it is desirable that the auxiliary capacitance element CCS is also used as a dummy capacitance element formed in the capacitance element formation region in the source driver.

  FIGS. 15A and 15B are explanatory diagrams of the auxiliary capacitance element CCS.

  FIG. 15A shows a layout image of the source driver 30. In the source driver 30, source driver blocks SB1 to SBN are arranged in the arrangement direction of the output pads to the source lines. Each source driver block includes a gradation voltage generation circuit, a voltage selection circuit, and a source line driving circuit, and the layout arrangement of each source driver block is the same.

  FIG. 15B shows an image of the capacitor element formation region of the source driver block SBn. The source driver block SBn includes a first capacitor element C1, a second capacitor element C2, and an auxiliary capacitor element in a direction (crossing direction) perpendicular to the array direction (output pad array direction) of the source driver blocks SB1 to SBN. It has a capacitive element formation area CEA in which CCS is formed. At this time, the auxiliary capacitance element CCS is formed along one of the two boundary portions facing each other in the direction perpendicular to the arrangement direction (crossing direction) of the boundaries of the capacitance element formation region CEA. It is desirable that Generally, a dummy capacitive element in the capacitive element formation region is formed at this boundary portion. In FIG. 15B, assuming that the arrangement direction of the source driver blocks SB1 to SBN is DR1, one side EDn out of two sides constituting the boundary portion of the source driver block SBn facing each other in the direction DR2 perpendicular to the arrangement direction DR1. Along with this, the auxiliary capacitance element CCS is formed.

  Thus, the edges (end portions) of the first and second capacitor elements CS1 and CS2 are connected to the edge of the auxiliary capacitor element CCS of the source driver block or the first or second capacitor of the adjacent source driver block. Adjacent to the edges of the elements C1 and C2. Therefore, since the gaps Δd1 to Δd4 between the edges can be formed at substantially the same etching rate, the first and second capacitive elements C1 and C2 can be formed with high accuracy. On the other hand, the edge of the auxiliary capacitive element CCS is not adjacent to the edge of another capacitive element. Accordingly, for the edge of the auxiliary capacitive element CCS, for example, the etching rate from the output pad arrangement region side is different from the etching rate from the first or second capacitive element C1, C2 side. Capacitance elements cannot be formed with higher accuracy than the elements C1 and C2.

  By forming each capacitive element as shown in FIG. 15B, the capacitance values of the first and second capacitive elements C1 and C2 can be formed with high accuracy, while the auxiliary capacitive element is not used without wasting the layout area. A CCS can be formed.

2.4 Operational Amplifier Circuit It is desirable that the circuit scale of the flip-around sampling and holding circuit in this embodiment is small. Therefore, paying attention to the fact that the flip-around sampling and holding circuit in this embodiment performs discrete operations in the sampling period and the holding period, the operational amplifier circuit applied to the flip-around sampling and holding circuit is as follows. It is desirable to employ the configuration described.

The flip-around sampling and holding circuit in the present embodiment turns off the output switch S4 during the sampling period to drive a low load output, and turns on the output switch S4 during the hold period to drive a high load output. Therefore, the operational amplifier circuit of the flip-around sampling and holding circuit according to the present embodiment may perform the class A amplification operation during the sampling period and perform the class AB amplification operation during the hold period. Therefore, in the present embodiment, the following configurations can be employed as the operational amplifier circuits OPC _{1 to} OPC _N.

FIG. 16 is a circuit diagram showing a configuration example of the operational amplifier circuit OPC ₁ shown in FIG.

FIG. 16 shows a configuration example of the operational amplifier circuit OPC ₁ , but the other operational amplifier circuits OPC _{2 to} OPC _N also have the same configuration.

The operational amplifier circuit OPC ₁ includes a differential amplifier 110 (an operational amplifier in a broad sense), an output unit 120, a capacitor CCP, and a charge supply circuit 130. The differential amplifier 110 amplifies the difference value between the input voltage VIN and the output voltage VOUT. The output unit 120 is provided on the first power supply side that supplies the analog power supply voltage AVDD, and is a P-type drive transistor (first conductivity type) whose gate electrode is controlled based on the voltage of the output node NDD of the differential amplifier 110. First drive transistor) PTR1, and N-type drive transistor (second conductivity type second drive transistor) NTR1 provided on the second power supply side for supplying analog ground AGND in series with P-type drive transistor PTR1 Including. Capacitor CCP is provided to capacitively couple the gate electrode of P-type drive transistor PTR1 and the gate electrode of N-type drive transistor NTR1.

The charge supply circuit 130 supplies charge to the gate electrode of the N-type drive transistor NTR1 during the sampling period, and stops supplying charge to the gate electrode of the N-type drive transistor NTR1 during the hold period. Thus, during the sampling period, the P drive transistor PTR1 and the N drive transistor NTR1 are operated based on the voltage of the output node NDD of the differential amplifier 110, and the output voltage VOUT of the operational amplifier circuit 100 is set to the high potential side. Can also be changed to the low potential side. In the hold period, the output voltage VOUT is output depending on the voltage of the gate electrode of the P-type drive transistor PTR1. Therefore, the configuration of the operational amplifier circuit OPC ₁ that performs the class A amplification operation in the sampling period and performs the class AB amplification operation in the hold period can be simplified.

FIG. 17 shows a circuit diagram of a configuration example of the operational amplifier circuit OPC ₁ of FIG.

  17 identical to those in FIG. 16 are assigned the same reference numerals as in FIG.

  The differential amplifier 110 includes a current mirror circuit CM1, a differential pair DIF1, and a current source CS1. The current mirror circuit CM1 includes P-type transistors PTR10 and PTR11 whose source is supplied with the analog power supply voltage AVDD. The gate electrode of P-type transistor PTR10 and the gate electrode of P-type transistor PTR11 are connected. The gate electrode and drain of the P-type transistor PTR11 are connected.

  The differential pair DIF1 includes N-type transistors NTR10 and NTR11. The source of N-type transistor NTR10 and the source of N-type transistor NTR11 are connected. The drain of the N-type transistor NTR10 is connected to the drain of the P-type transistor PTR10. The drain of the N-type transistor NTR11 is connected to the drain of the P-type transistor PTR11. An analog ground AGND is supplied to one end of the current source CS1, and the other end of the current source CS1 is connected to the sources of the N-type transistors NTR10 and NTR11.

  In such a differential amplifier 110, the input voltage VIN is supplied to the gate electrode of the N-type transistor NTR10, and the output voltage VOUT is supplied to the gate electrode of the N-type transistor NTR11. A connection node to which the drain of the P-type transistor PTR10 and the drain of the N-type transistor NTR10 are connected is an output node NDD of the differential amplifier 110. This output node is connected to the gate electrode of the P-type drive transistor PTR1 of the output unit 120.

  The charge supply circuit 130 includes a current source transistor CTR that is supplied with current to the drain and is diode-connected, one end of which is connected to the gate electrode of the current source transistor CTR, and the other end is connected to one end of the capacitor CCP and the N-type drive transistor NTR1. Switch circuit SWT to which the gate electrode is connected. The switch circuit SWT is switch-controlled by a switch control signal STC. The charge supply circuit 130 may further include a current source CS2 that is connected to the drain of the current source transistor CTR and generates a constant current.

  FIG. 18 is a diagram for explaining the operation of the switch control signal of the sampling hold circuit to which the operational amplifier circuit of FIG. 17 is applied.

  In FIG. 18, together with the first and second input switches S0 and S1, the feedback switch S2, the first and second flip-around switches S3-1 and S3-2, and the output switch S4, the switch circuit SWT of FIG. An operation example is shown. As shown in FIG. 18, the switch circuit SWT in FIG. 17 is switch-controlled so as to be turned on in the sampling period and turned off in the hold period by a switch control signal STC generated by a control circuit (not shown).

In the operational amplifier circuit OPC ₁ of FIG. 17, the voltage of the gate electrode of the N-type drive transistor NTR1 also changes according to the change of the voltage of the gate electrode of the P-type drive transistor PTR1 via the capacitor CCP. In the charge supply circuit 130, during the sampling period, the switch circuit SWT is turned on to accumulate charges in the gate electrode of the N-type drive transistor NTR1 by the current source transistor CTR, while changing the voltage of the gate electrode of the P-type drive transistor PTR1. This is transmitted to the gate electrode of the N-type drive transistor NTR1. In the charge supply circuit 130, the switch circuit SWT is turned off in the hold period, and the change in the voltage of the gate electrode of the P-type drive transistor PTR1 is transmitted to the gate electrode of the N-type drive transistor NTR1.

Consider a case where the input voltage VIN is higher than the output voltage VOUT in the differential amplifier 110 of the operational amplifier circuit OPC _{1 having} such a configuration. In this case, the voltage at the output node NDD decreases and the voltage at the drain of the N-type transistor NTR11 increases. As a result, the voltage of the gate electrode of the P-type drive transistor PTR1 decreases, and the P-type drive transistor PTR1 is turned on. Here, when the voltage of the gate electrode of the P-type drive transistor PTR1 decreases, the voltage of the gate electrode of the N-type drive transistor NTR1 also decreases.

  On the other hand, in the differential amplifier 110, a case where the input voltage VIN is lower than the output voltage VOUT is considered. In this case, the voltage at the output node NDD increases and the voltage at the drain of the N-type transistor NTR11 decreases. As a result, the voltage of the gate electrode of the P-type drive transistor PTR1 increases, and the P-type drive transistor PTR1 is turned off. Here, when the voltage of the gate electrode of the P-type drive transistor PTR1 increases, the voltage of the gate electrode of the N-type drive transistor NTR1 also increases.

As a result of the operation as described above, the operational amplifier circuit OPC ₁ shifts to an equilibrium state in which the input voltage VIN and the output voltage VOUT become substantially the same potential.

The operational amplifier circuit OPC _{1 in} FIG. 16 is not limited to the configuration in FIG. For example, in FIG. 16, a power source that supplies an analog ground AGND as a first power source, a power source that supplies an analog power supply voltage AVDD as a second power source, an N type as a first conductivity type, and a P type as a second conductivity type. The configuration is as follows.

  FIG. 19 shows a circuit diagram of another configuration example of the operational amplifier circuit of FIG.

  In this case, the output unit 120 includes an N-type drive transistor NTR2 whose gate electrode is controlled based on the voltage at the output node of the differential amplifier 110 provided on the first power supply side, and an N-type drive transistor NTR2 in series. And a P-type drive transistor PTR2 provided on the second power supply side.

  A differential amplifier 110 of the operational amplifier circuit shown in FIG. 19 includes a current mirror circuit CM10, a differential pair DIF10, and a current source CS10. The current mirror circuit CM10 includes N-type transistors NTR40 and NTR41 whose analog ground AGND is supplied to the source. The gate electrode of N-type transistor NTR40 and the gate electrode of N-type transistor NTR41 are connected. The gate electrode and drain of N-type transistor NTR41 are connected.

  The differential pair DIF10 includes P-type transistors NTR40 and PTR41. The source of the P-type transistor PTR40 and the source of the P-type transistor PTR41 are connected. The drain of the P-type transistor PTR40 is connected to the drain of the N-type transistor NTR40. The drain of the P-type transistor PTR41 is connected to the drain of the N-type transistor NTR41. The analog power supply voltage VDD is supplied to one end of the current source CS10, and the other end of the current source 10 is connected to the sources of the P-type transistors PTR40 and PTR41.

  In such a differential amplifier 110, the input voltage VIN is supplied to the gate electrode of the P-type transistor PTR40, and the output voltage VOUT is supplied to the gate electrode of the P-type transistor PTR41. A connection node to which the drain of the N-type transistor NTR40 and the drain of the P-type transistor PTR40 are connected becomes an output node NDD of the differential amplifier 110. This output node is connected to the gate electrode of the N-type drive transistor NTR2 of the output unit 120.

  The charge supply circuit 130 includes a current source transistor CTR10 that is supplied with a diode and connected to a drain thereof, a gate electrode of the current source transistor CTR10 connected to one end thereof, and one end of a capacitor CCP and a P-type drive transistor PTR2 connected to the other end thereof. Switch circuit SWT to which the gate electrode is connected. The charge supply circuit 130 may further include a current source CS20 that is connected to the drain of the current source transistor CTR10 and generates a constant current.

Such operation of the operational amplifier circuit OPC ₁ having the configuration shown in FIG. 19 is omitted because it is same as the operation of the operational amplifier circuit OPC ₁ shown in FIG. 18.

2.5 Modification of Output Circuit In the present embodiment, the output circuit of the source line drive circuit 62 has been described as generating two types of gradation voltages between the first and second gradation voltages. In the modification of this embodiment, four types of gradation voltages between the first and second gradation voltages are generated. That is, the configuration example in the case where j is 4 in the description of FIG. 5 is the configuration of this modification.

Figure 20 is a circuit diagram showing a configuration example of the output circuit OP ₁ of the source line driver circuit 62 of the modification of this embodiment.

  In FIG. 20, the same parts as those in FIG. In FIG. 20, first to fourth input switches SI1 to SI4 are provided, and first to fourth flip-around switches S3-1 to S3-4 are provided. The capacitance values of the first to fourth capacitive elements C1 to C4 are equal.

FIG. 21 (A), the in FIG. 21 (B), an explanatory view of a first operation example of the output circuit OP ₁ in Figure 20.

  In FIGS. 21A and 21B, the first and second gradation voltages when the lower two bits of data D [1: 0] of gradation data D [5: 0] are “00”. In this example, 4.0 V is output as the output gradation voltage between the two. As shown in FIG. 21A, when 4.0 V is applied as the first gradation voltage Vin1 and 3.8 V is applied as the second gradation voltage Vin2 during the sampling period, the first to fourth input switches SI1. The voltage of 4.0V is supplied to all of the first to fourth capacitive elements C1 to C4 through -SI4. Then, as shown in FIG. 21B, in the hold period, the output grayscale voltage is supplied by supplying charges to the output side via the first to fourth flip-around switches S3-1 to S3-4. 4.0V can be output as Vout.

Figure 22 (A), in FIG. 22 (B), it shows a diagram of a second operation example of the output circuit OP ₁ in Figure 20.

  22A and 22B, the first and second gradation voltages when the lower-order 2-bit data D [1: 0] of the gradation data D [5: 0] is “01”. In the example, 3.95 V is output as the output gradation voltage between the two. As shown in FIG. 22A, when 4.0 V is applied as the first gradation voltage Vin1 and 3.8 V is applied as the second gradation voltage Vin2 during the sampling period, the first to fourth input switches SI1. Through ~ SI4, 4.0 V is supplied to three capacitive elements among the first to fourth capacitive elements C1 to C4, and 3.8 V is supplied to the remaining one capacitive element. Then, as shown in FIG. 22B, in the hold period, charge is supplied to the output side via the first to fourth flip-around switches S3-1 to S3-4, and thus the law of charge conservation. Accordingly, 3.95V can be output as the output gradation voltage Vout.

Figure 23 (A), in FIG. 23 (B), an explanatory view of a third operation example of the output circuit OP ₁ in Figure 20.

  In FIG. 23A and FIG. 23B, the first and second gradation voltages when the lower-order 2-bit data D [1: 0] of the gradation data D [5: 0] is “10”. In the example, 3.90 V is output as the output gradation voltage between the two. As shown in FIG. 23A, when 4.0 V is applied as the first gradation voltage Vin1 and 3.8 V is applied as the second gradation voltage Vin2 during the sampling period, the first to fourth input switches SI1. Through ~ SI4, 4.0 V is supplied to two of the first to fourth capacitive elements C1 to C4, and 3.8 V is supplied to the remaining two capacitive elements. Then, as shown in FIG. 23B, in the hold period, by supplying charges to the output side via the first to fourth flip-around switches S3-1 to S3-4, the law of charge conservation Accordingly, 3.90 V can be output as the output gradation voltage Vout.

Figure 24 (A), in FIG. 24 (B), an explanatory view of a fourth operation example of the output circuit OP ₁ in Figure 20.

  24A and 24B, the first and second gradation voltages when the lower-order 2-bit data D [1: 0] of the gradation data D [5: 0] is “11”. In the example, 3.85V is output as the output gradation voltage between the two. As shown in FIG. 24A, when 4.0 V is applied as the first gradation voltage Vin1 and 3.8 V is applied as the second gradation voltage Vin2 during the sampling period, the first to fourth input switches SI1. Through ~ SI4, 4.0 V is supplied to one of the first to fourth capacitive elements C1 to C4, and 3.8 V is supplied to the remaining three capacitive elements. Then, as shown in FIG. 24B, in the hold period, charge is supplied to the output side via the first to fourth flip-around switches S3-1 to S3-4, so that the law of charge conservation is achieved. Accordingly, 3.85V can be output as the output gradation voltage Vout.

3. Modified Example of Source Driver The flip-around sampling and holding circuit in this embodiment can also be applied to an output circuit of a so-called multi-drive source driver.

  FIG. 25 shows a block diagram of a configuration example of a source driver in a modification of the present embodiment. In FIG. 25, the same portions as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The source driver in this modification is different from the source driver in the present embodiment shown in FIG. 4 in that a multiplexing circuit 56 and a separation circuit 64 are provided. The voltage selection circuit and source line driving that constitute the DAC 60 are provided. To the output circuit constituting the circuit 62, gradation data and gradation voltage are supplied in a time division manner for each source output.

  In FIG. 25, the multiplexing circuit 56 is provided between the line latch 54 and the DAC 60. The separation circuit 64 is provided on the output side of the source line driving circuit 62.

The multiplexing circuit 56 includes multiplexers MPX _{1 to} MPX _k (k is a positive integer), and each multiplexer stores gradation data for one horizontal scan latched by the line latch 54, q (q is a positive integer). However, q × k = N) Multiplexed data multiplexed by time division is generated for each source output.

  FIG. 26 shows an operation explanatory diagram of the multiplexing circuit 56 of FIG.

In FIG. 26, it is assumed that k is 240. In this case, each multiplexer generates multiplexed data obtained by time-division-multiplexing gradation data corresponding to each source output for every 240 source outputs. First to 240 gray-scale data _GD 1 _{to GD 240} for source output captured by the line latch 54, for example, it is multiplexed by a multiplexer MPX ₁ of the multiplexer circuit 56. Each multiplexer of the multiplexer _MPX 1 _{~MPX k,} multiplex control signal SEL1~SEL240 defining the time division timing is input. Such multiplex control signals SEL1 to SEL240 are generated in a control circuit (not shown) of the source driver 30. This control circuit generates the multiplex control signals SEL1 to SEL240 so that, for example, any one of the multiplex control signals SEL1 to SEL240 sequentially becomes H level within one horizontal scanning period. During the period in which each multiplex control signal is at the H level, source output grayscale data corresponding to the multiplex control signal is output as multiplexed data.

  Such a multiplexing circuit 56 may time-division multiplex the gradation data in a plurality of pixel units in which each pixel has a plurality of dots, or gradation in a plurality of dot units of the same color component constituting each pixel. Data units may be time-division multiplexed. For example, when a pixel is composed of 3 dots of RGB, multiplexed data can be generated by time-division-multiplexing each RGB gradation data for 2 pixels. For example, when the pixel is composed of 3 dots of RGB, multiplexed data of R component gradation data, multiplexed data of G component gradation data, and multiplexed B component gradation data of pixels P1 to P6. Each data may be generated.

In FIG. 25, the separation circuit 64 includes demultiplexers DMPX _{1 to} DMPX _k , and each demultiplexer performs an operation opposite to that of the multiplexer of the multiplexing circuit 56 corresponding to the demultiplexer. That is, each demultiplexer separates and outputs the multiplexed gradation voltage from each output circuit of the source line driving circuit 62 into q source outputs. The demultiplexing operation timing of the demultiplexer is synchronized with the time division timing of each multiplexer of the multiplexing circuit 56.

4). Electronic Device FIG. 27 shows a block diagram of a configuration example of an electronic device in the present embodiment. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device. In FIG. 27, the same parts as those in FIG. 1 or FIG.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera and supplies image data captured by the CCD camera to the display controller 38 in the YUV format.

  Mobile phone 900 includes LCD panel 20. The LCD panel 20 is driven by a source driver 30 and a gate driver 32. The LCD panel 20 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels.

  The display controller 38 is connected to the source driver 30 and the gate driver 32, and supplies gradation data in RGB format to the source driver 30.

  The power supply circuit 94 is connected to the source driver 30 and the gate driver 32 and supplies a driving power supply voltage to each driver. Further, the counter electrode voltage Vcom is supplied to the counter electrode of the LCD panel 20.

  The host 940 is connected to the display controller 38. The host 940 controls the display controller 38. The host 940 can supply the gradation data received via the antenna 960 to the display controller 38 after demodulating the modulation / demodulation unit 950. The display controller 38 displays on the LCD panel 20 by the source driver 30 and the gate driver 32 based on the gradation data.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the LCD panel 20 based on operation information from the operation input unit 970.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

FIG. 3 is a diagram illustrating a configuration example of a liquid crystal device according to an embodiment. FIG. 10 is a diagram illustrating another configuration example of the liquid crystal device according to the embodiment. The block diagram of the structural example of the gate driver of FIG. FIG. 3 is a block diagram of a configuration example of the source driver in FIG. 1 or FIG. 2. FIG. 5 is a circuit diagram of a configuration example of an output circuit of the source line driver circuit in FIG. 4. FIG. 6 is an explanatory diagram of a first operation example of the output circuit of FIG. 5. FIG. 6 is an explanatory diagram of a second operation example of the output circuit of FIG. 5. Explanatory drawing of the 3rd operation example of the output circuit of FIG. Explanatory drawing of the 4th operation example of the output circuit of FIG. Operation | movement explanatory drawing in this comparative example. Explanatory drawing of the output order of the gradation voltage in this embodiment. The block diagram of the structural example of the source driver block of the source driver in this embodiment. Explanatory drawing of the addition timing signal of FIG. Operation | movement explanatory drawing of the addition control logic of FIG. FIG. 15A and FIG. 15B are explanatory diagrams of the auxiliary capacitance element CCS. FIG. 6 is a circuit diagram of a configuration example of the operational amplifier circuit of FIG. 5. FIG. 17 is a circuit diagram of a configuration example of the operational amplifier circuit in FIG. 16. FIG. 18 is an operation explanatory diagram of a switch control signal of a sampling hold circuit to which the operational amplifier circuit of FIG. 17 is applied. FIG. 17 is a circuit diagram of another configuration example of the operational amplifier circuit of FIG. 16. The circuit diagram of the structural example of the output circuit of the source line drive circuit of the modification of this embodiment. 21A and 21B are explanatory diagrams of a first operation example of the output circuit of FIG. 22A and 22B are explanatory diagrams of a second operation example of the output circuit of FIG. 23A and 23B are explanatory diagrams of a third operation example of the output circuit of FIG. 24A and 24B are explanatory diagrams of a fourth operation example of the output circuit of FIG. The block diagram of the structural example of the source driver in the modification of this embodiment. FIG. 26 is an operation explanatory diagram of the multiplexing circuit of FIG. 25. 1 is a block diagram of a configuration example of an electronic device according to an embodiment.

Explanation of symbols

10 liquid crystal device, 20 LCD panel, 30 source driver,
32 gate drivers, 38 display controllers, 50 I / O buffers,
52 display memory, 54 line latch, 58 gradation voltage generation circuit,
60 DAC, 62 source line drive circuit, 66 address control circuit,
68 row address decoder, 70 column address decoder,
72 line address decoder, 80 ₁ adder circuit, 82 ₁ add control logic,
90 display driver, 94 power supply circuit, AGND analog ground,
CCS auxiliary capacitive element, C1 first capacitive element, C2 second capacitive element,
DEC _{1 to} DEC _N voltage selection circuit, GL _{1 to} GLM gate line, NEG node, OPC ₁ operational amplifier circuit, OP _{1 to} OP _N output circuit,
SC0-SC4 switch control signal, SL1-SLN source line,
S0 first input switch, S1 second input switch, S2 feedback switch,
S3-1 First flip-around switch,
S3-2 Second flip-around switch, S4 output switch,
Vout output gradation voltage

Claims (10)

A source driver for driving a source line of an electro-optical device,
A gradation voltage generating circuit for generating a plurality of gradation voltages;
From among the gradation voltages of the plurality of gradation voltages generated by the generating circuit, a first and a DAC selects and outputs a gradation voltage of the second gradation voltage corresponding to the grayscale data,
A source line driving circuit for driving the source line based on the first and second gradation voltages,
The source line driving circuit is
Look including a flip-around sample-hold circuit for outputting an output gradation voltages between the first gray-scale voltage and said second gray-scale voltage to the source line,
The flip-around sample-and-hold circuit is
An operational amplifier circuit having an inverting input terminal and a non-inverting input terminal, wherein analog ground is supplied to the non-inverting input terminal;
A plurality of capacitive elements having one ends connected to the inverting input terminal of the operational amplifier circuit;
A ground power supply voltage or the analog ground is supplied to one end, and the other end includes an auxiliary capacitance element to which the inverting input terminal of the operational amplifier circuit is connected;
In the sampling period, in a state where the output of the operational amplifier circuit and the source line are electrically cut off, the inverting input terminal and the output of the operational amplifier circuit are electrically connected, and each of the plurality of capacitive elements A charge corresponding to the first or second gradation voltage is accumulated in the capacitor element,
In the hold period after the sampling period, the inverting input terminal and the output of the operational amplifier circuit are electrically cut off, and the charge accumulated in the plurality of capacitive elements is supplied to the output of the operational amplifier circuit. Output the output voltage of the operational amplifier circuit obtained to the source line,
The auxiliary capacitance element is
A source driver, wherein the source driver is also used as a dummy capacitor element formed in a capacitor element formation region . In claim 1 ,
Each source driver block for driving each source line of the electro-optical device includes a plurality of source driver blocks including the gradation voltage generation circuit and the source line drive circuit,
Each source driver block
A capacitor element forming region in which the first to jth capacitor elements and the auxiliary capacitor element are formed in a direction intersecting an arrangement direction of the plurality of source driver blocks;
The auxiliary capacitance element is
A source driver, wherein the source driver is formed along a boundary facing the array in the direction intersecting the arrangement direction among the boundaries of the capacitor element formation regions. A source driver for driving a source line of an electro-optical device,
A gradation voltage generating circuit for generating a plurality of gradation voltages;
From among the gradation voltages of the plurality of gradation voltages generated by the generating circuit, a first and a DAC selects and outputs a gradation voltage of the second gradation voltage corresponding to the grayscale data,
A source line driving circuit for driving the source line based on the first and second gradation voltages,
The source line driving circuit is
Look including a flip-around sample-hold circuit for outputting an output gradation voltages between the first gray-scale voltage and said second gray-scale voltage to the source line,
The flip-around sample-and-hold circuit is
An operational amplifier circuit having an inverting input terminal and a non-inverting input terminal, wherein analog ground is supplied to the non-inverting input terminal;
A plurality of capacitive elements having one ends connected to the inverting input terminal of the operational amplifier circuit;
In the sampling period, in a state where the output of the operational amplifier circuit and the source line are electrically cut off, the inverting input terminal and the output of the operational amplifier circuit are electrically connected, and each of the plurality of capacitive elements A charge corresponding to the first or second gradation voltage is accumulated in the capacitor element,
In the hold period after the sampling period, the inverting input terminal and the output of the operational amplifier circuit are electrically cut off, and the charge accumulated in the plurality of capacitive elements is supplied to the output of the operational amplifier circuit. Output the output voltage of the operational amplifier circuit obtained to the source line,
The operational amplifier circuit includes:
A source driver , wherein a class A amplification operation is performed during the sampling period, and a class AB amplification operation is performed during the hold period . A source driver for driving a source line of an electro-optical device,
A gradation voltage generating circuit for generating a plurality of gradation voltages;
From among the gradation voltages of the plurality of gradation voltages generated by the generating circuit, a first and a DAC selects and outputs a gradation voltage of the second gradation voltage corresponding to the grayscale data,
A source line driving circuit for driving the source line based on the first and second gradation voltages,
The source line driving circuit is
Look including a flip-around sample-hold circuit for outputting an output gradation voltages between the first gray-scale voltage and said second gray-scale voltage to the source line,
The flip-around sample-and-hold circuit is
An operational amplifier circuit having an inverting input terminal and a non-inverting input terminal, wherein analog ground is supplied to the non-inverting input terminal;
A plurality of capacitive elements having one ends connected to the inverting input terminal of the operational amplifier circuit;
In the sampling period, in a state where the output of the operational amplifier circuit and the source line are electrically cut off, the inverting input terminal and the output of the operational amplifier circuit are electrically connected, and each of the plurality of capacitive elements A charge corresponding to the first or second gradation voltage is accumulated in the capacitor element,
In the hold period after the sampling period, the inverting input terminal and the output of the operational amplifier circuit are electrically cut off, and the charge accumulated in the plurality of capacitive elements is supplied to the output of the operational amplifier circuit. A source driver that outputs the output voltage of the obtained operational amplifier circuit to the source line . In any one of Claims 1 thru | or 4 ,
The operational amplifier circuit includes:
An operational amplifier that amplifies a difference value between an input voltage of the inverting input terminal of the operational amplifier circuit and an output voltage of the operational amplifier circuit;
A first drive transistor of a first conductivity type provided on the first power supply side, the gate electrode of which is controlled based on the voltage of the output node of the operational amplifier;
A second drive transistor of a second conductivity type provided on the second power supply side in series with the first drive transistor;
A capacitor for capacitively coupling the gate electrode of the first driving transistor and the gate electrode of the second driving transistor;
And a charge supply circuit that supplies charge to the gate electrode of the second drive transistor in the sampling period and stops supply of charge to the gate electrode of the second drive transistor in the hold period. Source driver to use. In claim 5 ,
The charge supply circuit comprises:
A current generation circuit;
A switch circuit inserted between the current generation circuit and one end of the capacitor and the gate electrode of the second drive transistor;
The switch circuit is
The source driver is controlled so as to be turned on during the sampling period and turned off during the hold period. In claim 6 ,
The current generating circuit is
A current source transistor that is supplied with current to its drain and is diode-connected,
The switch circuit is
A source driver, wherein the source driver is inserted between the gate electrode of the current source transistor and one end of the capacitor and the gate electrode of the second driving transistor. A plurality of scan lines;
Multiple source lines,
A plurality of pixels each pixel is specified by each scanning line of the plurality of scanning lines and each source line of the plurality of source lines;
Electro-optical device which comprises a source driver according to any one of claims 1 to 7 for driving the plurality of source lines. An electronic apparatus comprising a source driver according to any one of claims 1 to 7. An electronic apparatus comprising the electro-optical device according to claim 8 .

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