JPH11239059A - Digital-to-analog converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a DA converter which makes the voltage of a power supply low, also reduces the number of transistors and has high accuracy. SOLUTION: This converter is provided with a termination circuit of low input impedance which mutually connects each current input terminal of plural differential current switches 110, connects a current source 101 to the connection points and operates a MOS transistors constituting the switches 110 in an on state in a linear area. The operation of the switches 110 is controlled in response to a digital signal and an analog signal is outputted from the termination circuit. The inter-gate/source voltage that turns on the MOS transistors of the switches 110 is set lower than the inter-drain/source voltage of a conventional current source transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / analog converter for converting a digital signal into an analog signal,
In particular, the present invention relates to a digital-to-analog converter suitable for application to information equipment.

[0002]

2. Description of the Related Art In recent years, various information devices have been put on the market, and LSIs used for the devices have been actively developed.
Digital-to-analog converters (hereinafter referred to as “DA converters”) are control systems, display systems, video /
Widely used for audio systems. Many DA converters are
It is mounted in an LSI together with other circuits. On the other hand, information devices have been remarkably developed into portable devices, and low power consumption of LSIs is strongly required. The power supply voltage is generally 5 V, but recently a voltage around 3 V has appeared, and further lowering the voltage is being promoted.

As an example of a general DA converter, there is a current selection type for selecting a current according to a digital signal and outputting an analog signal [for example, IEICE Technical Report No. CAS95-53, IDC95 issued by the Institute of Electronics, Communication and Communication Engineers of Japan. -126 page 55-
60 (September 1995)]. An example of the configuration is shown in FIG.
Shown in This figure shows the case of an 8-bit DA converter, in which 8 bits are divided into upper 5 bits (D7 to D3) and lower 3 bits (D2 to D0).

A current cell matrix 201 is used for the upper 5 bits. 31 current sources (current values are all equal to I _O ) 213 are arranged in a matrix of X rows and Y columns, and X is used to select a current for each X row and Y column.
A decoder 209 and Y decoders 207 and 208 are provided. As a result of the selection, a number of currents (current values I _O ) corresponding to the upper 5 bits of the signal are extracted. The number 31 of current sources is 2 when the total number of bits is k, the number of upper bits is m, and the number of lower bits is n (hence, k = m + n).
^{From m-} 1, it is determined as m = 5. The reason why 1 is subtracted from 2 ^m is that one bit is used for the lower bit.

[0005] One differential current switch is connected to each current source for the selection, and the details of such a current cell matrix 201 are shown in FIG. In the figure, MOS (Metal Oxide Transistor) transistors 401 to 431 of the same shape and the same size, which are biased by a common gate voltage VBU, each generate a current (current value _IO ) as a current source. Each current is supplied to current input terminals 469 to 499 of the differential current switches 438 to 468, respectively. Each switch is composed of a pair of two MOS transistors, and a control signal is supplied to one gate, and the negation of the control signal is supplied to the other gate via an inverter. The potential of the control signal is the ground potential when the signal is "1", and becomes the power supply potential when it is "0". To avoid complicating the drawing, the current sources are arranged not in a matrix but in a straight line. Also, the decoders 207 to 20
9 is simplified and shown as a decode / cell selection circuit 437. The control signal is supplied to a decode / cell selection circuit 437.
Output from

Each of the differential current switches 438 to 468 responds to the input digital signals D7 to D3, and selectively switches the current by turning on one of the transistors and turning off the other transistor. The drains of the transistors to which the control signal is directly supplied to the gate are connected to each other, the positive-phase analog current output _Iout is taken _out from the connection point, and the drains of the transistors to which the negative control signal is supplied to the gate via the inverter are connected. connected, its analog from the connection point of the negative-phase current output I _out ^* (the symbol ^* means a reverse-phase and negative. hereinafter the same) is extracted.

On the other hand, for the lower three bits, a weighted current source 202 with a weighted current value is used (see FIG. 6), and the three types of current sources 218 (current value I _O / 2), 2
One differential current switch is connected to each of I.sub.19 ( _I.sub.O / 4) and 220 ( _I.sub.O / 8), and a weighted current is extracted.

[0008] Both upper and lower bit currents are input to a current-to-voltage converter 214, which is a termination circuit, for each in-phase and each negative phase, and output as an in-phase analog voltage output 1 and a negative-phase analog voltage output 2. The configuration of the DA converter divided into upper bits and lower bits is to reduce the number of circuit elements (transistors). In the current cell matrix 201, a current source is provided for each differential current switch. Therefore, there is a problem that the number of transistors is large.

[0009]

In the above-mentioned conventional DA converter, the MOS transistors 401 to 4 to be manufactured are manufactured.
It is inevitable that the threshold voltage (the gate-source voltage at which the drain current starts flowing) of the transistor 31 varies, and the power supply voltage supplied to these transistors has a voltage gradient (parallel resistance due to the parasitic resistance of the power supply wiring). (A phenomenon in which the power supply voltage drops more in the deeper transistor) is practically unavoidable. The current (drain current) of the current source varies due to such threshold voltage variation and voltage gradient.

In order to suppress this current variation, a MOS
A large drain-source voltage is applied to the transistors 401 to 431, and the transistors are operated in a saturation region. The saturation region is larger than a voltage obtained by subtracting a threshold voltage from a gate-source voltage from a drain-source voltage (hereinafter, this difference voltage is referred to as an “effective gate voltage”), and is set to be, for example, about the same as a gate-source voltage. It is realized by doing. In the saturation region, since the change in the drain current is small with respect to the change in the drain-source voltage, the constant current property of the current source is maintained, and the current variation due to the voltage gradient is suppressed. However, since the drain current in the saturated region is proportional to the square of the effective gate voltage, the influence of the threshold voltage variation is large. As described above, the gate-source voltage is increased, and the threshold voltage is reduced proportionally. doing.

On the other hand, the gate-source voltage applied to the transistors of the differential current switches 438 to 468 may be a low voltage merely for maintaining the ON state, and is set to, for example, about twice the threshold voltage. The power supply voltage is the sum of the drain-source voltage of the MOS transistors 401 to 431 and the gate-source voltage of the transistors of the differential current switches 438 to 468 (the gate voltage of the transistor in the ON state of the switch is the ground potential. Power supply voltage V
Assuming that DD ₁ , the drain-source voltage of the current source transistor is V _DS1 , the gate-source voltage is V _GS1 , the gate-source voltage of the switch transistor is V _GS2 , and the threshold voltage is V _th (the same for each transistor) , Equation (1).

[0012]

## EQU1 ## VDD ₁ = V _DS1 (V _GS1 ) + V _GS2 (≒ 2V _th ) (1) In the conventional DA converter, the effective gate voltage V
To increase _GS1 - _Vth , and thus _VDS1 , VD
Forced to increase the D _1, there is a problem that it is difficult to operate at low supply voltages while maintaining the accuracy.

A main object of the present invention is to solve the above-mentioned problems of the prior art and to provide a high-precision DA converter capable of reducing the voltage of a power supply and reducing the number of transistors. It is in.

[0014]

The object of the present invention is to provide a D
A / A converter comprises a plurality of differential current switches as at least one set of differential current switches, a current input terminal is connected to each group, and a current source is connected to a connection point thereof, and a differential current switch is provided. The problem can be effectively solved by providing a low input impedance termination circuit that operates the MOS transistor constituting the switch in a linear region in an on state. If such a means is adopted, the voltage between the gate and the source of the MOS transistor for the differential current switch and the voltage between the drain and the source of the MOS transistor for the current source can be set to low voltage values. This is because it can be determined as a power supply voltage.

The linear region operation of the differential current switch MOS transistor can be realized by setting the potential of the termination circuit input terminal such that the drain-source voltage of the MOS transistor is lower than the effective gate voltage. Then, in the linear region, the MOS transistor
A low-resistance output resistor is formed between the drain and the source. Therefore, the number of output resistances connected between the mutually connected current input terminals and the positive-phase side and the number of output resistances connected between the negative-phase side are changed by control by digital signals. (The sum of the output resistances on the positive and negative phases is constant.)
The current of the current source is divided by these resistors, and the divided currents of the positive phase side and the negative phase side are respectively input to the input terminals of the termination circuit and output as analog signals. Note that the input terminal of the termination circuit is set to exhibit an impedance sufficiently lower than the output resistance so that the shunting is performed with high accuracy.

In the present invention, it is the output resistance that needs to take the variation into consideration. If the variation range is set to the same level as that of the prior art, the effective gate voltage for operating the transistor in the linear region is reduced. Can be reduced to almost half of the effective gate voltage of the current source transistor described in the above. The reason is that, as a basic property of the MOS transistor, the drain current in the saturation region is proportional to the square of the effective gate voltage, whereas the drain current in the linear region is proportional to the square of the effective gate voltage.
Therefore, the output resistance is inversely proportional to the first power of the effective gate voltage, and as a result, the influence of the variation in the threshold voltage is reduced by half. Since the influence of the threshold voltage variation is halved, the effective gate voltage can be halved, and by setting such a voltage, it is possible to obtain the same level of accuracy as in the past.

When the D / A converter is constituted by a set of differential current switches, that is, when the current source is constituted by a single unit, it is not necessary to consider the variation of the current source transistor, and the drain of the transistor is not required. The source-to-source voltage can be set to be substantially the same as the gate-source voltage in the ON state given to the conventional differential current switch.

As will be described in detail later, the power supply voltage can be determined by the sum of the drain-source voltage of the current source transistor and the gate-source voltage of the differential current switch transistor. From this, the power supply voltage VD of the present invention
D ₂ is expressed by equation (2), where V _{DS3 is} the voltage between the drain and source of the current source transistor, and V _GS4 is the voltage between the gate and source of the current switch transistor.

[0019]

(Equation 2)
VDD ₂ = V _DS3 (≒ 2V _th ) + V _GS4 (2) where

[0020]

V _GS4 −V _th ≒ (1/2) (V _GS1 −V _th ) (3)

[0021]

V _GS4 ≒ V _GS1 − (1/2) (V _GS1 −V _th ) (4) The power supply voltage VDD ₂ is compared with the conventional power supply voltage VDD ₁ . (1/2) (V _GS1 −V _th ).

The case where the current source is constituted as a single unit has been described above. If the number of transistors is small, instead of increasing the voltage between the drain and the source, for example, a transistor having a uniform characteristic is selected from a plurality of transistors. In some cases, it is easy to obtain a transistor with small variations. In such a case, select a transistor having matching characteristics, and select D /
The A-converter may be composed of several sets of differential current switches and the same number of current sources as the number of groups. Even in such a configuration, the effect of reducing the power supply voltage can be obtained.

Next, the type of the current source is one when the DA converter is constituted by only the current cell matrix type or the weighted current source type, and the two types are divided into upper bits and lower bits. Are used, the two types are different from each other, so there are a total of two types.

When the D / A converter is constituted only by a current cell matrix type or a weighted current source type and is constituted by a set of differential current switches, the current source is an analog output capable of being output by the D / A converter. A current value for obtaining the maximum amplitude (normally, the difference between the analog output when all of the digital signals become "1" and the analog output when all of the digital signals become "0") (hereinafter referred to as " _Iref "). ").

When the D / A converter is configured by dividing the upper bit and the lower bit and each of them is constituted by a set of differential current switches, the current of the upper bit current source is
The current value becomes the same current value _Iref as described above, and the current of the current source for the lower bits becomes a current value for obtaining the maximum analog amplitude that can be output by the lower bits (hereinafter, this is represented by “I _O ”). I _O = I _ref / m.

Next, in the current cell matrix type, the number of transistors of each differential current switch is two pairs, and in the weighted current source type, the number of pairs corresponding to the weight is determined for each weight. Is twice as many.

With such a configuration, in the current cell matrix type according to the present invention, the effect that the number of transistors can be reduced as compared with the prior art can be obtained. Although there is no difference in the number of transistors of the differential current switch, the number of current source transistors is two in the prior art.
^{Whereas k} (when the DA converter is configured only with the current cell matrix type) and 2 ^m -1 (when the upper bits of the DA converter are configured with the current cell matrix type),
This is because in the present invention, the number of the differential current switch groups is 1 to a small number.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a DA converter according to the present invention will be described in more detail with reference to the embodiment shown in FIG. 1 and the embodiments shown in FIGS. Note that the same symbols in FIGS. 1 to 5 indicate the same or similar objects.

The D / A converter according to the embodiment of the present invention is divided into upper bits and lower bits. In FIG. 1, reference numeral 109 denotes a current cell matrix type converter for upper bits, and 105 denotes a converter. , A differential current switch group of the converter 109, 112 is a weighted current source type converter for lower bits, 110 is a weighted differential current switch group of the converter 112, and 101 is a reference current. A reference current source 104 is a current mirror circuit which generates a current obtained by duplicating and reducing the current of the reference current source 101 and serves as a current source of the switch groups 105 and 110; 102 is an input terminal for a digital signal of an upper bit; Input terminals 106 and 107 for the lower bit digital signal are X-row Y-column matrix for converting the upper bit digital signal into a signal for controlling the switch group 105. X decoder, Y decoder, 10
Reference numeral 8 denotes a latch circuit for equalizing the delay amounts of the output signals of the decoders 106 and 107, and reference numeral 111 denotes a latch circuit for adjusting the delay amount of the lower-order digital signal to make the conversion timing of the converter 112 coincide with that of the converter 109. Latch circuit, 1
Reference numeral 13 denotes a terminating circuit, which is a current-voltage converter that inputs the output currents of the converters 105 and 112 and outputs an analog signal output voltage.

The switch group 105 includes an MO operating in a linear region.
A plurality of differential current switches composed of S transistors (FIG. 1
, Which will be described later) are arranged in X rows and Y columns. The current input terminals of these switches are connected in common, and a current from the current mirror circuit 104 is supplied to the terminals. The current from the current mirror circuit 104 is divided by the output resistance of the MOS transistor operating in the linear region, and each differential current switch is connected to the decoder 106,
Under the control of 107, the divided current is distributed in one of two directions. As a result, a shunt ratio according to the input digital signal is determined, and a predetermined current is extracted.

The switch group 110 has an MO operating in a linear region.
A plurality of weighted differential current switches (not shown in FIG. 1) composed of S-transistors are arranged in one row. Due to the weight, digital signals are directly input to the switches without passing through a decoder. The operation of the switch group 110 is basically the same as that of the switch group 105.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The DA converter according to the present embodiment is configured such that the number of bits of an input digital signal is 10 bits, its upper 7 bits are of a current cell matrix type, and its lower 3 bits are of a weighted current source type. , Each comprising a set of differential current switches.

In FIG. 2, reference numeral 501 denotes a DA converter;
2 is an input terminal for digital signals (D9 to D0), 513
Are differential current switches connected to the output terminal of the current mirror circuit 104, 516 to 518 are weighted differential current switches connected to the output terminal of the current mirror circuit 104, and 506 and 507 are current-voltage converters. 113 voltage output positive and negative phase analog signal output terminals,
Reference numeral 520 denotes a control signal for controlling the conversion timing of the latch circuits 108 and 111. The control signal 52
By the control of 0, the analog voltage output of the output terminals 506 and 507 retains the previous conversion result until the next control signal is input. In addition, the latch circuits 108 and 111
By adjusting the conversion timing, generation of glitches (impulse-like noise) caused by delay variations of the control signal and the lower bits is suppressed.

The reference current source 101 generates a reference current of the current value I _ref, from the current mirror circuit, which duplicate, the reduced two current (current value I _ref, I _O) to output a. The current value I _ref is a current having the maximum analog amplitude as described above, and the current value I _O is I _ref / 128 where m = 7 when I _O = I _ref / 2 ^m .

The differential current switch 513 is 2 ^m −1 = 1
There are 27, and one is reduced in 8 rows and 16 columns. Not limited to this arrangement, it is possible to use 16 rows and 8 columns (one is reduced), 1 row and 127 columns, and the like. The reason why one is reduced is that the lower bit can supply the current for one as described above. However, since I _ref needs to be divided by 2 ^m ,
A dummy circuit for constantly flowing I _O irrespective of a digital signal was connected to the portion of the switch group 105 shown in FIG.

Each of the differential current switches 513 shunts the current of the current value I _{ref to convert} the current of the current value I _O into the positive phase,
The output is distributed to one of the opposite phases. Therefore, the differential current switch group 105 sets the digital signal value to 0
If one of the integers p to 127 is made to correspond, pIO is _output to the positive phase side and (127-p) _IO is output to the negative phase side.

Next, the weighted differential current switches 516 to
518 distributes a current corresponding to the bit weight according to the input of the digital signals D2 to D0. The digital signals D2 to D0 are supplied directly to the individual current switches via the latch circuit 111 without the necessity of decoding because the currents are weighted. The current I _O is weighted and shunted by each current switch, and the current switch 516
The _O / 2 of the current, the current switch 517 I _O / 4 of the current, the current switch 518 outputs distributes a current of I _O / 8 to each positive phase side or the reverse phase side.

Table 1 shows the relationship between the output current and the value of each bit of the input digital signals D2 to D0.

[0039]

[Table 1]

If the input value is binary (000), the output current is 0, if binary (001), I _O / 8, if binary (010), 2 (I _O / 8) current Flows. Thereafter, each time the input value increases by 1, the output current increases by I _O / 8,
When the input value is a binary number (111), a current of 7 ( _IO / 8) is output.

Next, the configuration and operation principle of the differential current switch 513 will be described with reference to FIG. In Figure 3a, SW is shows the switch 513 in the symbol, 701, terminal for receiving a current I _in, 70
Reference numeral 2 denotes an input terminal of the digital signal D, reference numeral 703 denotes an output terminal of the current I _out distributed to the positive phase side by control of the digital signal D, and reference numeral 704 denotes an output terminal of the current I _out ^* distributed to the negative phase side. .

The actual circuit of switch 513 is shown in FIG. In the figure, reference numerals 705 and 706 denote Ms forming a differential pair.
The OS transistor 708 indicates an inverter that inverts the digital signal D and outputs its negation D ^* . MOS
Transistors 705 and 706 have the same channel length and channel width, and are formed of a source-coupled pair laid out in consideration of matching. The common source becomes an input terminal 701 to which the current _Iin is input. The input terminal 702 is connected to the gate of the transistor 705, and the output terminal of the inverter 708 is connected to the gate of the transistor 706. Further, the drain of the transistor 705 is connected to the output terminal 703, and the drain of the transistor 706 is connected to the output terminal 704.

With such a configuration, the digital signal D
And one of the transistors 705 and 706 is turned on and the other is turned off according to the negative D ^{* of the} output of the inverter 708,
The input current I _in is output from the output terminal 703 or the output terminal 704.
Flows _out to only one of the two, the current I _out or the current I _out
out ^* . Note that "1" of the digital signal D is a ground potential, and "0" is a power supply potential.

The output terminal 703 and the output terminal 704 are connected to the positive-phase input terminal and the negative-phase input terminal of the current / voltage converter 113, respectively. In the present embodiment, the transistors 705 and 706 are operated in the linear region in the on state. Therefore, as will be described in detail later, when the transistors 705 and 706 are in the ON state (that is, when the gate potential is the ground potential), the gate-source voltage exceeds the threshold voltage, and the drain The potentials of both input terminals of the current-to-voltage converter 113 are set so that the source voltage is lower than the effective gate voltage and that an appropriate potential is applied to the connected current mirror 104 (see FIG. 2).

Since the characteristics of the transistors 705 and 706 are the same, the circuit of FIG. 3B is equivalent to the circuit of FIG. 3C in which two equal-valued output resistors are replaced. That is, FIG.
The circuit b can be regarded as a circuit in which the input terminal 701 is connected to the output terminal 703 via the resistor 714 or is connected to the output terminal 704 via the resistor 716. Since the impedance of the input terminal of the current-voltage converter 113 is set to a low value, the input terminal 701
Is constant at the value of the output resistance regardless of the state of the digital signal.

The differential current switch group 105 (see FIG. 2) was constituted by arranging 127 of the above differential current switches 513 in a matrix. The sources of each switch are all connected to the output terminal of the current mirror circuit 104.

The current mirror circuit 104 shown in FIG.
FIG. 4 shows an actual circuit for the upper bits by the current-voltage converter 113 and the current cell matrix type converter 109. In the figure, reference numeral 801 denotes a current having a current value _Iref , 8
02 is a current mirror circuit 10 that outputs a current 801
A transistor 817 is an output terminal of the current 801 (drain of the transistor 802), and 803 to 810
Are the transistors of the differential current switch 513 shown in FIG. 3B, 813 to 816 are the inverters of the differential current switch 513 also shown in FIG. 3B, 824 is a decode / cell selection circuit, and 840 and 841 are dummy 1 shows a transistor of a circuit.

The transistor 802 has a source connected to a power supply (voltage VDD ₂ ), a gate supplied with a bias 850 (voltage VB ₁ ) from the reference current source 101, and outputs a current 801 from a drain. The differential current switch 513 and the common source of the dummy circuit were connected to the output terminal 817. Therefore, the output terminal 817 is also a connection point connecting the current input terminals of the respective differential current switches 513 to each other. Although 127 differential current switches 513 were used,
In FIG. 4, four are arranged in series to avoid complexity. The decode / cell selection circuit 824 is a simplified version of the X decode 106, the Y decode 107 and the latch circuit 108 shown in FIG. 2, and receives digital signals D9 to D3.

The control signal output from the decode / cell selection circuit 824 is supplied to one gate of each differential current switch, and the negative control signals output from the inverters 813 to 816 are:
It is supplied to the other gate of each differential current switch. When the control signal is “1”, the potential is the ground potential GND, and when the control signal is “0”, the potential is the power supply potential VDD ₂ . At that time, the negative control signal has the opposite potential. Then, the transistor when the potential of the gate of the ground potential GND is turned on, turned off when the power supply potential VDD _2.

Transistor 80 supplied with a control signal
The drains of 4, 806, 808, and 810 are connected to a common output terminal 818, and a positive-phase output current to the output terminal 818 is supplied to a positive-phase input terminal of the current-voltage converter 113. Transistors 803 and 8 to which a negative control signal is supplied
The drains 05, 807, and 809 are connected to a common output terminal 819, and a negative-phase output current to the output terminal 819 is supplied to a negative-phase input terminal of the current-voltage converter 113. Note that the dummy circuit, the gate terminal 842 of the transistor 840 provides a ground potential GND, and was kept always on the transistor 840 given to the gate terminal 843 of the transistor 841 to the power supply potential VDD _2.

The potential of both input terminals of the current-voltage converter 113 is made equal, and the potential of the output terminal 817 is set to VDD.
_2- V _DS3 was set. Since the gate potential of the on-state transistor is the ground potential GND, the gate-source voltage V
_GS4 will VDD ₂ -V _DS3. That is, as shown in equation (2), VDD ₂ = V _DS3 + V _GS4 . Note that the voltage between the drain and source of the transistor that operates in the linear region in the ON state is extremely low, and the potential of both input terminals of the current-to-voltage converter 113 is slightly lower than VDD ₂ −V _DS3 .

By setting such a potential, the output resistances of the transistors in the ON state are equalized by the same resistance value (hereinafter, this is represented by "R _O1 "). Further, as described above, since the impedance of the input terminal of the current-voltage converter 113 is set sufficiently lower than this resistance value R _O1 , the impedance seen from the output terminal of the current mirror circuit 104 on the switch side becomes the digital signal. R _O1 regardless of the state of
/ 128, and therefore the potential of the output terminal is also constant (the output resistance of the dummy circuit also has the same resistance value R _O1 ). Therefore, the current 801 (current value I _ref ) is 128
A current having a current value I _O flows into each differential current switch by being equally divided.

In response to the digital signal, p output resistors are connected between the output terminal of the current mirror circuit 104 and the common positive-phase output terminal 818 of each differential current switch, and the current-voltage converter 113 analog current output I _out of the current value pI _O to the positive phase side input terminal is input, 127
−p output resistors are connected between the output terminal of the current mirror circuit 104 and the negative-phase input terminal 819 of the current-voltage converter 113, and the current value (127) is connected to the negative-phase input terminal of the current-voltage converter 113. −p) I _O analog current output I _out ^*
Is entered.

The current-voltage converter 113 comprises a high-gain operational amplifier 821 and an in-phase feedback amplifier 828 as shown in the lower right part of FIG.
A power supply that supplies the intermediate potential VOCM of 507 and the potential of the input terminal of the converter 113 to the input terminal 827 of the amplifier 828
It is controlled to be equal to VCMFB. Output terminal 5
06, 507 is obtained at the connection point between resistors 829 and 830 having the same resistance value connected between both terminals. Potential of the input and output terminals becomes equal due to the feedback action of the feedback resistor RFB. By using such a converter 113, the potential of the power supply VCMFB was adjusted to set the potential of the output terminal 817 of the current source transistor 802 to a predetermined voltage value. Note that each input terminal of the converter 113 exhibits a remarkably low impedance due to the feedback action of the feedback resistor RFB.

Finally, the output terminal 825 of the converter 113
, A positive-phase voltage output 1 of a voltage value of I _out RFB;
At the output terminal 826, a negative-phase voltage output 2 of the voltage value of I _out ^* RFB is obtained.

Next, the weighted differential current switches 516 to 518 shown in FIG. 2 are realized by replacing each of the transistors 705 and 706 shown in FIG. 3B with a number of parallel-connected transistors corresponding to the weight. be able to.

FIG. 5 shows an actual circuit for the lower bits by the current source type converter 112 using the parallel-connected transistor and the current mirror circuit 104 and the current-voltage converter 113 shown in FIG. In FIG.
07 is a current of the current value I _O , 906 is a transistor of the current mirror circuit 104 which outputs a current 907, 90
Reference numeral 5 denotes an output terminal of the current 907 (drain of the transistor 906), and reference numeral 904 denotes a dummy circuit.

The transistor 906 has a source connected to a power supply (voltage VDD ₂ ), a gate supplied with a bias 925 (voltage VB ₂ ) from the reference current source 101, and outputs a current 907 from a drain. The current switches 516 to 518 and the current input terminal (common source) of the dummy circuit 904 were connected to the output terminal 905. That is, the output terminal 90
5 is also a connection point of each current input terminal of the current switches 516 to 518.

Each of the current switches 516 to 518 has a number of transistors corresponding to the weight. That is,
The switch 516 has a total of eight pairs of four transistors,
The switch 517 has a total of four switches of two transistors,
The number of switches 518 is two in one pair. Each transistor was the same transistor having the same channel length and channel width. Since the current flowing through these transistors is a fraction of that in the case of the current switch 513, the dimensions of the transistors are reduced, and the resistance value of the output resistance is set to R _O2 . Therefore, the current switch 516
To 518 are R _O2 / 4 and R _O2 /
2 and R _O2 , and the switches 516 and 51 are determined by the resistance value and the output resistance (resistance value R _O2 ) of the dummy circuit 904.
7, 518 can shunt the current value I _O to obtain the respective currents of the current values I _O / 2, I _O / 4, and I _O / 8 (the current value of the dummy circuit is I _O / 8).

The digital signals D2 to D0 are supplied to the respective differential current switches, and when "1", the potential is changed to the ground potential GN.
D, the potential at "0" become the power supply potential VDD _2, respectively OFF control transistor.

Each of the drains of the transistors to which the digital signals D2 to D0 are directly supplied has a common output terminal 818.
And the positive-phase output current to the output terminal 818 is supplied to the positive-phase input terminal of the current-voltage converter 113. Each drain of a transistor to which the same digital signal is supplied via an inverter is connected to a common output terminal 819, and a negative-phase output current to the output terminal 819 is supplied to a negative-phase input terminal of the current-voltage converter 113. Is done.

By setting the potential of both input terminals of the current-voltage converter 113, the potential of the output terminal 907 becomes VDD ₂ −V _DS3 as in the case of the upper 7 bits. In addition, the gate-source voltage V _GS4 of the on-state transistor is V
Become DD ₂ -V _DS3.

By setting such a potential, the output resistances of the transistors in the ON state are equalized by the resistance value R _O2 , and the shunt currents 925 to 928 are obtained. And
According to the values of the digital signals D2 to D0, the output terminal 81
8, an in-phase analog current output I _out is provided at an output terminal 819.
, An _out- of-phase analog current output I _out ^* flows.

Finally, these currents are added to the upper 7-bit current, and the output terminal 506 of the current / voltage converter 113 is added.
And a negative-phase voltage output 2 can be obtained at the output terminal 507.

As described above, in the DA converter of the present invention, it is possible to adopt a voltage value VDD ₂ lower than that of the conventional power supply, and it is possible to reduce the power supply voltage.

[0066]

According to the present invention, the current is shunted by utilizing the output resistance in the linear region of the MOS transistor, so that the gate-source voltage can be set lower than in the prior art. Voltage can be reduced. In the current cell matrix type, one or a small number of current sources are connected to a plurality of differential current switches, so that the number of transistors can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram for explaining an embodiment of a digital-to-analog converter according to the present invention.

FIG. 2 is a circuit block diagram for explaining an embodiment of the digital-to-analog converter of the present invention.

FIG. 3 is a diagram illustrating the concept, configuration, and operation principle of a differential current switch.

FIG. 4 is a diagram for explaining a first circuit example of the embodiment of the present invention.

FIG. 5 is a diagram for explaining a second circuit example of the embodiment of the present invention.

FIG. 6 is a circuit block diagram for explaining a conventional digital / analog converter.

FIG. 7 is a diagram illustrating a circuit example of a conventional digital-to-analog converter.

[Explanation of symbols]

101: current source, 104: current mirror circuit, 10
5, 110: differential current switch group, 109: current cell matrix type converter, 112: weighted current source type converter,
113 ... current-voltage converter, 705, 706, 802-8
10,840,841,906 ... MOS transistor,
513: differential current switch, 701: current input terminal, 5
16 to 518: Weighted differential current switch, 817, 9
05: Current input terminal connection point (current source output terminal), D9 to D
0: Digital signal, _Iout , _Iout ^* : Analog current output.

Claims (6)

[Claims] 1. A plurality of differential current switches having a current input terminal and distributing a current input to the terminal in two directions;
And a terminating circuit for inputting the distributed current, wherein each of the plurality of differential current switches is a MOS transistor forming a differential pair.
A digital-to-analog converter comprising a transistor, controlling the on / off of the MOS transistor in response to a digital signal, controlling the distribution operation of a plurality of differential current switches, and outputting an analog signal from a termination circuit. The plurality of differential current switches constitute at least one differential current switch group, current input terminals are connected to each other for each group, and a current source is connected to the connection point; The circuit has an input terminal that has a potential that causes the MOS transistor to operate in a linear region in an on state, and has an input terminal that exhibits an impedance sufficiently lower than the output resistance of a MOS transistor that operates in a linear region. Digital-to-analog converter. 2. The digital-to-analog converter according to claim 1, wherein each of said differential current switches comprises two MOS transistors forming a pair. 3. The digital-to-analog converter according to claim 1, wherein each of said differential current switches comprises a number of pairs of MOS transistors corresponding to a weight set for each of said differential current switches. 4. The plurality of differential current switches constitute a set of differential current switches, and the current source outputs a single current which outputs a current having a maximum value of an analog signal. 4. A digital-to-analog converter according to claim 1, wherein the digital-to-analog converter is a source. 5. A bit of a digital signal is divided into an upper bit and a lower bit, and a converter for the upper bit comprises the digital / analog converter according to claim 2,
4. A digital-to-analog converter according to claim 3, wherein the converter for the lower bits comprises the digital-to-analog converter according to claim 3. 6. A converter for the upper bits, wherein a set of a first differential current switch group and a single first current for outputting a current having a current value at which an output of an analog signal is maximum. And a converter for the lower order bits comprises a set of second
6. The differential current switch group according to claim 5, further comprising a second current source that outputs a current having a current value that maximizes the output of an analog signal based on the digital signal of the lower bit. Digital-to-analog converter.