KR101212157B1 - Data driving circuit, apparatus and method for driving of flat panel display device using the same - Google Patents

Abstract

The present invention relates to a data driving circuit capable of reducing current consumption, a driving apparatus and a driving method of a flat panel display device using the same.

According to another aspect of the present invention, a data driving circuit includes a shift register array unit configured to generate a sampling signal; A latch array section for latching low voltage M (where M is a positive integer) bit digital data in accordance with a sampling signal; A level shifter array unit for converting some bits of the low voltage M bit digital data latched according to the text mode signal into the high voltage digital data; A digital-to-analog conversion array unit for converting M-bit digital data including high voltage digital data converted by the level shifter array unit into an analog image signal; And an output buffer array unit configured to buffer and output the analog image signal.

Data driver circuit, level shifter, current consumption

Description

DATA DRIVING CIRCUIT, APPARATUS AND METHOD FOR DRIVING OF FLAT PANEL DISPLAY DEVICE USING THE SAME}

1 is a view schematically illustrating a driving device of a flat panel display device according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram schematically illustrating a data driving circuit shown in FIG. 1.

FIG. 3 is a diagram showing M-bit digital data supplied to the data driving circuit shown in FIG.

4 is a schematic view of the level shifter portion shown in FIG.

<Explanation of Signs of Major Parts of Drawings>

106: data driving circuit 120: shift register array unit

122: latch array portion 124: level shifter array portion

126: DAC array unit 128: output buffer array unit

130: switching unit 132: level shifter unit

134: selection unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driving circuit, and more particularly, to a data driving circuit capable of reducing current consumption, a driving apparatus, and a driving method of a flat panel display device using the same.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Examples of such flat panel display devices include a liquid crystal display, a field emission display, a plasma display panel, and a light emitting display.

Among the flat panel displays, the liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel having a liquid crystal cell and a driving circuit for driving the liquid crystal panel. The driving circuit drives the liquid crystal cell so that the image information is displayed on the liquid crystal panel.

Specifically, the driving circuit includes a gate driving circuit for supplying scan pulses to the liquid crystal panel, a data driving circuit for supplying an image signal to the liquid crystal panel, and a timing controller for controlling each of the gate and the data driving circuit. .

The timing controller arranges the data from the outside to be suitable for driving the liquid crystal panel, supplies the data to the data driving circuit, and generates a control signal for controlling each of the gate and the data driving circuit.

The gate driving circuit sequentially generates scan pulses according to a control signal from the timing controller, and sequentially supplies the scan pulses to the gate lines of the liquid crystal panel.

The data driving circuit converts the data from the timing controller into an analog image signal according to the control signal from the timing controller and supplies the data to the data lines of the liquid crystal panel.

On the other hand, in recent years, the size of the liquid crystal panel is increasing due to technology development. Accordingly, the area and power consumption of the data driving circuit for driving the liquid crystal panel are increasing.

Accordingly, Korean Patent Publication No. 2005-0081608 (a multilevel shifter circuit of a flat panel source driver having a small chip area and a small current consumption) proposes a multilevel shifter circuit of a flat panel source driver having a relatively small chip area and a small current consumption. It became.

Such a conventional multi-level shifter circuit includes a voltage drop unit for dropping a power supply voltage and outputting a dropped power supply voltage; And a plurality of level shifters using the dropped power supply voltage in common, and receiving a plurality of bits of data and converting the levels thereof.

However, the conventional multi-level shifter circuit has a problem in that current consumption is large because digital data applied from the outside converts the level of the digital data irrespective of moving images and still images.

For example, if the digital data is 6 bits, the still image such as text fixes the remaining bit data except the most significant bit data to a value of "1" or "0", and the most significant bit data (or higher). 3 bit data) to display. Accordingly, the conventional multi-level shifter circuit converts the levels of all the bit data when displaying a still image, resulting in large current consumption.

Accordingly, in order to solve the above problems, an object of the present invention is to provide a data driving circuit and a driving apparatus and driving method of a flat panel display device using the same to reduce the current consumption.

A data driving circuit according to an embodiment of the present invention for achieving the above object includes a shift register array unit for generating a sampling signal; A latch array section for latching low voltage M (where M is a positive integer) bit digital data in accordance with a sampling signal; A level shifter array unit for converting some bits of the low voltage M bit digital data latched according to the text mode signal into the high voltage digital data; A digital-to-analog conversion array unit for converting M-bit digital data including high voltage digital data converted by the level shifter array unit into an analog image signal; And an output buffer array unit configured to buffer and output the analog image signal.

The text mode signal is in a first logic state when the low voltage M bit digital data is image data, and in a second logic state when the low voltage M bit digital data is text data.

The level shifter array unit converts each of the latched low voltage M bit digital data into high voltage digital data according to the text mode signal of the first logic state, and the latched low voltage M according to the text mode signal of the second logic state. The low-voltage MN bit digital data except for the low voltage N (where N is a positive integer smaller than M) bit digital data among the bit digital data may be converted into high voltage digital data.

The level shifter array unit and the switching unit for selectively outputting each of the low voltage N (where N is a positive integer less than M) of the low voltage M bit digital data supplied from the latch array unit in accordance with the text mode signal; ; A level shifter for converting low voltage M-N bit digital data excluding the low voltage N bit digital data and low voltage N bit digital data from the switching unit into the high voltage M bit digital data using a driving voltage and a base voltage; And a selection unit for selecting and outputting any one of high voltage N-bit digital data from the level shifter unit and an external power source according to the text mode signal.

According to an exemplary embodiment of the present invention, a flat panel display includes: a display panel displaying an image, a gate driving circuit supplying scan pulses to the display panel; The data driving circuit; And a timing controller for supplying the low voltage M-bit digital data to the data driving circuit and controlling each of the gate and the data driving circuit.

According to an aspect of the present invention, there is provided a method of driving a flat panel display, the method for displaying an image by supplying an analog image signal to a display panel. A first step of generating a sampling signal; Latching a low voltage M (where M is a positive integer) bit digital data in accordance with the sampling signal; Converting some bits of the low voltage M bit digital data latched in accordance with the text mode signal into high voltage digital data; A fourth step of converting the M-bit digital data including the converted high voltage digital data into an analog image signal; And a fifth step of buffering and outputting the analog image signal.

The text mode signal is in a first logic state when the low voltage M bit digital data is image data, and in a second logic state when the low voltage M bit digital data is text data.

The third step converts each of the latched low voltage M bit digital data into high voltage digital data according to the text mode signal of the first logic state, and the latched low voltage M bit according to the text mode signal of the second logic state. Among the digital data, low voltage MN bit digital data except low voltage N (where N is a positive integer smaller than M) bit digital data is converted into high voltage digital data.

The third step may include a step 3-1 of selectively outputting low voltage N (where N is a positive integer less than M) bit digital data among the latched low voltage M bit digital data according to the text mode signal; A step 3-2 of converting the low voltage M-N bit digital data and the low voltage N bit digital data except the low voltage N bit digital data into the high voltage M bit digital data using a driving voltage and a base voltage; And a third step of selecting and outputting any one of the high voltage N-bit digital data and an external power source according to the text mode signal.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

1 is a view schematically illustrating a data driving circuit and a driving apparatus of a liquid crystal display using the same according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a data driving circuit and a driving device of a liquid crystal display using the same according to an exemplary embodiment of the present invention are regions defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. A liquid crystal panel 102 each having a liquid crystal cell; A gate driving circuit 104 which sequentially supplies scan pulses to the plurality of gate lines GL1 to GLn; Low voltage M (where M is a positive integer) bit digital data (R, G, B) input according to the text mode signal TMS by the user converts some bits of the high voltage digital data and converts the converted high voltage digital data A data driver circuit 106 for converting digital data including an analog image signal into an analog image signal and supplying the digital data to the data lines DL1 through DLm; And a timing controller 108 for supplying the low voltage M-bit digital data R, G, and B to the data driving circuit 106 and controlling the gate and the data driving circuits 104 and 106, respectively.

The liquid crystal panel 102 includes a thin film transistor TFT formed in a region defined by n gate lines GL1 through GLn and m data lines DL1 through DLm, and a liquid crystal connected to the thin film transistor TFT. With cells. The thin film transistor TFT supplies a data signal from the data lines DL1 to DLm to the liquid crystal cell in response to a scan pulse from the gate lines GL1 to GLn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell also includes a storage capacitor Cst for maintaining the data signal charged in the liquid crystal capacitor Clc until the next data signal is charged.

The timing controller 108 arranges the M-bit digital data supplied from the outside to the data driving circuit 106 in alignment with the driving of the liquid crystal panel 102. In addition, the timing controller 108 uses the dot clock DCLK, the data enable signal DE, and the horizontal and vertical synchronization signals Hsync and Vsync, which are input from the outside, to control the data control signal DCS and the gate control signal ( A GCS is generated to control driving timing of each of the data driving circuit 106 and the gate driving circuit 104.

The gate driving circuit 104 sequentially generates scan pulses, that is, gate high pulses, according to the gate control signal GCS from the timing controller 108, and sequentially supplies the gate pulses to the n gate lines GL1 to GLn.

The data driving circuit 106 is a low-voltage M (where M is a positive integer) bit digital data R, supplied from the timing controller 108 in accordance with the data control signal DCS supplied from the timing controller 108. Latches G and B, converts some bits of the low voltage M bit digital data R, G and B latched according to the text mode signal TMS by the user into high voltage digital data, and converts the converted high voltage digital data. Convert the digital data including the to an analog image signal. The data driving circuit 106 supplies an analog image signal for one horizontal line to the data lines DL1 to DLm every horizontal period in which scan pulses are supplied to the gate lines GL1 to GLn. Here, the text mode signal TMS is generated in a low state when the display image displayed on the liquid crystal panel 102 by the user is changed from a moving image to a still image, and becomes a high state otherwise. . That is, the text mode signal TMS may be generated when a user writes or reads a character in the mobile communication terminal.

To this end, the data driving circuit 106 includes a shift register array unit 120 for generating a sampling signal as shown in FIG. A latch array unit 122 for latching low voltage M-bit digital data in accordance with a sampling signal; A level shifter array unit 124 for converting some bits of the low voltage M bit digital data R, G, and B latched according to the text mode signal TMS into high voltage digital data; A digital-to-analog converter (hereinafter referred to as a "DAC") array unit 126 for converting M-bit digital data including high voltage digital data converted by the level shifter array unit 124 into an analog image signal. Wow; And an output buffer array unit 128 for outputting analog image signals to the data lines DL1 to DLm.

The shift register array unit 120 sequentially generates a sampling signal using the source start pulse SSP and the source shift clock SSC of the data control signal DCS from the timing controller 108 to generate the latch array unit 122. Supplies).

The latch array unit 122 latches the low voltage M-bit digital data R, G, and B supplied from the timing controller 122 according to the sampling signal from the shift register array unit 120. At this time, the latch array unit 122 latches the low voltage M-bit digital data R, G, and B for one horizontal line, and is latched according to the source output enable signal SOE of the data control signal DCS. Outputs low-voltage M-bit digital data (R, G, B) for horizontal lines.

The level shifter array unit 124 converts each of the low voltage M bit digital data latched according to the text mode signal in the high state into high voltage digital data, and the low voltage among the latched low voltage M bit digital data in accordance with the text mode signal in the low state. Converts low voltage MN bit digital data to high voltage digital data except for N (where N is a positive integer less than M) bit digital data.

To this end, the level shifter array unit 124 is a low-voltage N-bit digital data (R, G of the low-voltage M-bit digital data (R, G, B) supplied from the latch array unit 122 in accordance with the text mode signal (TMS) Switching unit 130 for selectively outputting, B); The low voltage MN bit digital data (R, G, B) supplied from the latch array unit 122 and the low voltage N bit digital data (R, G, B) from the switching unit 130 are converted into the high voltage M bit digital data (R, G). A level shifter unit 132 for converting to G and B); And a selector 134 for selecting and outputting any one of the high voltage N-bit digital data R, G, and B from the level shifter 132 and an external power source according to the text mode signal TMS.

Here, it is assumed that the low voltage M-bit digital data R, G, and B are 6 bits D0 to D5 as shown in FIG. In this case, grayscale is implemented using 6 bits (D0 to D5) in the case of video data, whereas "1" or "0 is selected as the lower two bit data (D0, D1) among 6 bits (D0 to D5) in case of text data. It is fixed to the value of "and implements the text gradation with the gradation value of the remaining 4 bits (D2 to D5). The number of bits for implementing the text gradation may vary depending on the system.

As shown in FIG. 4, the switching unit 130 is connected between the lower first bit transmission line of the low voltage M bit digital data R, G, and B and the level shifter unit 132 to the text mode signal TMS. Accordingly, the first transistor T1 supplies the lower first bit data D0 to the level shifter unit 132, and the lower second bit transmission line and the level shifter unit of the low voltage M bit digital data R, G, and B. And a second transistor T2 connected between the 132 and supplying the lower second bit data D1 to the level shifter 132 according to the text mode signal TMS.

The first transistor T1 is turned on according to the text mode signal TMS in the high state to supply the lower first bit data D0 to the level shifter 132 while the text mode signal TMS in the low state. ) And turns off the lower first bit data D0 supplied to the level shifter unit 132.

The second transistor T2 is turned on according to the text mode signal TMS in the high state to supply the lower second bit data D1 to the level shifter 132 while the text mode signal TMS in the low state. ) And turns off the second lower bit data D1 supplied to the level shifter unit 132.

The level shifter unit 132 includes six level shifters LS0 to LS5 having low voltage 6-bit digital data R, G, and B connected to each bit transmission line, as shown in FIG.

Each of the six level shifters LS0 to LS5 uses the driving voltage VDD and the ground voltage VSS supplied from the outside to respectively convert the low voltage 6 bit digital data D0 to D5 into the high voltage 6 bit digital data (D0 '. To D5 ').

Each of the first and second level shifters LS0 and LS1 of the six level shifters LS0 to LS5 is operated to correspond to the switching of each of the first and second transistors T1 and T2. That is, each of the first and second level shifters LS0 and LS1 may be turned on to supply the digital data D0 and D1 according to the text mode signal TMS. Will only work.

As shown in FIG. 4, the selector 134 selects the high voltage first bit digital data D0 ′ and the base voltage VSS supplied from the first level shifter LS0 according to the text mode signal TMS. A second multiplexer M1 for outputting and a second multiplexer for selecting and outputting the high voltage second bit digital data D1 'supplied from the second level shifter LS1 and an external power source according to the text mode signal TMS; And M2). Here, the external power source may be any one of the driving voltage VDD and the base voltage VSS.

The first multiplexer M1 supplies the high voltage first bit digital data D0 'to the DAC array unit 126 according to the text mode signal TMS in the high state, and in accordance with the text mode signal TMS in the low state. The base voltage VSS is supplied to the DAC array unit 126.

The second multiplexer M2 supplies the high voltage second bit digital data D1 'to the DAC array unit 126 according to the text mode signal TMS in the high state, and in accordance with the text mode signal TMS in the low state. The base voltage VSS is supplied to the DAC array unit 126.

Meanwhile, the driving voltage VDD may be supplied to the first and second multiplexers M1 and M2 instead of the base voltage VSS.

In FIG. 2, the DAC array unit 126 converts the high voltage 6-bit digital data supplied from the level shifter array unit 124 into an analog image signal by using a plurality of input gamma voltages GMA.

The output buffer array unit 128 buffers the analog image signal from the DAC array unit 126 and supplies it to the data lines DL1 to DLm.

Such a data driving circuit and a driving apparatus and driving method of a flat panel display device using the same according to an embodiment of the present invention are low-voltage 6-bit digital data (R, G, By converting the upper four bits of B) into high voltage digital data, the current consumption of the data driving circuit 104 can be reduced.

Meanwhile, in the above-described data driving circuit and driving device and driving method of the flat panel display device using the same, the liquid crystal display device is described as an example, but is not limited thereto. The present invention may also be applied to a flat panel display including the device.

On the other hand, the present invention described above is not limited to the above-described embodiments and the accompanying drawings, it is a technology that the various permutations, modifications and changes are possible within the scope without departing from the spirit of the present invention It will be apparent to those skilled in the art.

As described above, the data driving circuit and the driving apparatus and driving method of the flat panel display using the same convert the low voltage MN bit digital data into the high voltage MN bit digital data when the low voltage M bit digital data is text. Converts the N-bit digital data into either of the first and second driving power supplies. Therefore, the present invention can reduce current consumption because the two level shifters for converting the low voltage N bit digital data among the low voltage M bit digital data are turned off.

Claims (15)

A shift register array unit for generating a sampling signal; A latch array section for latching low voltage M (where M is a positive integer) bit digital data in accordance with a sampling signal; A level shifter array unit for converting some bits of the low voltage M bit digital data latched according to the text mode signal into the high voltage digital data; A digital-analog conversion array unit for converting M-bit digital data including the high voltage digital data converted by the level shifter array unit into an analog image signal; And An output buffer array unit configured to buffer and output the analog image signal; The text mode signal is in a first logic state when the low voltage M-bit digital data is image data and in a second logic state when the low voltage M-bit digital data is text data; The level shifter array unit converts each of the latched low voltage M bits digital data into high voltage digital data according to the text mode signal of the first logic state, and the latched low voltage M bits according to the text mode signal of the second logic state. A data driving circuit characterized by converting low voltage MN bit digital data except high voltage N (where N is a positive integer smaller than M) bit digital data into high voltage digital data. delete delete The method of claim 1, The level shifter array unit A switching unit for selectively outputting low voltage N (where N is a positive integer less than M) bit digital data among the low voltage M bit digital data supplied from the latch array unit according to the text mode signal; A level shifter for converting low voltage M-N bit digital data excluding the low voltage N bit digital data and low voltage N bit digital data from the switching unit into the high voltage M bit digital data using a driving voltage and a base voltage; And a selection unit for selecting and outputting any one of high voltage N-bit digital data from the level shifter unit and an external power source according to the text mode signal. 5. The method of claim 4, The switching unit includes: Supplying each of the low voltage N-bit digital data to the level shifter according to the text mode signal of the first logic state, And N transistors which respectively block the low voltage N-bit digital data supplied to the level shifter in accordance with the text mode signal of the second logic state. 5. The method of claim 4, The selection unit supplies high voltage N-bit digital data to the digital-analog conversion array unit according to the text mode signal of the first logic state, and supplies an external power source to the digital-analog conversion array according to the text mode signal of the second logic state. And a N multiplexer for supplying negatively. 5. The method of claim 4, And the external power source is any one of the driving voltage and the base voltage. A display panel displaying an image, A gate driving circuit supplying scan pulses to the display panel; The data driving circuit according to any one of claims 1 to 4 and 7; And a timing controller for supplying the low voltage M-bit digital data to the data driving circuit and controlling the gate and the data driving circuit, respectively. A method of displaying an image by supplying an analog image signal to a display panel, Supplying an analog image signal to the display panel A first step of generating a sampling signal; Latching a low voltage M (where M is a positive integer) bit digital data in accordance with the sampling signal; Converting some bits of the low voltage M bit digital data latched in accordance with the text mode signal into high voltage digital data; A fourth step of converting M-bit digital data including the converted high voltage digital data into an analog image signal; And A fifth step of buffering and outputting the analog image signal; The text mode signal is in a first logic state when the low voltage M-bit digital data is image data and in a second logic state when the low voltage M-bit digital data is text data; The third step converts each of the latched low voltage M bit digital data into high voltage digital data according to the text mode signal of the first logic state, and the latched low voltage M bit according to the text mode signal of the second logic state. And converting the low voltage MN bit digital data except the low voltage N (where N is a positive integer smaller than M) bit digital data into high voltage digital data. delete delete The method of claim 9, The third step is Step 3-1 of selectively outputting low voltage N (where N is a positive integer less than M) bit digital data among the latched low voltage M bit digital data according to the text mode signal; 3-2 step of converting the low voltage M-N bit digital data and the low voltage N bit digital data except the low voltage N bit digital data into the high voltage M bit digital data using a driving voltage and a base voltage; And a step 3-3 of selecting and outputting any one of the high voltage N-bit digital data and an external power source according to the text mode signal. 13. The method of claim 12, The step 3-1 selects and outputs each of the low voltage N-bit digital data according to the text mode signal of the first logic state, and supplies to the step 3-2 according to the text mode signal of the second logic state. And driving the low voltage N-bit digital data, respectively. 13. The method of claim 12, In step 3-3, high voltage N-bit digital data is selected and supplied to the fourth step according to the text mode signal of the first logic state, and external power is selected according to the text mode signal of the second logic state. And driving in the fourth step. 13. The method of claim 12, And the external power source is any one of the driving voltage and the base voltage.

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