JP3782418B2 - Display device drive circuit and liquid crystal display device - Google Patents

Description

  The present invention relates to a drive circuit for a display device and a liquid crystal display device. More specifically, the present invention relates to a display device driving circuit and a liquid crystal display device that provide a high-quality image display with a simple configuration and that can extremely easily change display gradation.

  Among flat-panel display devices used for personal computers, flat-screen television receivers, information equipment terminals (PDAs), and the like, there are those composed of a plurality of pixels having a capacitive load. One example is a liquid crystal display device.

  For example, a so-called “active matrix type liquid crystal display device” in which a pixel switching element such as a thin film transistor (TFT) or a thin film diode (TFD) is provided for each display pixel has a clear image quality and a CRT. It has the same or higher density display performance. In particular, a thin film transistor type liquid crystal display device (TFT-LCD) using a TFT as a pixel switching element has been actively put into practical use.

  Usually, amorphous silicon or polycrystalline silicon is used for the semiconductor active layer (channel, source and drain regions) of the TFT. In recent years, a “driving circuit built-in type” TFT-LCD in which a scanning line driving circuit and a video signal line driving circuit are integrally formed on a transparent insulating substrate simultaneously with a pixel TFT has been actively developed. According to this configuration, the effective screen area of the transparent insulating substrate of the liquid crystal display device can be expanded and the manufacturing cost can be reduced.

  By the way, in such a TFT-LCD with a built-in drive circuit, there is a digital / analog conversion circuit (hereinafter abbreviated as “DAC”) for converting a digital signal inputted from the outside as a video signal into an analog signal. It is provided on the pixel substrate.

  However, in the conventional TFT-LCD with a built-in driving circuit, if the number of bits of the digital input signal is increased in order to increase the resolution of the display image, the scale of the DAC increases and the effective display area of the screen is narrowed. There was a problem that. Hereinafter, this problem will be described with reference to the drawings.

  FIG. 53 is a conceptual diagram showing a configuration of a capacitive array type DAC used in a conventional liquid crystal display device. The DAC illustrated in FIG. 1 is a so-called parallel input type, and includes a switch control circuit 41, a reference voltage source 42, a switch array 43, a capacitor array 44, a reset switch 45, and a buffer amplifier 46.

  In the example shown in the figure, 6-bit digital data (B6, B5,... B1) is input in parallel as a video signal.

  The capacitor array 44 is provided with one more capacitor than the number of bits of digital data. The capacitance values of these capacitors are weighted to six types from C to C / 32 corresponding to the binary. In addition, one end of these capacitors is connected in common and is connected to the video signal line via the amplifier 46. Further, the other end of each capacitor is selectively connected to the reference voltage Vs or the ground potential by each MOS switch of the switch array 43.

  Each switch of the switch array 43 is directly controlled by input binary data that matches the capacitance weighting order of each capacitor.

In the example shown in FIG. 53, 6-bit conversion is possible. That is, when parallel data (B6, B5,... B1) is input, the output voltage Vout is expressed by the following equation.

  However, this DAC requires (n + 1) capacitors to convert n-bit digital data. Therefore, in order to display a high-definition image with a high display gradation by increasing the number of bits, there is a problem that the circuit scale inevitably increases. In the liquid crystal display device with a built-in drive circuit, when the circuit scale of the DAC increases, it becomes difficult to ensure an effective pixel area, and the display device becomes large and heavy.

  On the other hand, in the DAC of FIG. 53, the capacitance of each capacitor in the capacitance array 44 needs to be weighted binary, so that the accuracy of the capacitance value must be more accurately guaranteed as the bit teaching increases. Accordingly, the margin for designing and manufacturing is strict and the yield tends to decrease.

  Further, the conventional DAC as shown in FIG. 53 has a problem that the number of bits of digital data that can be converted is fixed. That is, the gradation of the video signal that can be handled is fixed to a constant value by the circuit configuration of the DAC, and cannot be changed afterwards. Then, for example, in a personal computer, there arises a problem that an operation for switching the display mode according to the display content becomes difficult.

  For this reason, for example, Japanese Patent Application Laid-Open No. 7-72822 describes the use of a serial DAC composed of two capacitive elements. However, with this configuration, digital / analog conversion and analog signal input to the capacitive element or digital signal output from the capacitive element must be performed in different periods, so there is a limit in terms of speeding up data processing. there were.

  The present invention has been made based on recognition of the problems described above. That is, an object of the present invention is to provide a display device driving circuit and a liquid crystal display device which can display a high-quality image with a small circuit scale and can freely change the display gradation.

  To achieve the above object, a reference voltage selection circuit that exclusively selects and outputs one of a plurality of reference voltages according to each bit signal of a plurality of bits of serial data input in time series, and the reference voltage selection A first capacitive element connected to a circuit and holding a reference voltage output from the reference voltage selection circuit, and connected to the first capacitive element via a connection circuit, the connection circuit being the reference voltage selection circuit By displaying a short circuit at a timing before each bit signal is input to the second capacitor element, a second capacitor element that holds charges distributed from the first capacitor element and a voltage held in the second capacitor element are displayed. The basic configuration is that an output line for outputting a signal is provided.

  That is, the display device drive circuit according to the present invention is a display device drive circuit that inputs digital data, converts the digital data into an analog video signal, and outputs the analog video signal. When a bit is input and the value of the bit is “1”, the charging voltage of the first capacitor is the first voltage, and when the value of the bit is “0”, the first A selection circuit that sets a charge voltage of the capacitor to a second voltage different from the first voltage, a second capacitor, the first capacitor, and the second capacitor are connected to charge charge of both. A connection circuit that redistributes both charging voltages at the same voltage, and operates the selection circuit and the connection circuit in this order for each bit from the least significant bit to the most significant bit of the digital data. The first capacity or the second capacity obtained by Outputting a charging voltage of the capacitor as the analog video signal.

  On the premise of the above basic configuration, the drive circuit of the first display device of the present invention is a drive circuit of a display device including a digital-analog conversion circuit that inputs digital data and outputs an analog video signal, The digital-analog conversion circuit includes a reference voltage selection circuit that exclusively selects and outputs one of a plurality of reference voltages according to each bit signal of a plurality of bit data input in time series, and the reference voltage selection An input side capacitive element group consisting of a plurality of capacitive elements connected to a circuit and holding a reference voltage output from the reference voltage selection circuit, and connected to each capacitive element of the input side capacitive element group via a connection circuit And by short-circuiting the connection circuit at a predetermined timing, the capacitors in the input-side capacitive element group are selectively connected in order to connect the capacitors in the input-side capacitive element group. Has an output side capacitor element for holding the electric charges to be dispensed from the device, the input capacitance-parallel configuration with the voltage held in the output-side capacitive element and outputs an analog video signal.

  The drive circuit of the second display device of the present invention is a drive circuit of a display device provided with a digital-analog conversion circuit that inputs digital data and outputs an analog video signal, and the digital-analog conversion circuit Is connected to a reference voltage selection circuit that exclusively selects and outputs one of a plurality of reference voltages according to each bit signal of a plurality of bit data input in time series, and the reference voltage selection circuit. An input side capacitive element that holds a reference voltage output from a reference voltage selection circuit, and is connected to the input side capacitive element via a connection circuit, and the input side capacitive element is short-circuited at a predetermined timing. And an output-side capacitive element group comprising a plurality of capacitive elements that hold a charge distributed from the input-side capacitive element, and have an output capacitance parallel type configuration And outputting a voltage held in each capacitor element in the output side capacitor element group as selective analog video signal.

  The third display device drive circuit of the present invention is a display device drive circuit including a digital-analog conversion circuit that inputs digital data and outputs an analog video signal, the digital-analog conversion circuit. Is connected to a reference voltage selection circuit that exclusively selects and outputs one of a plurality of reference voltages according to each bit signal of a plurality of bit data input in time series, and the reference voltage selection circuit. An input side capacitive element group composed of a plurality of capacitive elements that hold a reference voltage output from a reference voltage selection circuit, and connected to each capacitive element of the input side capacitive element group via a connection circuit, By short-circuiting at a predetermined timing, the capacitive elements in the input-side capacitive element group are selectively connected in sequence, and the capacitive elements in the input-side capacitive element group are selectively connected in sequence. And an output-side capacitive element group comprising a plurality of capacitive elements that hold a charge distributed from each capacitive element in the input-side capacitive element group, and an input / output capacitance parallel type configuration, A voltage held in each capacitive element in the output side capacitive element group is selectively output as an analog video signal.

  The first to third drive circuits described above further include a shielding circuit connected between the reference voltage selection circuit and the input side capacitive element, and the input side capacitive element and the output side capacitance are connected by the connection circuit. By blocking the reference voltage selection circuit and the input side capacitive element by the shielding circuit before the element is short-circuited, it is possible to prevent the backflow of charges from the input side capacitive element to the reference voltage selection circuit. be able to.

  Further, if the input-side capacitive element and the output-side capacitive element have substantially the same capacitance value, charge redistribution can be performed evenly.

  On the other hand, the drive circuit of the fourth display device of the present invention includes a plurality of signal lines and scanning lines arranged orthogonal to each other, and pixel switching elements provided at intersections of the signal lines and the scanning lines, respectively. A display device driving circuit for performing gray scale display of 2 to the power of m based on m-bit data (m is a plurality), a data distribution circuit to which the m-bit data is supplied, and the m-bit data Are sequentially stored and output at a predetermined timing; the output from the data latch circuit is stored; the gamma correction circuit that outputs at a predetermined timing; and the output from the gamma correction circuit is stored; A digital / analog converter circuit used in the drive circuits of the first to third display devices that output at the timing of Characterized by comprising a and.

  On the other hand, a liquid crystal display device of the present invention includes any one of the above-described drive circuits of the display device and a liquid crystal controlled by the pixel switching element, and an operating threshold value of the liquid crystal is about 2.5 volts. It is characterized by being.

  Alternatively, the liquid crystal display device of the present invention includes any one of the drive circuits of the display device described above and a liquid crystal controlled by the pixel switching element, and the operation threshold value of the liquid crystal is about 1.5 volts. It is characterized by being.

  Alternatively, the liquid crystal display device of the present invention is a transmissive liquid crystal display device including any one of the drive circuits of the display device described above and a light source provided on the back side when viewed from the image observation surface. Features.

  Alternatively, the liquid crystal display device of the present invention includes any one of the drive circuits of the display device described above and a reflector provided on the back side as viewed from the image observation surface, and external light incident from the image observation surface side. It is a reflective liquid crystal display device that displays an image by reflecting the light by the reflector.

  Alternatively, the liquid crystal display device of the present invention includes a drive circuit for any of the display devices described above, a light source provided on the back side as viewed from the image observation surface, and a reflector provided on the back side as viewed from the image observation surface. And displaying the image by transmitting the light emitted from the light source or reflecting the external light incident from the image observation surface side by the reflector.

  Alternatively, the liquid crystal display device of the present invention includes a drive circuit for any one of the display devices described above and a pixel switching element provided for each display pixel, and the drive circuit and the pixel switching element are the same. The semiconductor device includes a semiconductor layer of the same layer provided on the substrate and deposited on the substrate.

  The present invention is implemented in the form described above, and has the effects described below.

  First, according to the present invention, a serially input digital video signal can be reliably and easily converted into an analog signal. Moreover, according to the present invention, the circuit configuration of the DAC is extremely simple, and the circuit area can be greatly reduced as compared with the conventional case. Such an effect of reducing the circuit scale becomes higher according to the number of bits of the digital data, and the effect can be obtained more remarkably as the display image becomes higher in image quality.

  That is, compared with a general n-bit parallel input DAC, the circuit scale of the DAC of the present invention is approximately 1 / n, and the effect of reducing the circuit scale can be obtained as the number of bits increases. This is particularly advantageous in a polysilicon TFT liquid crystal display device in which a drive circuit is integrated in a panel. In order to improve the image quality of the display image, it is necessary to increase the display gradation, that is, the number of bits of the video signal. However, according to the present invention, the panel size and the image quality can be improved without increasing the circuit scale. And both.

  Furthermore, according to the present invention, it is possible to obtain an effect that digital data having a different number of bits can be converted into an analog video signal without changing the circuit. That is, according to the present invention, the digital data can be converted into an analog signal without depending on the number of bits by repeating the above-described operation for each bit of the digital data input serially.

  This effect of the present invention is particularly advantageous when applied to a computer display device or the like. That is, in a computer, it is often necessary to switch the image display mode in accordance with the application or software. At that time, it is desirable to switch the display gradation, that is, the number of gradation bits together with the display resolution. According to the present invention, even in such a case, analog conversion can be performed using the same DAC.

  Furthermore, according to the present invention, digital data can be input at high speed in parallel by providing a plurality of primary capacitors of the DAC. Also, by providing a plurality of DAC secondary side capacitors, DA conversion for the next signal line and analog potential writing to the previous signal line can be executed in parallel. As a result, high-speed operation is possible, and a predetermined analog potential can be reliably written even when the parasitic capacitance of a signal line is large in a high-definition display device or the like.

  Furthermore, according to the present invention, an input circuit is input to the gate of the TFT as an output circuit (amplifier circuit) for writing an analog potential from the DAC to the signal line. A stable sampling output that is not affected can be ensured.

  Further, according to the present invention, the output circuit is controlled so that the voltage of the signal line is increased when the voltage of the signal line is lower than the voltage of the input signal, and the signal line is compared with the voltage of the input signal. Since the control is performed so that the voltage of the signal line is lowered when the voltage is high, the voltage of the signal line can be made equal to the voltage of the input signal.

  Further, in such an output circuit, before controlling the voltage of the signal line, by setting the voltage of the input terminal of each inverter constituting the output circuit to the respective threshold voltage, the operation of these inverters is controlled. Even if the threshold voltage varies, it is possible to prevent the influence from affecting the voltage of the signal line.

  As described above in detail, according to the present invention, digital data having a different number of bits can be converted into an analog video signal and reliably written to a signal line with a significantly simpler circuit configuration than in the past. The above benefits are enormous.

  According to the present invention, a part of the three or more capacitors is charged to a potential corresponding to the bit value of the digital data, and then the charge charge is redistributed with the remaining capacitors. By repeating the operation, an analog voltage corresponding to the digital data can be formed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic diagram showing a digital-to-analog converter circuit (DAC) used in a video signal driving circuit made as a prototype in the course of reaching the present invention.

  FIG. 2 is a timing chart showing the operation waveform.

  Furthermore, FIG. 3 is a conceptual diagram illustrating a schematic configuration of a main part of a liquid crystal display device equipped with such a DAC.

  First, the configuration of the liquid crystal display device of the present invention will be described with reference to FIG. The liquid crystal display device illustrated in the figure is of a type called “line sequential method”, and operates so as to simultaneously write video signals to all video signal lines. That is, the video signal drive circuit VD and the scanning line drive circuit SD are provided on the same substrate adjacent to the image display unit 20. Further, the switching elements constituting them are made of the same semiconductor layer such as polysilicon formed by the same deposition process.

  The image display unit 20 is wired with a double textbook video signal line 27 and a double textbook scanning line 28 orthogonal thereto, and a pixel TFT 29 is provided at the intersection of these lines. A liquid crystal capacitor Clc and an auxiliary capacitor Cs are connected to the drain electrode of the TFT 29 to form a display pixel.

  The scanning line driving circuit SD is composed of, for example, a shift register (not shown) and a scanning line driving buffer, and each buffer output is supplied to each scanning line 28. Based on the scanning line signal supplied to each scanning line 28 in this way, the TFT 29 of the corresponding pixel is on / off controlled.

  The video signal drive circuit VD includes a shift register 21, a sampling switch 24, a DAC 10, and a buffer amplifier (amplifier circuit) 50. A clock signal (CLK-A) and a trigger signal are input to the shift register 21. The sampling switch 24 is controlled by the output from the shift register 21 and the serial data sampling clock. The sampling switch 24 outputs a sample signal (Sample), its inverted signal (/ Sample), and a control signal (Control).

  Based on these signals, the DAC 10 converts a serially input digital video signal into an analog signal and outputs the analog signal. The output analog video signal is supplied to each video signal line 27 via the write control switch AS and the buffer amplifier 50, and is stored in the liquid crystal capacitor Clc and the auxiliary capacitor Cs via the corresponding pixel TFT 29. A predetermined image is displayed.

  Next, the configuration of the serial DAC manufactured in the process leading to the present invention will be described with reference to FIG.

  First, a switch selection circuit 11 is provided at the input stage. The switch selection circuit 11 is composed of NOR1, NOR2, NOT1, and NOT2.

  In the subsequent stage of the switch selection circuit 11, an N channel transistor M1, a P channel transistor M2, a capacitor C1, an N channel transistor M4, a P channel transistor M5, a capacitor C2, and an N channel transistor M3 are provided.

  The switch selection circuit 11 selects either the transistor M1 or the transistor M2 according to the input data signal (Data) and the control signal (Control). More specifically, when the control signal is "L" (low), the transistors M1 and M2 can be exclusively selected by the data signal, and when the data signal is "0", the transistor M1 is selected and the data signal When "1", the transistor M2 is selected.

  On the other hand, when the control signal is “H” (high), neither of the transistors M1 and M2 is selected.

  The transistor M1 is connected to the ground potential and discharges the capacitor C1 in accordance with a signal from the selection circuit 11. The transistor M2 is connected to the reference voltage Vs, and charges the capacitor C1 in accordance with a signal from the selection circuit 11.

  The transistors M4 and M5 form a transfer gate that inputs a sample signal (Sample, / Sample) and controls the electrical connection state between the capacitors C1 and C2. That is, when the sample signal (Sample) is “L”, the transfer gate is non-conductive, and when it is “H”, it is conductive. On the other hand, the transistor M3 is controlled by a reset signal (Reset) and discharges the charge of the capacitor C2.

Next, the operation of the DAC of FIG. 1 will be described with reference to FIG.
Here, a case where (1001), which is 4-bit digital data, is input as a serially input digital video signal is illustrated as an example. That is, a case where digital signals corresponding to “1”, “0”, “0”, “1” are sequentially input as the data signal (Data) will be described. Here, it is assumed that the capacitance values of the capacitors C1 and C2 in FIG. 1 are equal.

  First, at time t0 to t2 before inputting the data signal, the control signal (Control) is set to “H”, and the transistors M1 and M2 are both turned off. At the same time, the sample signal (Sample) is set to “L”, and the transistors M4 and M5 constituting the transfer gate are turned off. As a result, point B, which is one end of the capacitor C1, is opened.

  Further, at time t1 to t2, the reset signal (Reset) is set to “H”, and the transistor M3 is turned on, whereby the point A which is one end of the capacitor C2 is grounded, and the potential Va at the point A is 0. (Bolts).

  The above operation corresponds to the reset operation before inputting the serial video signal.

  Next, serial video signals are sequentially input from time t2 to start the DA conversion operation.

  First, at time t2 to t4, “1” that is the least significant bit (LSB) is input. Correspondingly, first, at time t2 to t3, the control signal is set to “L” to select the transistors M1 and M2, and the sample signal is set to “L” to turn off the transfer gates M4 and M5. As conduction, points A and B are electrically cut off. Here, since the input data signal is “1”, the transistor M1 becomes non-conductive, the M2 becomes conductive, and the potential Vb at the point B is set to Vs (volts). That is, the capacitor C1 is charged to a voltage of Vs (volt). At this time, the potential Va at the point A is maintained at 0 (volt).

  Next, at time t3 to t4, the control signal is set to “H” to turn off the transistors M1 and M2, and the sample signal is set to “H” to set the transfer gates M4 and M5 to the conductive state. The point and the point B are electrically connected, and the potential at the point B is not affected by the input data. Then, the redistribution of accumulated charges occurs between the capacitors C1 and C2.

That is, at time t3, the potential Vb at point B is set to Vs (volts) and the potential Va at point A is set to 0 (volts). Therefore, assuming that the capacitance values of capacitors C1 and C2 are equal, time t4 In

Va = Vb = 1/2 × “1” × Vs = Vs / 2 (2)

It becomes. That is, the charging voltages of the capacitors C1 and C2 are both Vs / 2 (volts).

  Next, at time t4 to t6, “0” that is the next bit of the video signal is input. In response to this, first, at time t4 to t5, control signals (control signal, sample signal, and reset signal) in the same state as at time t2 to t3 are input. That is, the transistors M1 and M2 can be selected, and the capacitors C1 and C2 are electrically cut off. Here, since “0” of the second bit is input as the data signal, the transistor M1 becomes conductive and the transistor M2 becomes non-conductive, and the potential at the point A becomes Vb = 0 (volts). Va is maintained at the potential Vs / 2 (volt) at time t4. That is, the charging voltage of the capacitor C1 is 0 (volt), and the charging voltage of the capacitor C2 is maintained at Vs / 2 (volt).

At times t5 to t6, the control signal in the same state as that at times t3 to t4 is input, so that the stored charge is redistributed between the capacitors C1 and C2. As a result, at time t6,

Va = Vb
= 1/2 * ("0" * Vs + 1/2 * "1" * Vs) = Vs / 4 (3)

It becomes.

Thereafter, “0” that is the third bit of the video signal is input from time t6 to t8, and “1” that is the most significant bit (MSB) is input from time t8 to t10. The series of operations described above is repeated in response to the input of these bit data. As a result, at time t10, the potential Va at point A and the potential Vb at point B are

Va = Vb
= {1/2 × “1” + (1/2) ² × “0” + (1/2) ³ × “0” + (1/2) ⁴ × “1”} × Vs
= (9/16) Vs (4)

Thus, an analog potential corresponding to the input digital data (1001) is obtained.

  After time t10, the control signal (Control) is set to “H”, and the sample signal (Sample) and the reset signal (Reset) are set to “L”. As a result, the capacitors C1 and C2 are electrically cut off, and Va can be held such that the transistors M1 and M2 are not selected by the input digital data. In this way, the analog potential Va corresponding to the input digital data is obtained and applied to the corresponding video signal line 27.

  As described above, according to the serial DAC illustrated in FIG. 1, the digital video signal input serially can be converted into an analog signal reliably and easily. Moreover, the circuit configuration of the DAC is extremely simple, and the circuit area can be greatly reduced as compared with the conventional case. That is, the area of the driving circuit can be reduced when the pixel TFT and the switching element of the driving circuit are formed using the same semiconductor layer such as polysilicon deposited on the same substrate.

  Such an effect of reducing the circuit scale becomes higher according to the number of bits of the digital data, and the effect can be obtained more remarkably as the display image becomes higher in image quality. For example, as compared with the conventional 6-bit parallel input DAC illustrated in FIG. 53, the circuit scale of the serial DAC of FIG. 1 can be extremely reduced to about 1/6. That is, the area occupied by the circuit can be reduced to about 1/6 of the conventional one.

  Compared with a general n-bit parallel input DAC, the circuit scale of the serial DAC of FIG. 1 is approximately 1 / n, and the effect of reducing the circuit scale can be obtained as the number of bits increases. This is particularly advantageous in a polysilicon TFT liquid crystal display device in which a drive circuit is integrated in a panel. In order to improve the image quality of the display image, it is necessary to increase the display gradation, that is, the number of bits of the video signal. However, according to the serial DAC of FIG. High image quality can be achieved at the same time.

  Further, according to the serial DAC of FIG. 1, it is possible to obtain an effect that digital data having different numbers of bits can be converted into an analog video signal without changing the circuit. That is, by repeating the above-described operation for each bit of digital data input serially, the digital data can be converted into an analog signal without depending on the number of bits.

  These effects produced by the serial DAC of FIG. 1 are particularly advantageous when applied to a computer display device or the like. That is, in a computer, it is often necessary to switch the image display mode in accordance with the application or software. At that time, it is desirable to switch the display gradation, that is, the number of gradation bits together with the display resolution. According to the serial DAC of FIG. 1, even in such a case, analog conversion can be performed using the same DAC.

For example, digital data with a larger number of bits is converted into an analog potential by further dividing the period ts to te for DA conversion as illustrated in FIG. 2 according to the number of bits of input digital data. it can. An analog potential Va obtained when n-bit digital data (Bn, Bn-1,... B1) (where each bit Bk is 0 or 1) is converted by the DAC of FIG. It is expressed by the following formula.

  As described above, according to the serial DAC of FIG. 1, DA conversion can be performed with a smaller number of elements as compared with the conventional DAC. Also, digital data of an arbitrary length can be converted into an analog potential simply by changing the frequency of the control signal during the conversion period without changing the circuit. As a result, a video signal driving circuit capable of high-definition display and having a small number of elements can be realized.

  The serial DAC described above is further conceptually described as follows.

  FIG. 4 is a configuration diagram conceptually showing the configuration of the serial DAC exemplified in FIG. That is, the serial DAC illustrated in FIG. 1 has two capacitors C1 and C2 as a basic configuration. Based on the data signals (data, / data) and the control signal (/ control), a voltage corresponding to the digital signal is serially input to the capacitor C1. On the other hand, the digital signal is converted into an analog voltage by executing charge redistribution between the capacitors C1 and C2 based on the sample signal (sample) in parallel with this. The input voltages V + and V− shown in FIG. 4 correspond to Vs and ground potential in FIG. 1, respectively.

  The present inventor has further improved the serial DAC, and invented a more preferable serial DAC by being mounted on a driving circuit of a display device.

  FIG. 5 is a conceptual diagram showing the basic configuration of the first serial DAC according to the present invention.

  FIG. 6 is a timing chart for explaining the operation of the serial DAC of FIG.

  The serial DAC 10A shown in FIG. 5 is an “output capacitance parallel type” DAC in which one capacitor C1 is provided on the primary side and two capacitors C21 and C22 are provided on the secondary side. By alternately using these two capacitors C21 and C22, DA (digital / analog) conversion processing and writing to the signal line can be continuously performed.

  The operation will be described below with reference to the timing chart of FIG.

  First, the capacitors C21 and C22 are initialized by turning on the reset signal (RST).

  Next, by alternately turning on the control signal (/ control) and the sample signal (sample1), a voltage corresponding to each bit of the digital signal is serially applied to the capacitor C1, and at the same time, a charge is generated between the capacitor C21 and the capacitor C21. Perform reallocation of By this operation, the analog potential corresponding to the digital data is charged in the capacitor C21.

  Next, by alternately turning on the control signal (/ control) and the sample signal (sample2), a voltage corresponding to each bit of the digital signal is serially applied to the capacitor C1, and at the same time, a charge is generated between the capacitor C22 and the capacitor C22. Perform reallocation of By this operation, the analog potential corresponding to the digital data is charged in the capacitor C22.

  At this time, the analog potential can be written from the capacitor C21 to a signal line (not shown) in parallel with the DA conversion process using the capacitor C22. That is, according to the serial DAC shown in FIG. 5, the potential conversion from the other capacitor to the signal line can be performed in parallel while performing the DA conversion process using one of the capacitors C21 and C22. The signal processing time of the drive circuit can be greatly shortened.

  In general, various display devices such as a liquid crystal display device tend to have larger capacity and higher definition, and the parasitic capacitance of the signal line itself also tends to increase. That is, it is necessary to lengthen the time for accurately writing the analog potential to the signal line.

  In response to such a request, according to the configuration of FIG. 5, the DA conversion processing and the potential writing processing to the signal line can be performed in parallel, so that the signal processing time can be shortened and the signal line can be accurately processed. An analog potential can be written to the display, and a high-definition and high-quality image with a high number of gradations can be displayed quickly and accurately.

In the timing chart of FIG. 6, the case where DA conversion is performed on 3-bit digital data is illustrated, but the present invention is not limited to this, and the same processing is performed on digital data having an arbitrary number of bits. be able to.
Further, as will be described in detail later, each of the secondary-side capacitors C21 and C22 of the serial DAC is not necessarily fixed to a specific signal line, and any one of a plurality of signal lines is connected via a changeover switch. Can be switched and connected as needed. According to the results of the inventor's trial production, for example, it is found that about 6 to 30 signal lines can be appropriately connected to the capacitors C21 and C22 via a changeover switch. is doing. In this way, the number of DACs mounted on the drive circuit can be greatly reduced, and the configuration can be reduced in size and simplified.

  Next, the second DAC according to the present invention will be described.

  FIG. 7 is a conceptual diagram showing the basic configuration of the second DAC according to the present invention.

  FIG. 8 is a timing chart for explaining the operation of the DAC of FIG.

  The DAC 10B illustrated in FIG. 7 is an “input capacitance parallel type” DAC in which three capacitors C11 to C13 are provided on the primary side and one capacitor C2 is provided on the secondary side. By providing a plurality of capacitors on the primary side in this way, digital signals can be input in parallel and converted into analog signals serially in the DAC.

  The operation will be described with reference to the timing chart of FIG.

  First, the reset signal (RST) is turned on to initialize the capacitor C2.

  Next, by simultaneously turning on the three control signals (/ control1 to / control3), voltages corresponding to the respective bits of the digital signal are applied in parallel to the capacitors C11 to C13. When the input digital data is 3-bit data, for example, the third bit (least significant bit) data (data1) is stored in the capacitor C11, the second bit data (data2) is stored in the capacitor C12, and 1 bit is stored in the capacitor C13. A voltage corresponding to the data (data3) of the first (most significant bit) is applied.

  Next, by sequentially turning on the sample signals (sample1 to sample3), the charges stored in the capacitors C11 to C13 are redistributed with the capacitor C2. That is, serial analog conversion is performed. By this operation, the analog potential corresponding to the digital data input to the capacitors C11 to C13 is charged in the capacitor C2.

  Thereafter, the analog potential charged in the capacitor C2 is written to a predetermined signal line via an analog switch or output circuit (not shown).

  As described above, according to the DAC shown in FIG. 7, a plurality of capacitors C11 to C13 are provided on the primary side, and digital data can be input in parallel to these. The effect of being able to input to is obtained.

  In the configuration illustrated in FIG. 7, the number of primary-side capacitors is not necessarily the same as the input digital data. For example, DA conversion of 6-bit digital data can be performed using a DAC having three capacitors C11 to C13 as illustrated in FIG. Specifically, first, as the first cycle, data from the 6th bit (least significant bit) to the 4th bit are input to the capacitors C11 to C13, respectively, and serial analog conversion is executed. Next, as the second cycle, data from the third bit to the first bit (most significant bit) may be input to the capacitors C11 to C13, respectively, and serial analog conversion may be executed.

  As can be seen from this specific example, the number of capacities on the primary side is not necessarily equal to the number of bits of the input digital data, but if the number of capacities on the primary side is set to 1 / integer of the number of input bits. Efficient.

On the other hand, digital data having a smaller number of bits than the number of capacities on the primary side can be handled in the same manner. That is, in such a case, a number of capacitors corresponding to the number of bits may be selected and used.

  On the other hand, in the DAC shown in FIG. 7, the secondary-side capacitor C2 does not need to be fixed to a specific signal line, and can be switched and connected to any of a plurality of signal lines at any time via a changeover switch. can do. This is the same as described above with reference to FIG.

  Next, the third DAC according to the present invention will be described.

  FIG. 9 is a conceptual diagram showing the basic configuration of the third DAC according to the present invention.

  FIG. 10 is a timing chart for explaining the operation of the DAC of FIG.

  The DAC 10C illustrated in FIG. 9 includes three capacitors C11 to C13 on the primary side, and two capacitors C21 and C22 on the secondary side. That is, it is an “input / output capacitor parallel type” DAC in which a plurality of capacitors are provided on both the primary side and the secondary side.

  By providing a plurality of capacitors C11 to C13 on the primary side, digital signals can be input in parallel at high speed as described above with reference to FIG. On the other hand, by providing a plurality of capacitors C21 and C22 on the secondary side, the DA conversion process and the writing to the signal line can be processed in parallel as described above with reference to FIG.

  The operation will be described below with reference to the timing chart of FIG.

  First, the capacitors C21 and C22 are initialized by turning on the reset signal (RST).

  Next, by simultaneously turning on the three control signals (/ control1 to / control3), voltages corresponding to the respective bits of the digital signal are applied in parallel to the capacitors C11 to C13. When the input digital data is 3-bit data, for example, the third bit (least significant bit) data (data1) is stored in the capacitor C11, the second bit data (data2) is stored in the capacitor C12, and 1 bit is stored in the capacitor C13. A voltage corresponding to the data (data3) of the first (most significant bit) is applied.

  Next, the secondary side capacitor C21 is selected by turning on the sample signal (sample1). Then, by sequentially turning on the sample signals (sample11 to sample13), the charges accumulated in the capacitors C11 to C13 are redistributed with the capacitor C21. That is, serial analog conversion is performed. By this operation, the analog potential corresponding to the digital data input to the capacitors C11 to C13 is charged in the capacitor C21.

  Next, the secondary side capacitor C22 is selected and the next DA conversion process is executed.

  That is, by simultaneously turning on the three control signals (/ control1 to / control3), voltages corresponding to the bit data (data1 to data3) of the digital signal are applied in parallel to the capacitors C11 to C13.

  Next, the secondary side capacitor C22 is selected by turning on the sample signal (sample2). Then, by sequentially turning on the sample signals (sample11 to sample13), the charges accumulated in the capacitors C11 to C13 are redistributed with the capacitor C22. By this operation, the analog potential corresponding to the digital data input to the capacitors C11 to C13 is charged in the capacitor C22.

  During this DA conversion process, the analog potential charged in the capacitor C21 can be written to a predetermined signal line via an analog switch or output circuit (not shown).

  As described above, according to the DAC shown in FIG. 9, a plurality of capacitors C11 to C13 are provided on the primary side, and digital data can be input in parallel to these. The effect of being able to input to is obtained.

  Furthermore, by providing a plurality of capacitors C21 and C22 on the secondary side, DA conversion processing and writing to the signal line can be processed simultaneously.

  Therefore, according to the DAC illustrated in FIG. 9, the effects described above with reference to FIGS. 5 to 8 can be obtained at the same time.

The digital-analog converter circuit (DAC) used in the drive circuit of the present invention has been described with reference to specific examples. However, the DAC of the present invention is not limited to these specific examples. For example, in FIGS. 1 to 9, the case where the primary side capacitance C1 (or C11 or the like) and the secondary side capacitance C2 (or C21 or the like) have the same capacitance value has been described as an example. May not be the same. When the primary-side capacitance value and the secondary-side capacitance value are different, a predetermined “gain” is obtained. Specifically, for example, when the capacitance value of the primary side capacitance C1 is C ₁ and the capacitance value of the secondary side capacitance C2 is C ₂ , the coefficient on the right side in the equations (2) to (5) A coefficient “C ₁ / (C ₁ + C ₂ )” may be applied instead of “1/2”. For example, when the capacitance C2 has a capacitance value three times that of the capacitance C1, the coefficient is “1/4”. Further, when the capacitance C1 has a capacitance value three times that of the capacitance C2, this coefficient is “3/4”.

  Therefore, the video signal voltage range can be adjusted to the optimum range with respect to the reference potential Vs by appropriately selecting the capacitance values of the capacitors C1 and C2 so as to obtain a predetermined gain.

  In the specific example shown in FIG. 1 or FIG. 5, the case where serial data is input to the DAC has been described. However, the present invention is not limited to this, and digital data input in parallel can be converted. For this purpose, for example, a means for accumulating digital data input in parallel and taking out and supplying data of each bit sequentially from the least significant bit may be provided separately. In this way, digital data input in parallel can be similarly converted to analog by repeating the operation described above with reference to FIG. In this case, although the circuit scale is slightly increased, the effect of the present invention that it is possible to deal with arbitrary length of digital data can be similarly obtained.

  Further, a second reference potential may be provided instead of the ground potential for discharging the capacitors C1 and C2. In this case, the lower limit voltage of the obtained analog video signal is the same voltage as the second reference potential.

  In the specific examples illustrated in FIGS. 1 to 9, the configuration in which the charging voltage of the second capacitor C2 is output as an analog video signal is shown, but the present invention is not limited to this. That is, in the configuration of FIG. 1 or FIG. 5, the charging voltages of the first capacitor C1 and the second capacitor C2 are the same when a series of charging / charge redistribution operations up to the most significant bit is completed. Since it is a value, a selection circuit that outputs the charging voltage of the first capacitor C1 to the outside as an analog video signal instead of the second capacitor C2 may be provided.

  Furthermore, in a state where the first capacitor C1 and the second capacitor C2 are short-circuited, the charging voltage of the output capacitor C1 + C2 may be output to the outside as an analog video signal. In this way, it is possible to obtain an effect that the fluctuation of the DAC output voltage due to the parasitic capacitance of the external circuit can be halved.

  Next, a modification of the serial DAC suitable for use in the drive circuit of the present invention will be described.

  FIG. 11 is a schematic circuit diagram in which the serial DAC illustrated in FIGS. 1 to 9 is further simplified and modified. That is, the serial DAC has switches data (corresponding to the transistor M2 in FIG. 1) and / data (corresponding to the transistor M1 in FIG. 1) and a cutoff switch for switching the two levels of voltages Vref and Vcom in a complementary manner. / SW1, capacitors C1 and C2, a connection switch 16 provided therebetween, and a reset switch 18.

  In the modified example of FIG. 11, the reverse flow of the accumulated charge from the capacitor C1 can be surely prevented by providing the cutoff switch / SW1.

  Furthermore, in the DAC circuits of FIGS. 1 to 11, it is desirable to form the reset switch 18 so that the amount of leakage when the reset switch 18 is off is smaller than that of other switches. This is to prevent leakage of accumulated charge in the capacitor C2. For this purpose, it is advantageous to form a double gate structure by forming the reset switch 18 with a long gate length L and a short gate width W.

  Similarly, in order to prevent fluctuation of the accumulated charge in the capacitor C1, it is desirable that the cutoff switch / SW1 also has a small amount of leakage when it is off. For this purpose, it is advantageous that the gate length L of the transistor constituting the cutoff switch / SW1 is long and the gate width W is short to form a double gate structure.

  In connection with this, it is desirable to set the ON period of the cutoff switch / SW1 longer than the ON period of the connection switch 16. This is because when the cut-off switch / SW1 is composed of a transistor with a small leak amount, it is necessary to lengthen the voltage writing time.

  On the other hand, in the display device illustrated in FIG. 3, the TFT 29 constituting the pixel switching element often uses a −2 volt and 12 volt power supply. Therefore, each switch of the DAC illustrated in FIGS. 1 to 11 can simplify the power supply configuration by using -2 volt and 12 volt power supplies and making the off condition equivalent to that of the pixel TFT.

  FIG. 12 is a schematic circuit diagram showing a second modification of the DAC suitable for use in the drive circuit of the present invention. That is, in the circuit shown in the figure, the switch SA is provided in series with the cutoff switch / SW1. The switch SA is operated based on the NAND logic of the cutoff switch / SW1 and the connection switch 16. That is, when both the cutoff switch / SW1 and the connection switch 16 are half open, the switch SA is operated to be turned off. By providing such a switch SA, it is possible to reliably prevent erroneous voltage writing to the capacitor C1 due to a “deviation” between the operation timings of the switch / SW1 and the switch 16, and to improve the accuracy of the DAC conversion operation.

  FIG. 13 is a schematic circuit diagram showing a third modified example of the DAC suitable for use in the drive circuit of the present invention. That is, in the circuit shown in the figure, two capacitors, a capacitor C2A and a capacitor C2B, are provided in parallel as secondary-side capacitors. Each of these two capacitors is complementarily connected to the primary side capacitor C1 via the connection switches 16A and 16B. That is, one DA conversion process is performed between the capacitors C1 and C2A, and the next DA conversion process is performed between the capacitors C1 and C2B. Although omitted in FIG. 13, it is desirable to provide a reset switch for each of the secondary side capacitors C2A and C2B.

  As described above, two capacitors C2A and C2B are provided as the secondary side capacitors, and are switched for each DA conversion process, so that analog data is output from one of the secondary side capacitors to the signal output circuit 50. Also, the next DA conversion process can be disclosed using the other secondary side capacitor, and the data processing can be speeded up.

  As another merit, the effect of “error diffusion” can be obtained when there is “variation” in the capacitance ratio C2 / C1 between the primary side capacitance and the secondary side capacitance between adjacent DACs.

  FIG. 14 is a conceptual diagram for explaining the effect of “error diffusion”. That is, in the example shown in FIG. 9A, the DAC corresponding to the signal line N has the secondary side capacitor C2, and the DAC corresponding to the adjacent signal line (N + 1) has the secondary side capacitor C2 ′. Have. Further, these DACs share a capacitor C2B as a second secondary side capacitor. As shown on the right side of the figure, the DAC of the signal line N uses the capacitor C2 in the first, third, and fourth frames, and uses the capacitor C2B in the second frame. On the other hand, the DAC of the signal line (N + 1) uses the capacitor C2 'in the first, second, and fourth frames, and uses the capacitor C2B in the third frame.

  In this way, even when there is a capacitance “error” between the capacitances C2 and C2 ′, by sharing the capacitance C2B, this “error” can be diffused in time and made inconspicuous. it can.

  Furthermore, in the present invention, as illustrated in FIG. 14B, it is possible to use adjacent secondary DACs without newly adding a secondary side capacitor. In other words, in the specific example shown in the figure, the DAC corresponding to the signal line N has the secondary side capacitance C2, and the DAC corresponding to the adjacent signal line (N + 1) has the secondary side capacitance C2 '. And each DAC exchanges the secondary side capacity | capacitance for every flame | frame, and performs DA conversion process. Even in this case, the “error” of the capacitance between the capacitances C2 and C2 ′ can be diffused with time to make it less noticeable.

  The serial DAC suitable for use in the drive circuit of the present invention has been described in detail above.

  Next, a signal output circuit (amplifier circuit) that outputs the video signal output from the DAC to the video signal line in the drive circuit of the present invention will be described in detail.

  As described above with reference to FIG. 3, the video signal line driving circuit according to the present invention has a configuration in which the DACs 10 </ b> A to 10 </ b> C, the analog switch AS, and the video signal output circuit 50 are connected in series for each video signal line 27.

  FIG. 15 is a schematic diagram showing a main part of a video signal line driving circuit according to one embodiment of the present invention. That is, this figure is a circuit diagram showing a state in which the DAC, the analog switch AS, and the video signal output circuit 50A are connected to one of the video signal lines 27, and is equivalent to that described above with reference to FIGS. These elements are denoted by the same reference numerals, and detailed description thereof is omitted.

  The signal output circuit 50A includes switches S1 to S4, a capacitor C3, NOT3, NOT4, and NOT4, and transistors M4 and M5. Transistors M4 and M5 are selectively selected by NOT3-5. By using such an output circuit 50, it is possible to detect the inverting amplifier operating point voltage for controlling the switching operation and reduce the influence of variations in TFT characteristics, and provide a good image.

  FIG. 16 is a timing chart showing operation waveforms in the circuit of FIG. The operation of the signal output circuit 50A will be described with reference to FIG.

  First, during a period from time t1 to t10, serial digital-analog (DA) conversion by the DACs 10A to 10C is executed. Since this conversion operation has been described in detail with reference to FIGS. 1 to 10, a detailed description thereof will be omitted. Then, when the DA conversion ends at t10, the operation of the signal line output circuit starts.

  First, at time t11, the control signal ENABLE becomes “H”, so that the analog switch AS is turned on. Then, the point A and the point C are electrically connected. Here, at time t11-t12, since the control signal CLK is “L”, the switch S2 and the switch S3 are turned on, and the switches S1 and S4 are turned off. As a result, the potential Vd at one end D of the capacitance C3 becomes the video signal line potential Vsig, and the potential Ve at the other end E is short-circuited at the input / output of the inverter NOT3 by S3. It becomes. Here, the operating point voltage of NOT3 varies depending on the TFT characteristics constituting the circuit, and therefore varies depending on the video signal line driving circuit.

Next, at time t12 to t13, when CLK becomes “H”, the switches S1 and S4 are turned on, and the switches S2 and S3 are turned off. Therefore, the potential at the point D is Vd = Vc = Va, which is equal to the output potential of the DACs 10A to 10C. On the other hand, the potential Ve at the point E is Ve = (Va−Vsig) + Vop because C3 holds the potential when the CLK is in the “L” state. Therefore, the voltage Vf at point F is
(1) When Va> Vsig, Vf = 0
(2) When Va <Vsig, Vf = VDD
It becomes.

  In this specific example, Va> Vsig at time t11, so that the potential Vf at point F is zero. As a result, the P-channel transistor M5 becomes conductive, and the current Ip is supplied to the video signal line 27. At this time, the voltage increase ΔVp of the video signal line 27 during the period T is expressed as ΔVp = 1p × T / Csig, where Csig is the signal line capacitance.

  When the above operation is performed a plurality of times and at time t26, Va <Vsig, so that the N-channel transistor M4 becomes conductive, and the current In flows from the video signal line 27 to GND. At this time, the potential ΔVn that changes during the period T is expressed as ΔVn = In × T / Csig.

  After time t26, Vsig continues to change in the range of ΔVp and ΔVn in the vicinity of Va during the video output period. The error voltage Verr of the finally formed video signal line potential Vsig is Verr = | ΔVp−ΔVn | / T. Here, ΔVp depends on the characteristics of the transistor M5, and ΔVn depends on the characteristics of the transistor M4, but by setting the frequency of CLK sufficiently high, Verr can be reduced to a negligible level.

  As described above, the signal output unit of the video signal line driving circuit according to the present invention causes the operating point voltage variation of the inverter used to compare the output voltage of the DACs 10A to 10C and the voltage of the video signal line 27 to the capacitance C3. Can be canceled. Furthermore, by setting the frequency of the control signal CLK sufficiently high, it is possible to reduce variations in characteristics of TFTs that directly supply current to the video signal line 27. As a result, a uniform and good image with little display unevenness can be provided.

  16 illustrates the case where the time steps t1 to t10 in the DA conversion operation and the time steps t11 to t27 in the signal output operation are substantially the same, the present invention is not limited to this, and the DA The time step in the conversion operation and the time step in the signal output operation may be different from each other.

  Next, a video signal output circuit 50 that is more suitable for use in the video signal drive circuit of the present invention will be described.

  FIG. 17 is a circuit diagram showing a conceptual configuration of a video signal output circuit 50B suitable for use in the present invention.

  The output circuit (amplifier circuit) 50B of this modified example can also provide a small and highly accurate output amplifier that is hardly affected by variations in TFT characteristics.

  That is, the output circuit 50B includes an input comparison circuit ID configured by transistors M6 to M10, and an inverting amplification output circuit IO configured by capacitors C3 and NOT3, switches S6 to S8, and transistors M11 and M12. Outputs from the DACs 10A to 10C are input to Vin via an analog switch. The output from the output circuit 50B is output from the output terminal Vout to the signal line 27.

  In this output circuit 50B, the DACs 10A to 10C are connected to the signal line 27 via the switch S5, the potential of the signal line 27 and the analog video potential sampled from the DAC are compared by the input comparison circuit ID, and both potentials match. Then, the switch S6 is turned off.

  FIG. 18 is a timing chart for explaining the operation of the output circuit 50B.

  In the chart, during the period of T1, the switches S5, S6, and S8 are on and the switch S7 is off. In this state, the potential Veven in the state where two inputs to the input comparison circuit ID, that is, IN− and IN + are equal, is held at the nd point. On the other hand, the circuit threshold Vinv of the inverting amplifier circuit is held at the point n1.

  On the other hand, during the period T2, the switch S7 is on and the switches S5, S6, and S8 are off. In this state, a potential difference is generated between the two inputs, ie, IN− and IN +. As a result, the potential at the nd point rises to (Veven + ΔV). Further, the potential at the point n1 also rises to (Vinv + ΔV). As a result, the n2 point becomes L output, the video signal line is charged by Vdd, and the potential rises.

  Then, IN + rises and when IN + = IN-(= Vin), the nd point becomes Veven again. At the same time, the potential at the point n1 returns to Vinv, the point n2 increases to the H level, and the charging of the video signal line 27 is completed.

  As can be seen from the above description, there are almost no restrictions on the series of operations due to variations in threshold values of TFTs constituting the circuit. For example, when the two inputs (IN− and IN +) of the input comparison circuit ID are equal during the period T1, the potential at the nd point can take a different value with a threshold variation, but this does not cause a problem in circuit operation.

  Further, in this variation, the input IN− from the DACs 10A to 10C is input to the gate of the TFT of the input comparison circuit ID. The capacitance of the TFT gate is generally on the order of femtofarad (fF), while the storage capacitance C2 of the DACs 10A to 10C is generally on the order of picofarad (pF).

  In general, if the input capacity of the output circuit is about 10% or less of the output capacity of the DAC, even if the input capacity of the output circuit varies, for example, by about 10% due to a variation in the manufacturing process, the variation is the output of the DAC. It is about 10% × 0.1 = 1% with respect to the capacity, which is a practically acceptable level.

  On the other hand, according to this modification, the input gate capacitance of the output circuit 50 is nearly three digits smaller than the output capacitance of the DACs 10A to 10C. Distribution can be prevented and analog output “deviation” can be eliminated.

Further, the capacitance of the capacitor C3 in this modified example is about 0.2 pF, and the entire area of the output circuit 50B can be sufficiently reduced to about 70 × 300 μm ² even when the design rule is 5 μm.

  The output current source can be only Vdd or Vss depending on the operating range of the amplifier, and the configuration can be simplified.

  Further, if the current source is a constant current source, output variations with respect to the input voltage can be suppressed to a substantially constant small level (= delay time × constant current / Csig).

  Further, in the circuit illustrated in FIG. 17, oscillation can be prevented by generating an inverted signal of the output n2 of NOT3 as n3 and inserting a resistor and a capacitor in series between n3 and Vout.

  Further, if the input of the capacitor C3 (nd in FIG. 17) greatly fluctuates with respect to a slight deviation between the two inputs (IN− and IN +) of the input comparison circuit, the output circuit 50B can be made more accurate. High output can be achieved. For this purpose, an amplifier circuit (not shown) may be further provided between nd and C3.

  In FIG. 17, IN− and IN + may be interchanged, and the capacitor C3 may be connected to ne.

Incidentally, one characteristic of the output circuit 50B illustrated in FIG.
(1) In the input comparison circuit ID, input signals (IN− and IN +) are input to the TFT gates;
(2) The output signal from the input comparison circuit ID has a unique relationship with the input signal, that is, there is only one output signal corresponding to a certain input signal.

  The input comparison circuit ID having these characteristics is not limited to that illustrated in FIG.

  FIG. 19 is a schematic circuit diagram illustrating a modification of the output circuit 50B. Also in this figure, the same components as those described above with reference to FIGS. 1 to 18 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the output circuit (amplifier circuit) 50C of FIG. 19, the input comparison circuit ID is the same as that illustrated in FIG. 17, and has a so-called “emitter (source) coupled” amplifier configuration. However, the signal input is different. In this operation, the switch group generically designated by symbol φ and the switch group generically designated by symbol / φ are alternately turned on / off.

  First, in a state where the switch group generically denoted by symbol φ is on, a signal Vin from a DAC (not shown) is input to IN−, and at the same time, the operation threshold potential of the inverter constituting NOT3 is held at both ends of the capacitor C3. The

  Next, the switch group collectively designated by the symbol / φ is turned on. At this time, if Vout <Vin, nd decreases. Then, the node S becomes L level, and current writing is performed on the signal line 27, that is, the equivalent capacitance Csig. When the potential of the signal line capacitor Csig reaches Vout = Vin or higher, the node S becomes H level, and the increase in the potential of Csig stops.

  Also in the output circuit 50C illustrated in FIG. 19, since the input signal is input to the gate of the TFT of the input comparison circuit ID, redistribution of the secondary side capacitance of the DAC can be prevented as described above with reference to FIG.

  In the input comparison circuit ID of the output circuit 50C, the output nd has a unique relationship with respect to the input potential IN−.

  FIG. 20 is a graph showing the relationship between the input potential IN− and the output nd of the input comparison circuit ID. As shown in the figure, since the input and the output have a unique relationship, the output characteristics of the output circuit 50C can be reliably and easily controlled by appropriately setting NOT3 and Vbi.

  FIG. 21 is a schematic circuit diagram illustrating a second modification of the output circuit 50B. Also in this figure, the same components as those described above with reference to FIGS. 1 to 20 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the output circuit (amplifier circuit) 50D of FIG. 21, the input comparison circuit ID has a configuration of a so-called “complementary” amplifier circuit. That is, the gates of the n-channel transistor M20 and the p-channel transistor M22 as complementary transistors are connected in common to serve as an input terminal. Therefore, as described above with reference to FIG. 17, the redistribution of the secondary side capacity of the DAC can be prevented.

  Also in this output circuit 50D, the video potential from the DAC can be written to the signal line 27 by alternately turning on the switch represented by symbol φ and the switch represented by symbol / φ.

  FIG. 22 is a graph showing the relationship between the input and output of the input comparison circuit ID of the output circuit 50D. As shown in the figure, also in the input comparison circuit ID as a “complementary” amplifier, the output has a unique relationship with respect to the input.

  Therefore, the output characteristics of the output circuit 50D can be precisely controlled by adjusting the size of the Vdd and Vss or the size of the n-channel transistor M20 and the p-channel transistor M22, that is, the gate width and the gate length.

  FIG. 23 is a schematic circuit diagram illustrating a third modification of the output circuit 50B. Also in this figure, the same components as those described above with reference to FIGS. 1 to 21 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The output circuits (amplifier circuits) 50E to 50G illustrated in FIG. 23 have a configuration of a general amplifier circuit in which a load and a driving transistor are connected in series as the input comparison circuit ID. That is, a transistor having the voltage Vbi or nd input to the gate (indicated by reference numeral M24 in FIG. 23A) acts as a load, and a transistor having Vin or Vout input to the gate acts as a driving transistor. To do.

  Also in these circuits, since a signal is input to the low-capacitance gate of the transistor, redistribution of the secondary side capacitance of the DAC can be prevented as described above with reference to FIG. Further, the video potential from the DAC can be written to the signal line 27 by alternately turning on the switch represented by the symbol φ and the switch represented by the symbol / φ.

  FIG. 24 is a graph showing the relationship between the input and output of the input comparison circuit ID of the output circuits 50E to 50G. As shown in the figure, also in these input comparison circuit IDs, the output has a unique relationship with respect to the input. Therefore, by adjusting Vbi, the size of the transistor, etc., the output of the output circuits 50E to 50G It becomes possible to precisely control the characteristics.

  FIG. 25 is a schematic circuit diagram illustrating a fourth modification of the output circuit 50B. Also in this figure, the same components as those described above with reference to FIGS. 1 to 23 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the output circuit (amplifier circuit) 50H of FIG. 25, the input comparison circuit ID has the configuration of an “emitter (source) coupled” amplifier similar to that of FIGS. However, in this variation, two inverting amplifier circuits are provided.

  The operation of the output circuit 50H will be described as follows.

  First, in the sampling period, the switch group generically designated by the symbol φ is turned on, and the other switches are turned off. In this state, nd holds the potential Vinit when the input of the input comparison circuit ID is IN− = Vcom and IN + = Vin (that is, the output of the DAC), respectively. In addition, n1A and n1B hold the circuit threshold Vinv of the inverters NOT3A and NOT3B constituting the inverting amplifier circuit, respectively.

  Next, in the writing period for the signal line, the switch group collectively denoted by the symbol / φ is turned on, and the other switches are turned off. In this state, the case of Vout <Vin will be described. First, since IN + = Vout (= signal line potential), nd becomes (Vinit + ΔV), and n1 also becomes (Vinv + ΔV). Then, n2A decreases, n3A becomes L level, and the transistor MP is turned on. As a result, the signal line 27 is charged by Vdd, the Csig potential (that is, Vout) approaches Vdd, and ΔV gradually becomes zero.

  When ΔV = 0, n1A returns to Vinv, n3A becomes H level, the transistor MP is turned off, and the signal line potential is held.

  On the other hand, when Vout> Vin, C1B, n1B, and n3B perform the same operation, so that Vsig is discharged toward Vss and reaches a desired potential, and then the signal line potential is held.

  In this modification, the output circuit 50H refers to the DAC output only during the sampling period. In the signal line writing period, the DAC can perform DA conversion of the signal potential of the next row in parallel. Also in this modified example, the input circuit of the output circuit is small, and stable sampling output that is not affected by the characteristics of the TFT is possible.

  FIG. 26 is a schematic circuit diagram illustrating a fifth modification of the output circuit 50B. Also in this figure, the same components as those described above with reference to FIGS. 1 to 25 are denoted by the same reference numerals, and detailed description thereof is omitted.

  Also in the output circuit (amplifier circuit) 50I of FIG. 26, the input comparison circuit ID has the configuration of an “emitter (source) coupled” amplifier similar to that of FIG. 17, FIG. 19 or FIG. However, in this modified example, the inverting amplifier circuit is one system, the switch / φ1 is connected to the output transistor MP, and the switch / φ2 is connected to the output transistor MN.

  The operation of the output circuit 50I will be described as follows.

  First, in the sampling period, the switch group generically designated by the symbol φ is turned on, and the other switches are turned off. In this state, nd holds the potential Vinit when the input of the input comparison circuit ID is IN− = Vcom and IN + = Vin (that is, the output of the DAC), respectively. N1 holds the circuit threshold value Vinv of the inverter NOT3 constituting the inverting amplifier circuit.

  Next, in the writing period for the first signal line, the switch group generically designated by symbol / φ and the switch / φ1 are turned on, and the switches φ and / φ2 are turned off. In this state, only when Vout <Vin, the signal line capacitance Csig is charged up to Vout = Vin by Vss. When Vout> Vin, charging is not performed.

  In the writing period for the second signal line, the switch group and the switch / φ2 collectively referred to by the symbol / φ are turned on, and the switches φ and / φ1 are turned off. In this state, only when Vout> Vin, the signal line capacitance Csig is charged up to Vout = Vin by Vss. When Vout <Vin, charging is not performed.

  Also in this modified example, the output circuit 50I refers to the DAC output only during the sampling period. In the signal line writing period, the DAC can perform DA conversion of the signal potential of the next row in parallel. Also in this modified example, the input circuit of the output circuit is small, and stable sampling output that is not affected by the characteristics of the TFT is possible. That is, it is possible to realize a signal line driver circuit in which the number of sampling latches and digital latches is small and the DAC output is amplified with high accuracy and written to the signal line.

  In the specific examples illustrated in FIGS. 25 and 26, a so-called N-TOP type differential amplification stage is employed, but a P-TOP type differential amplification stage may be used according to the output voltage range. .

  As described above, the output circuits 50A to 50I described above perform sampling comparison between the potential of the signal line and the potential of the DAC, and charge the signal line.

  However, the drive circuit of the present invention is not limited to such an output circuit, and an output circuit that charges a signal line in an analog manner can also be used.

  FIG. 27 is a circuit diagram showing an output circuit 50J for negative polarity that can be used in the present invention. The output circuit (amplifier circuit) 50J includes switches SW1 to SW8, inverters INV1, INV2, and a transistor Q1. Further, as will be described later in detail, the capacitor C2 can be shared with the secondary capacitor of the DAC.

  One end of the switch SW6 is connected to the other end of the capacitor C2, and the other end of the switch SW6 is connected to a voltage Vdd (for example, 10V). One end of the switch SW5 is connected to the input terminal of the front end inverter INV1, and the other end of the switch SW5 is connected to the output terminal of the front stage inverter INV1. One end of the switch SW7 is connected to the output terminal of the preceding inverter INV1, and the other end of the switch SW7 is connected to the input terminal of the succeeding inverter INV2. One end of the switch SW8 is connected to the input terminal of the subsequent inverter INV2, and the other end of the switch SW8 is connected to the voltage VSS (for example, 0 V).

  The capacitor C2 forms a differential voltage holding circuit, the voltage source of the voltage VDD and the constant current circuit I1 form a voltage changing circuit that changes the voltage of the signal line 27 at a constant rate, and the switch SW3 is an input voltage setting circuit. The feedback loop of the switch SW5 forms a threshold voltage setting circuit.

  FIG. 28 is a timing chart of each part of the output circuit 50J of FIG. The operation of the output circuit 50J will be described below using this timing diagram.

  First, the switches SW4, SW6, and SW8 are turned on and the switches SW1 to SW3, SW5, and SW7 are turned off within a period of time T21 to T22 (reset period). Thereby, the voltage of the signal line 27 (point d in FIG. 26) becomes the same voltage (for example, 0 V) as the voltage VSS. Further, the voltage at the input terminal of the front-stage inverter INV1 is the same voltage (for example, 10V) as the voltage VDD, and the voltage at the input terminal of the rear-stage inverter INV2 is the same voltage (for example, 0V) as the voltage VSS. Here, the voltage of the input terminal of the pre-stage inverter INV1 is set to the voltage VDD and the voltage of the input terminal of the post-stage inverter INV2 is set to the voltage VSS so that the through current does not flow in the CMOS transistors constituting the pre-stage inverter and the post-stage inverter. It is to do. That is, a through current is prevented from flowing by sufficiently turning off one of the p-type MOS transistor and the n-type MOS transistor constituting the CMOS transistor. Thereby, the power consumption in the output circuit 50J can be reduced. Therefore, the voltage applied to the input terminal of the front-stage inverter INV1 and the input terminal of the rear-stage inverter INV2 may be either the voltage VDD (for example, 10V) or the voltage VSS (for example, 0V).

  Next, the switches SW3 and SW5 are turned on and the switches SW1, SW2, SW4, and SW6 to SW8 are turned off during the period from time T22 to T23 (writing period to the secondary side capacitor C2). As a result, the voltage at the point a becomes substantially equal to the voltage of the input video signal Vin from the DAC. FIG. 27 shows an example in which the voltage of the input video signal Vin is 3V. However, since the switch SW1 is off, the voltage of the signal line 27 is maintained at 0V.

  Further, since the switch SW5 is on, the voltage at the point b is set to a voltage substantially equal to the threshold voltage (here, 5V) of the preceding inverter INV1. That is, by feeding back the output of the previous stage inverter INV1 to the input, the voltage at the input terminal and the output terminal of the previous stage inverter INV1 is set to a voltage substantially equal to the threshold voltage of the previous stage inverter INV1. Accordingly, the capacitor C2 holds a differential voltage (for example, 2V) between the voltage (for example, 3V) of the input video signal Vin and the threshold voltage (for example, 5V) of the preceding inverter INV1.

  Next, after time T23 (writing period, stable period), the switches SW1, SW2, and SW7 are turned on, and the switches SW3 to SW6 and SW8 are turned off. At time T3, point a is 3V, while point d is 0V. For this reason, when the switch SW1 is turned on, the voltage at the point a is pulled down to the point d and decreases. Since the capacitor C2 maintains the above-described differential voltage (2V), the voltage at the point b on the other end side of the capacitor C2 also decreases following the voltage at the point a, and the output of the logic circuit LC is inverted. To a low level (for example, 0 V). Thereby, the transistor Q1 is turned on, and a constant current is supplied from the constant current circuit I1 to the signal line 27 via the transistor Q1 and the switch SW2. For this reason, the voltage of the signal line 27 (point d) rises with a constant slope dt.

  When the voltage of the signal line 27 rises with a constant slope dt, the voltages at points a and b rise accordingly with a constant slope dt. Eventually, at time T4, the voltage of the signal line 27 becomes equal to 3V that is the voltage of the input video signal Vin, and the voltage at the point a is also equal to 3V. Since the capacitor C2 holds the above-described differential voltage (2V), the voltage at the point b in FIG. 26 is 5V, which is the threshold voltage of the preceding inverter INV1. For this reason, the output of the logic circuit LC is inverted again to a high level (for example, 10 V). Thereby, the transistor Q1 is turned off, and the current supply from the constant current circuit I1 to the signal line 27, that is, the supply of voltage is cut off. With such an operation, the signal line 27 is set to 3 V, which is substantially equal to the voltage of the input video signal Vin.

  Next, a specific example in which the output circuit 50J is modified for positive polarity will be described.

  FIG. 29 is a circuit diagram showing a detailed configuration of the output circuit 50K for positive polarity. As shown in FIG. 27, in the output circuit (amplifier circuit) 50K for positive polarity, the transistor Q1 is n-type and the constant current circuit I1 is connected to the voltage VSS. Different from the output circuit 50J for negative polarity. Since the other points are the same as those of the negative polarity output circuit 50J described above, detailed description thereof is omitted.

  As described above, the signal lines 27 can be set substantially equal to the voltage of the input video signal Vin by the output circuits 50J and 50K described with reference to FIGS.

  In addition, since the input video signal Vin is supplied to the signal line 27 after the voltage difference between the threshold voltage of the previous inverter INV1 and the input video signal Vin is held in the capacitor C2, the threshold voltage of the previous inverter INV1 is supplied. Even if there is a variation in the voltage, the voltage of the signal line 27 can be prevented from being affected.

  Further, according to the output circuits 50J and 50K, when the voltage VDD is supplied to the signal line 27, the voltage VDD is supplied via the constant current circuit I1, and therefore, the voltage depends on the voltage of the input video signal Vin and the voltage of the signal line 27. Instead, the voltage of the signal line S can be raised with a constant slope dt. Therefore, the linearity of the output circuits 50J and 50K can be ensured, and so-called write errors can be prevented.

  Further, according to the output circuits 50J and 50K, when setting the differential voltage to be held by the capacitor C2 to the capacitor C2, the threshold voltage of the previous inverter INV1 and the voltage of the input video signal Vin are sampled in the same cycle. As a result, the differential voltage can be set more accurately than when these two voltages are set in separate cycles.

  Note that the various switches shown in the above specific examples can be configured using transfer gates or analog switches. In the above specific example, an example in which two stages of inverters that invert and amplify an input signal are connected in series to configure the logic circuit LC has been described. There is no particular limitation on the internal configuration of the circuit LC.

  Next, another output circuit that can be used in the drive circuit of the present invention will be described.

  FIG. 30 is a circuit diagram of the output circuit 50L. The output circuit (amplifier circuit) 50L sets the voltage at the input terminal of each inverter of the inverting amplifier circuit that controls the voltage of the signal line to be approximately equal to the threshold voltage of each inverter, thereby reducing the operation of each inverter. Even if the threshold voltage varies, the voltage of the signal line can be controlled to a desired voltage.

  That is, as shown in FIG. 30, each output circuit 50L includes switches SW1 to SW3, an inverting amplifier circuit IA including a front inverter INV1, a middle inverter INV2, and a rear inverter INV3, and a capacitor C2. . The signal line 27 driven by the output circuit 50L is connected to a pixel display TFT, a liquid crystal capacitor, an auxiliary capacitor, and the like. In FIG. R and capacitor Csig.

  One end of the switch SW1 is connected to the signal line 27, and the other end of the switch SW1 is connected to one end of the switch SW3 and one end of the capacitor C2. The other end of the switch SW3 is connected to the input terminal of the input video signal Vin output from the DAC. The other end of the capacitor C2 is connected to the input terminal of the inverting amplifier circuit IA. The output terminal of the inverting amplifier circuit IA is connected to one end of the switch SW2. The other end of the switch SW2 is connected to the signal line 27 described above.

  The inverting amplifier circuit IA is configured by connecting a front-stage inverter INV1, a middle-stage inverter INV2, and a rear-stage inverter INV3 in series. The switches SW1 to SW3 are controlled to be switched by a switch switching control circuit (not shown).

  The inverting amplifier circuit IA forms a signal line voltage control circuit, the capacitor C2 forms a first differential voltage holding circuit, and the switch SW3 forms a first differential voltage setting circuit.

  FIG. 31 is a timing chart of each part in the output circuit 50L. The operation of the output circuit 50L will be described below using this timing diagram.

  First, within a period (sampling period) between times T11 and T12, the switch SW3 is turned on, and the other switches SW1 and SW2 are turned off. Thereby, the voltage at the point a becomes substantially equal to the voltage of the input video signal Vin. FIG. 31 shows an example in which the voltage of the input video signal Vin is 3V. However, since the switch SW1 is off, the voltage of the signal line 27 (point d) maintains the voltage supplied before time T11. In the example of FIG. 31, 7V is maintained.

  Here, as described above, the threshold voltage of the front inverter INV1 is 5.5V, the threshold voltage of the middle inverter INV2 is 4.5V, and the threshold voltage of the rear inverter INV3 is 5V. Assuming that, by some means, the voltage at the input terminal of the front inverter INV1 is set to 5.5V, the voltage at the input terminal of the middle inverter INV2 is set to 4.5V, and the voltage at the input terminal of the rear inverter INV3 is set to Set to 5V. That is, the voltages at the input terminals of the inverters INV1 to INV3 are set substantially equal to the respective threshold voltages of the inverters INV1 to INV3. A method for setting the voltage at the input terminals of the inverters INV1 to INV3 to the threshold voltage will be described later.

  In this way, by setting the input terminals of the inverters INV1 to INV3 to be substantially equal to the respective threshold voltages, the amplification degree of the inverting amplifier circuit IA can be made close to the maximum value. The amplification degree of the inverting amplifier circuit IA refers to the ratio of the change amount of the output voltage to the change amount of the input voltage of the inverting amplifier circuit IA. That is, with this setting, even if the voltage at the input terminal of the inverting amplifier circuit IA is slightly changed, the voltage at the output terminal of the inverting amplifier circuit IA is inverted and greatly changed.

  In addition, as described above, the voltage at point a in FIG. 30 is 3V, which is the voltage of the input video signal Vin, and the voltage at point b is 5.5V, similar to the voltage at point e described above. . For this reason, during the period from time T11 to time T12 (sampling period), the capacitor C2 stores the voltage (for example, 3V) of the input video signal Vin and the pre-stage inverter INV1 that the capacitor C2 should hold after time T12 described later. The differential voltage (for example, 2.5 V) of the threshold voltage (for example, 5.5 V) is set.

  Next, in a period after time T12 (writing period, stable period), the switches SW1 and SW2 are turned on, and the switch SW3 which is the other switch is turned off. At time T12, point a in FIG. 29 is 3V, while point d is 7V. For this reason, when the switch SW1 is turned on, the voltage at the point a rises while being pulled to the point d. Since the capacitor C2 holds the above-described differential voltage (2.5V), the voltage at the point b on the other end side of the capacitor C2 also increases following the voltage at the point a.

  When the voltage at the point b rises, the logic output of the front stage inverter INV1 tries to become low level (for example, 0V), the logic output of the middle stage inverter INV2 tries to become high level (for example, 10V), and the logic output of the rear stage inverter INV3 The logic output is going to become a low level (for example, 0V). That is, when the voltage at the point b rises, the logic output of the inverting amplifier circuit IA is inverted and tends to become a low level (for example, 0 V). As a result, the voltage of the signal line 27 also decreases. When the voltage of the signal line decreases, the voltages at points a and b also decrease accordingly.

  When the voltage of the signal line 27 (point d) drops as it is, the voltage of the signal line eventually becomes equal to 3V that is the voltage of the input video signal Vin, and the voltage at the point a is also equal to 3V. Since the capacitor C2 holds the above-described differential voltage (2.5V), the voltage at the point b becomes 5.5V which is the threshold voltage of the previous inverter INV1. For this reason, the logic output of the front stage inverter INV1 is inverted to become high level (for example, 10V), the logic output of the middle stage inverter INV2 is inverted to attempt to become low level (for example, 0V), and the rear stage inverter INV3 The logic output of the signal is inverted and becomes high level (for example, 10V). That is, when the voltage at the point b falls below 3V, the logic output of the inverting amplifier circuit IA is inverted and tends to be at a high level (for example, 10V). As a result, the voltage of the signal line 27 also increases. When the voltage of the signal line increases, the voltages at points a and b in FIG. 30 also increase accordingly. By repeating such a phenomenon, after time T13, the voltage of the signal line 27 converges to be approximately equal to 3V that is the voltage of the input video signal Vin and is stabilized.

  However, in practice, the voltages at points a, d, and f are not completely stabilized at 3V, but are shifted by the offset voltage ΔVa1 to 3V + ΔVa1. Further, the voltage at the point b is also shifted by the offset voltage ΔVa1 and becomes 5.5V + ΔVa1. Therefore, the voltage at the point e is shifted by the offset voltage ΔVb1 to 5.5V−ΔVb1. Further, the voltage at the point c is shifted by the offset voltage ΔVc1 and becomes 4.5V + ΔVc1.

  However, as described above, the voltages of the input terminals of the inverters INV1 to INV3 are set substantially equal to the respective threshold voltages during the period from the time T11 to the time T12, so that the amplification degree of the inverting amplifier circuit IA becomes extremely large. ing. For this reason, the offset voltage ΔVa1 can be made extremely small. That is, the offset voltage ΔVa1 can be considered to be substantially 0V, and it can be said that the voltages at the points d, a, and f are substantially equal to 3V.

  As described above, according to the output circuit 50L, the voltages of the input terminals of the front-stage inverter INV1, the middle-stage inverter INV2, and the rear-stage inverter INV3 constituting the inverting amplifier circuit IA are set to be approximately equal to the respective threshold voltages, and Since the difference voltage between the voltage of the input video signal Vin and the threshold voltage of the previous inverter INV1 is held in the capacitor C1, the switches SW1 and SW2 and the inverting amplifier circuit IA constitute a feedback loop. The voltage of the signal line 27 can be set substantially equal to the voltage of the input video signal Vin.

  FIG. 32 is a schematic circuit diagram showing a modification of the output circuit 50L shown in FIG. As shown in FIG. 32, in the output circuit 50M, each of the inverters INV1 to INV3 is short-circuited by switches SW4 to SW6, and capacitors C3 and C4 are provided therebetween.

  The inverter circuit 7 with the threshold voltage setting function located on the most input side is not provided with the capacitor C2, and the input terminal of the previous inverter INV1 is directly connected to the other end of the capacitor C2. Therefore, the capacitor C2 holds a differential voltage between the voltage of the input video signal Vin and the threshold voltage of the previous inverter INV1.

  The inverting amplifier circuit IA constitutes the signal line voltage control circuit in the present embodiment, the capacitor C2 constitutes the first differential voltage holding circuit, the switches SW3 and SW4 constitute the first differential voltage setting circuit, and the capacitor C3. , C4 constitute a second differential voltage holding circuit, and each of the switches SW5, SW6 constitutes a second differential voltage setting circuit.

  Since the operation of the output circuit 50M according to this modification is the same as that of the output circuit 50L described above, detailed description thereof is omitted.

  The output circuits 50J to 50M that can be used in the video signal line driving circuit of the present invention have been described in detail above with reference to FIGS.

  Next, an interface suitable for connecting the output circuits 50J to 50M and the serial DACs 10A to 10C described above will be described.

  FIG. 33 is a schematic circuit diagram showing a connection portion between the serial DAC described above with reference to FIGS. 1 to 14 and the output circuits 50J to 50M described above with reference to FIGS.

  That is, in the figure, the schematic configuration of the DACs 10A to 10C and only the input part of the output circuits 50J to 50M are shown. As is clear from the figure, the secondary-side capacitor C2 of the DAC is directly used as the input capacitor C2 of the output circuits 50J to 50M. In the figure, the sizes of the capacitors C1 and C2 are each about 1 pF, and the gradation voltage values are, for example, Vref = 9 volts and Vcom = 6 volts in the case of positive polarity. In this case, Vref = 1 volt and Vcom = 4 volt.

  FIG. 34 is a timing chart showing the operation of each part in FIG. In the first half of one horizontal period, the switch S1 is turned on / off while the switch SW1 is turned on, so that charge is redistributed between the capacitors C1 and C2 and serial DA conversion is executed. That is, DA conversion and sampling to the output circuit are executed simultaneously.

  Next, in the second half of one horizontal period, the switch SW2 is turned on with the switch SW1 turned off, and the video signal charge as an analog signal accumulated in the capacitor C2 is written to the signal line 27 by the output circuits 50J to 50M.

  Thus, by sharing the capacitor C2 between the DAC and the output circuit, the circuit can be simplified and the circuit area can be reduced. However, as can be seen from the timing chart of FIG. 34, sampling to the output circuit and serial DA conversion are processed in parallel, so the buffer output period is short.

  FIG. 35 is a schematic circuit diagram showing another specific example of the connection portion between the serial DAC and the output circuits 50J to 50M. That is, in the figure, the schematic configurations of the DACs 10A to 10C described above with reference to FIGS. 1 to 14 and only the input units of the output circuits 50J to 50M described above with reference to FIGS. As can be seen from the figure, in this specific example, the secondary-side capacitor C2 of the DAC and the input capacitor C3 of the output circuit are provided separately. In the figure, the sizes of the capacitors C1, C2 and C3 are about 1 pF, and the gradation voltage values are, for example, Vref = 9 volts and Vcom = 1 volts in the case of positive polarity. In the case of negative polarity, Vref = 1 volt and Vcom = 9 volt can be set. Further, the potential at the node N in the figure can be about 5 to 9 volts in the case of positive polarity and about 1 to 5 volts in the case of negative polarity.

  FIG. 36 is a timing chart showing the operation of each unit in FIG.

  In the first half of one horizontal period, the switch S1 is turned on / off with the switch SW0 turned off and the output circuit is disconnected, thereby redistributing charges between the capacitors C1 and C2 and performing serial DA conversion. Execute. That is, only the serial DA conversion process is performed without sampling the output circuit.

  Next, the switch SW0 is turned on for a predetermined period, and sampling to the output circuit is executed. After that, the switch SW2 is turned on to execute writing from the main circuit to the signal line. This writing period continues until the first half of the next one horizontal period, and is executed redundantly with the DAC DA conversion process.

  When writing to the signal line is completed, a reset period is provided in which the switch SW3 is once turned on to discharge the capacitor C3 before the next sampling.

  According to this specific example, the data writing D process from the output circuit to the signal line and the serial DA conversion process can be operated simultaneously.

  In this specific example, the reason why Vref and Vcom, which are reference voltages for DA conversion, are set in the range of 9 to 1 volt is that when the DAC capacitor C2 and the output circuit capacitor C3 are connected, the accumulated charge Is halved. That is, if a double amount of charge is first stored in the capacitor C2 in the DAC, a predetermined charge amount can be obtained after the charge is distributed to the capacitor C3 of the output circuit.

  The serial DAC, the video signal output circuit, and their connection interfaces in the video signal line driving circuit of the present invention have been described above in detail.

  Next, the overall configuration of the video signal driving circuit including these elements will be outlined.

  FIG. 37 is a circuit block diagram of the multi-gradation display device according to the embodiment of the present invention. This example can be realized as an XGA display device having 6 bits (64 gradations) and 10 inches diagonal, for example.

  FIG. 38 is a circuit block diagram showing a video signal driving circuit of the multi-gradation display device shown in FIG.

  FIG. 39 is a timing chart showing the operation of the video signal driving circuit of FIG.

  In the circuit of FIG. 37, the image display unit 20 is provided with a plurality of video signal lines 27 and a plurality of scanning lines 28 orthogonal thereto, and pixel TFTs 29 are provided at intersections thereof. A liquid crystal capacitor Clc and an auxiliary capacitor Cs are connected to the drain electrode of the TFT 29 to form a display pixel.

  The scanning line driving circuit includes, for example, a shift register and a scanning line driving buffer, and each buffer output is supplied to each scanning line 28. On the basis of the scanning line signal supplied to each scanning line 28, the TFTs 29 in the corresponding row are on / off controlled.

  The video signal line driving circuit illustrated in FIG. 38 includes a digital video data line (digital bus) DB, a shift register 21, a sampling latch 24, a load latch 23, DACs 10A to 10C, and an output circuit 50. ing. As described above, the DACs 10 </ b> A to 10 </ b> C output an analog potential once during one horizontal period, and a video signal is written to one signal line 27 via the output circuit 50.

  Digital video signals output from an external gate array GA are sequentially written into the digital bus DB. Here, the video signal line driving circuit SD of the present invention includes serial DACs 10A to 10C as described in detail with reference to FIGS. For this reason, it is necessary to devise the order of data output when outputting digital video data stored in the gate array GA.

  FIG. 40 is a conceptual diagram for explaining the output order of digital video data from the gate array GA. When digital video data is output to a conventional parallel DAC as shown in FIG. 53, as shown in FIG. 40A, the least significant bit (LSB) stored in the gate array GA A multiple of 6-bit data from the most significant bit (MSB) to the most significant bit (MSB) may be output in parallel.

  On the other hand, when data is output to the serial DAC of the present invention, as shown in FIG. 40 (b), the common divisor of this number is used in accordance with the number of signal lines 27 of the display device. It is necessary to output data in order from the lower bit. For this purpose, means for rearranging data may be provided inside the gate array GA or outside the gate array GA.

  On the other hand, if the specific example illustrated in FIG. 37 is realized by a polysilicon TFT, the variation in TFT characteristics may be relatively large. Therefore, the gate array output of the signal input to the video signal line driving circuit has an amplitude of 5 volts or more. Is desirable.

  For example, as illustrated in FIG. 37, the level shift circuit LS is connected to the gate array GA of the 3.3 volt power supply, and the digital data of 3.3 volt amplitude, the clock and the control signal are all level shifted to 5 volt amplitude. After that, it may be supplied to the video signal line driving circuit SD.

  If the level shift is not performed before being supplied to the video signal line drive circuit SD, (1) the power supply voltage of the gate array itself is set to 5 volts, or (2) it is on the same substrate as the video signal line drive circuit. It is necessary to build a level shift circuit using a polysilicon TFT or the like. However, in the case of (1), the power consumption is high, and in the case of (2), when the delay variation of the level shift circuit is large, the desired digital video data can be supplied to the shift register at a desired timing. There is a risk of “data shift”.

  A clock signal (CLK, / CLK) and a trigger signal (XST) are input to the shift register 21. The sampling latch 24 is controlled by the output from the shift register 21, and the digital video data is sequentially stored in the sampling latch 24.

  Next, the digital data stored in the sampling latch 24 is simultaneously latched in the load latch 23 by the control signals (LR, / LR) for data loading, and then output to the DACs 10A to 10C. Here, as illustrated, a level shift circuit LS may be provided between the load latch 23 and the DACs 10A to 10C as necessary.

  When a DAC is provided for each signal line 27, the sampling, loading, and output to the DAC described above are repeated for 6 bits, that is, 6 times. This series of operations is as described in detail with reference to FIGS. 1 to 14 and as shown in the timing chart of FIG. Every time, digital data is converted into a voltage and held in a capacitor in the DAC.

  The output circuit 50 receives the output from the DAC during the sampling period, and then writes the voltage to the signal line 27 during the writing period. Details of this are as described above with reference to FIGS. The DAC and the output circuit 50 are not connected during the writing period.

  Next, a modified example of the video signal line driving circuit according to the present invention will be described.

  41 and 42 are conceptual diagrams for explaining a modified example of the video signal line driving circuit according to the present invention. Here, FIG. 41 (a) corresponds to the basic form shown in FIG. 38, and FIGS. 41 (b), 42 (a), and (b) respectively correspond to modified examples.

  In these modified examples, a selection switch SSW or an analog switch ASW is provided so that one of a plurality of signal lines can be selected, whereby a part of the latches 24A and 24B, the level shifter LS, the DACs 10A to 10C, and the output circuit 50 Can be shared to simplify the circuit.

  In the following description, a case where one of the two signal lines 27 can be selected will be described for convenience. Then, all the signal lines are divided into an odd number (2N-1) and an even number (2N). However, it goes without saying that the number of selections and selection methods in the present invention can be variously modified.

  First, in the modified example illustrated in FIG. 41B, by providing the selection switch SSW, the latches 24A and 24B can be used by switching between two signal lines. According to this configuration, the number of latches can be halved. As a specific operation method, one horizontal period is divided into twelve, and the odd-numbered signal line DAC and the even-numbered signal line DAC are switched and connected 12 times. Writing to the signal line by the output circuit (AMP) can be performed simultaneously after the analog outputs of all the DACs are determined. Since writing to the signal line can be performed over almost one horizontal period, there is an advantage that the average amount of current is small.

  Next, in the modified example illustrated in FIG. 42A, the latches 24A and 24B and the DAC can be shared between the two signal lines by providing the analog switch ASW. That is, the number of latches and DACs can be halved.

  As the operation method, one horizontal period is divided into two, the odd-numbered signal lines are connected to the DAC in the first half period, and the even-numbered signal lines are connected to the DAC 10 in the second half period. Writing to the signal line by the output circuit 50 is performed immediately after the odd-numbered DAC output is determined. The writing time is approximately ½ of one horizontal period. Then, after the even-numbered DAC output is determined, writing to the remaining signal lines is performed. In the case of this modification, the area occupied by the DAC can be halved compared to that illustrated in FIG.

  In this modified example, one DAC sequentially outputs analog potentials to a plurality of signal lines, but the selection order of the signal lines at that time differs for each horizontal period or for each frame. It is good to do so. This is because an error voltage that may slightly occur between the signal line to which the voltage has been written first and the signal line to which the voltage has been written later can be temporally averaged.

  Next, in the modified example illustrated in FIG. 42B, the number of latches, DACs, and output circuits can be halved. That is, in this modified example, an analog switch ASW is provided between the output circuit 50 and the signal line 27 so that writing is performed in a period of about ½ of one horizontal period. However, for this purpose, it is desirable to secure the current capacity by forming the analog switch ASW relatively large.

  In the specific example described above, one DAC is used for one signal line. However, as another idea, two output circuits 50 are arranged in parallel for one signal line. An “analog buffer method” in which one of them is used for sampling and the other is used for signal line writing can be realized. When this configuration is applied to the above-described modification of FIG. 42A, signal line writing can be continued for one horizontal period. Therefore, there is an advantage that the average current amount can be halved.

  In the configuration described above, it is particularly advantageous to use the “common inversion driving method”. That is, the common potential is varied within a range of 2.5 volts ± 2.5 volts every horizontal period. In response to this, the signal line potential is output at 2.5 volts ± 2.5 volts. In this way, the voltage output possible range of the DAC and output circuit 50 can be reduced to about 5 volts at most. In a circuit composed of TFTs having a characteristic variation larger than that of a crystalline silicon TFT such as a polysilicon TFT, for example, the width of threshold variation narrows the output range of the output circuit 50. In a large display device having a screen diagonal size of 13 inches or more, it is not realistic to change the common potential every horizontal period. Therefore, the common potential is fixed to, for example, about 5 volts, and the signal line potential is set to 1 to 1. It is a good idea to control in the range of 9 volts. In the case of the output circuit illustrated in FIGS. 25 and 26, this can be realized by adjusting Vdd, Vss, and Vbi.

  In the specific example described above, it is necessary to operate the shift register 21 at high speed. In the case of 10.4 inches XGA, the number of digital bus DBs is divided into four screens and is about 8 phases × 3 colors (RGB) = 24. In this case, one bit data must be latched for about 60 nanoseconds (that is, about 16 MHz). If the shift register can follow the 16 MHz clock, there is no problem, but if the TFT characteristics vary greatly, the 16 MHz operation of the shift register may become uncertain. In order to solve such a problem, there is a method of operating the shift register 21 corresponding to 16 MHz with an 8 MHz clock.

  43 and 44 are conceptual diagrams showing the configuration of such a double speed operation shift register. That is, FIG. 4A shows the block configuration, and FIG. 4B shows the schematic circuit. In the configuration of FIG. 43, a half-clock type shift register 21 that operates according to each of CLK and / CLK is provided, and a control signal is supplied to the sampling latch 24 at a period twice that of the clock CLK.

  44, two 1-clock shift type shift registers 21A and 21B are provided, and by supplying a clock and its inverted signal to each, data is sampled at a double cycle and supplied to the load latch 23. To do.

  Further, separately from the illustrated example, two shift registers may be provided in parallel, and one may be operated by shifting one of the other by a half clock.

  When the serial type DAC as described above with reference to FIGS. 1 to 14 is employed, the circuit occupation area can be greatly reduced as compared with the case where the conventional parallel type DAC is used. Therefore, as illustrated in FIGS. It becomes easy to form a slightly complicated shift register.

  The case where the present invention is applied to the liquid crystal display device will be described. When the threshold voltage of the liquid crystal material is about 2.5 volts, the DACs 10A to 10C and the output circuit 50 are compared with the case of the 4 volt type liquid crystal. There is an advantage that the output range can be reduced. Further, when the threshold voltage of the liquid crystal is about 1.5 volts, vertical line (V line) inversion driving or horizontal / vertical (H / V) inversion driving is performed (particularly, the diagonal size is 13 inches or more). (This is often the case with large-screen liquid crystal display devices), and it is not necessary to set the output ranges of the DACs 10A to 10C and the output circuit 50 to 10 volts, which is advantageous in that the power supply can be reduced.

  A video signal line driving circuit according to the present invention is formed on a glass substrate simultaneously with a pixel driving TFT. A transmissive display device, a reflective display device, a transflective display device, and a light-emitting display device are extremely advantageous as a display device for a portable terminal in that the module strength is large and the frame portion can be reduced.

  Finally, a 10.4 inch XGA liquid crystal display device as an embodiment of the present invention will be described.

  FIG. 45 is a block diagram showing an embodiment of a video signal line driving circuit according to the present invention.

That is, the specific example shown in the figure corresponds to a 10.4 inch diagonal XGA liquid crystal display device. In this figure, elements that are the same as those described above with reference to FIGS. 1 to 43 are given the same reference numerals, and detailed descriptions thereof are omitted.

  FIG. 46 is a timing chart showing a specific example of the operation of the display device of this embodiment. In this embodiment, the video signal is supplied in 8 phases and 4 divisions. That is, digital image data of 8 phases × 3 (RGB) × 4 (division) = 96 is output from the gate array GA. Further, 15 types of signals are supplied as the clock CLK and the control signal CTRL, and these are input at a 5 volt level to the glass substrate on which the drive circuit is formed.

  On the other hand, there are four types of power sources of 12, 5, -2, and 0 volts, which is advantageous in that the 10-volt power source that has been conventionally required is unnecessary. Furthermore, YGVdd and XVdd are shared.

  768 signal lines 27 are provided, to which a shift register 21, a sampling latch 24, level shifters LS, DAC, and an output circuit 50 are connected. The power supply for each element is as shown in FIG.

  The shift register 21 is a half-clock shift output shift register that receives a control signal and a clock signal from the gate array GA and operates at double speed. This specific configuration is, for example, as illustrated in FIG.

  According to this embodiment, by providing the serial DAC, a small and light display device can be formed with a circuit area much smaller than that of the conventional one. Further, by devising the configuration of the output circuit 50, it is possible not only to ensure a stable operation against the characteristic variation of the polysilicon TFT but also to significantly improve the manufacturing yield, as well as the initial characteristics and reliability of the display device. Can also be improved.

  FIG. 47 is a conceptual diagram showing a variation of the shift register 21 that can be employed in the above-described specific example.

  FIG. 48 is a timing chart for explaining the operation.

  Normally, the shift register sends a pulse to the next stage with reference to the rising edge of the clock signal, but the shift register of this modified example performs an operation similar to a half clock shift register.

  That is, first, data (Data) (1) is output to the output A of the sampling latch by the output a * of the shift register S / RI. The shift register S / RII operates in the same manner. However, since the operation is similar to the half clock operation, not the data (2) but the data (1) is first latched at the output B, then the data (2) is latched. Similarly, the shift register S / RIII first latches the previous data (2), but finally latches the desired data (3).

  The feature of this modification is that it handles digital data, and further transfers data to the DAC via the load latch after the sampling latch stage, so that it does not depend on the operation before the desired data is obtained. It is in. In a configuration such as a half-clock shift register, it is possible to prevent the shift register output from overlapping by the logical operation of the previous stage and its own stage, but it is not easy to operate at high speed because the pulse width is halved. There is. In addition, the sampling latch may not operate due to an increase in the number of elements for logical operation and the influence of a delay associated therewith, resulting in a “thinning” of the pulse width.

  On the other hand, according to this modified example, the desired data is latched after the previous stage data is latched once. However, since the pulse width can be ensured reliably, compared with the half clock shift register. Therefore, there is an advantage that the operation margin is wide and the number of elements is small.

  Next, a configuration to which a gamma correction circuit is added will be described as a specific example of the drive circuit of the present invention.

  FIG. 49 is a schematic diagram for explaining a drive circuit of a liquid crystal display device to which a gamma correction circuit is added. 10A is a timing chart of a gate array for supplying signals to a drive circuit having a 6-signal line selection configuration, FIG. 10B is a conceptual diagram of the drive circuit having a 6-signal line selection configuration, and FIG. Is a timing chart of a gate array for supplying a signal to a drive circuit having an 8-signal line selection configuration, and FIG.

  First, the case of the 6-signal line selection configuration will be described with reference to FIGS. 49A and 49B. For the 6 signal lines, the drive circuit has 6 latches 24, 1 gamma ( γ) A correction circuit 80, a DAC 10C, and six output circuits (amplifier circuits) 50 are provided. That is, the DAC 10C sequentially selects one of the six signal lines and writes the analog potential. Here, the DAC 10C has the configuration illustrated in FIG. The gamma correction circuit 80 has a role of correcting an optical response characteristic of the liquid crystal and displaying an image in accordance with the visual sensitivity characteristic of the human naked eye.

  As shown in FIG. 49A, one horizontal period of 22.75 microseconds is divided by 2 microseconds, and in the first 2 microseconds, (6N + 1) th (where N is a natural number) signal line Bit data (d1 to d6) are latched by the latch 24. When the data latch is completed, the gamma correction circuit 80 selects the reference potentials V + and V− with reference to the latch data of the upper 3 bits (d1 to d3). On the other hand, the DAC 10C refers to the data of the lower 3 bits (d4 to d6), and charges the input capacitors C11, C12 and C13 provided in the DAC simultaneously with the reference potentials V + and V−, respectively.

  When the charging of the primary side capacitor is completed, the corresponding charging potential is sequentially redistributed with the secondary side capacitor, that is, the output capacitor C21 in order from the lower bit, and the desired analog potential Vi is obtained. The analog potential Vi thus formed is referred to by the output circuit 50 and written to the signal line 27.

  After the next 2 microseconds, the same operation is repeated up to the (6N + 2) th to (6N + 6) th signal lines, and analog potentials are written to all the signal lines. A blank period of 10.125 microseconds is provided in the second half of one horizontal period.

  Here, in the signal processing for each signal line, as described above with reference to FIG. 9, the DAC 10C uses the secondary side capacitors C21 and C22 alternately and makes them parallel while performing DA conversion for the next signal line. Thus, writing of the analog potential to the previous signal line can be executed. Accordingly, potential can be sufficiently written while maintaining high-speed operation, and a high-quality image can be displayed.

  In this specific example, since the gamma correction circuit 80 is of a power supply selection type, voltage conversion for the upper 3 bits is executed at a very high speed and takes almost no time. Further, since the DAC 10C only needs to perform DA conversion for the lower 3 bits, the DAC 10C can be operated at high speed.

  In the case of the 8-signal line selection configuration shown in FIGS. 49C and 49D, basically the same operation can be performed. That is, as shown in FIG. 49C, one horizontal period of 22.75 microseconds is divided by 2 microseconds, and in the first 2 microseconds, (8N + 1) th (where N is a natural number) The bit data of the signal line is latched, gamma correction, DA conversion, and output. Thereafter, the same operation as described above can be performed up to the (8N + 8) th signal line through a blank every 0.125 microseconds. In the second half of one horizontal period, a blank period of 5.875 microseconds is provided.

  FIG. 50 is a configuration diagram showing a more detailed specific example of a driving circuit having a 6-signal line selection configuration.

  That is, the data (d1 to d6) of each bit is input to each load latch 24 and latched. Of these, the upper 3 bits of data (d1 to d3) are input to the gamma correction circuit 80, and one of a plurality of reference potentials is selected based on the data and supplied to the DAC 10C as V + and V−. Is done.

  The gamma correction circuit 80 is configured by combining an inverter 80A, an AND gate 80B, an OR gate 80C, and a switch 80D, for example, as illustrated. Furthermore, in the illustrated example, nine types of potentials V1 to V9 are prepared as reference potentials.

  The logic gates 80A to 80C perform a logical operation based on the upper 3 bits of data input from the latch 24, and turn on one of the switches 80D according to the result, thereby causing any one of the reference potentials V1 to V9. Is selected and output as V + and V-.

  The reference potentials V1 to V9 can be, for example, voltage nodes of a total of 9 levels obtained by dividing the power supply voltage range of 4 to 5 volt range such that the effective voltage to the liquid crystal is 4 to 5 volts. However, in order to correct according to the visibility characteristic, V1 to V9 are formed by dividing the power supply potential at unequal intervals. Then, any two consecutive potentials Vi and V (i + 1) among the reference potentials V1 to V9 are selected and passed to the DAC side as V + and V-, so that the upper 3 bits of digital data are substantially converted. It was converted to analog. Next, the DAC is further finely divided between Vi and V (i + 1) to form a higher-order gradation potential as described below.

  On the other hand, the lower 3 bits of data (d4 to d6) latched in the load latch 24 are sent to the DAC 10C as they are.

  In the illustrated example, the DAC 10C includes three primary capacitors C11 to C13 and six secondary capacitors C21 to C26. The DAC 10C charges the primary side capacitors C11 to C13 using the reference potentials V + and V− selected by the gamma correction circuit 80 based on the input data (d4 to d6). The primary side capacitors C11 to C13 complete analog conversion by redistributing charges with any of the secondary side capacitors C21 to C26.

  The secondary-side capacitor that has received the charge redistribution writes an analog potential to the corresponding signal line 27 via the corresponding output circuit (amplifier circuit) 50M. In parallel with this writing operation, DA conversion for the next signal line can be executed.

  As described above, the drive circuit shown in FIG. 50 performs gamma correction on the input digital signal, executes DA conversion, and writes the formed analog potential to the signal line 27. At this time, gamma correction and DA conversion processing for the next signal line and writing processing for the previous signal line can be executed in parallel, and high-speed and reliable supply of analog signals can be realized. it can.

  FIG. 51 is a conceptual diagram showing a modification of the present invention. That is, what is illustrated in the figure is a “block sequential scanning type” sample-and-hold type (hereinafter, abbreviated as S / H type) liquid crystal display device. In this type of liquid crystal display device, a video signal is written for each block composed of a predetermined number of video signal lines.

  That is, the sampling switch is controlled by a timing circuit constituted by a shift register or the like, and the video signal supplied via the video signal line is held in the video signal line capacity and then written to the pixel capacity.

  Also in this modification, a video signal drive circuit VD and a scanning line drive circuit SD are provided adjacent to the image display unit 20.

  The image display unit 20 is wired with a double textbook video signal line 27 and a double textbook scanning line 28 orthogonal thereto, and a pixel TFT 29 is provided at the intersection of these lines. A liquid crystal capacitor Clc and an auxiliary capacitor Cs are connected to the drain electrode of the TFT 29 to form a display pixel.

  The scanning line driving circuit SD includes a shift register 25 and a scanning line driving buffer 26, and each buffer output is supplied to each scanning line. As these inputs, a basic clock CLK2 and a trigger signal IN2 are required.

  The video signal driving circuit VD includes DACs 10A to 10C, a shift register 31, a video signal line 32, a sampling switch control line 33, and a sampling switch 34. The configuration of the DACs 10A to 10C can be the same as that described above with reference to FIGS. Further, a shift register 21 and a sampling switch 24 (not shown) illustrated in FIG. 3 may be provided in the preceding stage of the DAC.

  Also in this modified example, the digital video signal serially input to the DAC from the outside is converted into an analog signal through the process described above with reference to FIGS. 1 to 14 and supplied to each video signal line 32.

  The analog video signal is written to the video signal line by controlling the sampling switch 34 by the shift register 31. In the configuration illustrated in the figure, each of m display pixels adjacent in the horizontal direction is divided into blocks, and a video signal is supplied to each block.

  FIG. 52 is a timing chart for explaining the operation principle of the video signal drive circuit VD. The operation will be described with reference to FIG. 51. First, the basic clock CLK1 and m-phase video signals (Video 1 to Video) synchronized therewith are input to the video signal line 32.

  Here, when a positive video signal is written to the pixel of the nth block, the control signal of the sampling switch 34 at the point b in FIG. 51 is in an OFF state at a timing corresponding to the nth block. To the ON state. Then, the sampling switch 34 changes from the non-conductive state to the conductive state, and the video signal input to the point a is supplied to the video signal line 27 via the video signal image 32. At this time, the potential of the video signal line 27 starts to rise from the initial potential Vm toward the predetermined potential Vs. Further, when the pixel TFT 29 is turned on, the potential at the point c in FIG. 51 also follows the potential of the video signal line 27.

  Subsequently, when the sampling switch 34 is turned off after the sampling period Tw, the video signal is held in the video signal line 27, the pixel capacitor Clc, and the auxiliary capacitor Cs, and the pixel potential is held at Vs for one horizontal period. .

  By scanning this operation in the horizontal direction for every m pixels while synchronizing with the basic clock CLK1, video signals are written to all the pixels within one frame period, and an image is displayed.

  Also in this modification example, as described above with reference to FIGS. 1 to 14, by using a very simple DAC, it is possible to reduce the circuit scale and to process digital data having a different number of bits. An effect can be obtained.

  In FIG. 52, the voltage represented by “ΔVw” is called “write undervoltage”, and the potential is written before the potential of the video signal line 27 on the terminal side of the video signal line 32 reaches a desired potential. Caused by This is because of the increase in the resistance and capacity of the video signal lines and video signal lines that accompany the increase in the screen size of the liquid crystal display device, the increase in the delay of the video signal transmission system, and the increase in the video signal frequency accompanying the increase in definition. This is because the sampling time is shortened by the increase. Such “writing undervoltage” may cause deterioration in image quality such as a decrease in display contrast.

  The S / H type drive circuit of this modification is inferior to the above-described line sequential method in that “writing undervoltage” is likely to occur, but on the other hand, since sequential scanning is performed for every m pixel blocks, line sequential scanning is performed. Compared with a driving circuit of the type, the circuit scale is small, and there are advantages that only the basic clock CLK1, the trigger signal IN1, and the m-phase video signal are necessary for the operation.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.

For example, in the DAC illustrated in FIGS. 5 to 9, the number of capacitors provided on the primary side or the secondary side can be changed as appropriate according to the number of bits of input data, the number of signal lines, and the like. The application of the drive circuit of the invention is not limited to the case of a liquid crystal display device, and can be similarly applied to various display devices such as an electroluminescence display device and a fluorescent light emitting display device. That is, the same effect can be obtained by applying the present invention in the same manner to all display devices in which pixels are arranged in a matrix and an analog video signal voltage is sequentially supplied to each pixel.

FIG. 1 is a conceptual diagram showing a digital-to-analog converter circuit (DAC) used in a video signal driving circuit that has been prototyped in the course of reaching the present invention. It is a conceptual diagram showing the digital-analog converting circuit (DAC) used in the video signal drive circuit concerning embodiment of this invention. 2 is a timing chart showing operation waveforms of the DAC of FIG. 1. It is a conceptual diagram which illustrates the principal part schematic structure of the liquid crystal display device carrying DAC. FIG. 2 is a configuration diagram conceptually showing a configuration of a serial DAC exemplified in FIG. 1. It is a conceptual diagram showing the basic composition of the 1st serial DAC concerning this invention. 6 is a timing chart for explaining the operation of the serial DAC of FIG. 5. It is a conceptual diagram showing the basic composition of the 2nd DAC concerning this invention. 8 is a timing chart for explaining the operation of the DAC of FIG. It is a conceptual diagram showing the basic composition of the 2nd DAC concerning this invention. 10 is a timing chart for explaining the operation of the DAC of FIG. 9. FIG. 10 is a schematic circuit diagram in which the serial DAC illustrated in FIGS. 1 to 9 is further simplified and modified. It is a schematic circuit diagram showing the 2nd modification of suitable DAC used for the drive circuit of this invention. It is a schematic circuit diagram showing the 3rd modification of suitable DAC used for the drive circuit of this invention. It is a conceptual diagram for demonstrating the effect of "error diffusion". It is the schematic showing the principal part of the video signal line drive circuit concerning one Embodiment of this invention. 16 is a timing chart showing operation waveforms in the circuit of FIG. It is a circuit diagram showing a conceptual configuration of a video signal output circuit 50B suitable for use in the present invention. 6 is a timing chart for explaining the operation of the output circuit 50B. It is a schematic circuit diagram showing the modification of the output circuit 50B. It is a graph showing the relationship between the input potential IN− of the input comparison circuit ID and the output nd. It is a schematic circuit diagram showing the 2nd modification of output circuit 50B. It is a graph showing the relationship between the input and output of the input comparison circuit ID of the output circuit 50D. It is a schematic circuit diagram showing the 3rd modification of output circuit 50B. It is a graph showing the relationship between the input and output of the input comparison circuit ID of the output circuits 50E to 50G. It is a schematic circuit diagram showing the 4th modification of the output circuit 50B. It is a schematic circuit diagram showing the 5th modification of the output circuit 50B. It is a circuit diagram showing the output circuit 50J for negative polarity which can be used in this invention. FIG. 28 is a timing chart of each part of the output circuit 50J of FIG. It is a circuit diagram which shows the detailed structure of the output circuit 50K for positive polarity. It is a circuit diagram of the output circuit 50L. It is a timing diagram of each part in the output circuit 50L. FIG. 31 is a schematic circuit diagram illustrating a modification of the output circuit 50L illustrated in FIG. 30. It is a schematic circuit diagram showing the connection part of serial type DAC mentioned above regarding FIGS. 1-14, and the output circuits 50J-50M mentioned above regarding FIGS. It is a timing chart showing operation | movement of each part in FIG. It is a schematic circuit diagram showing another specific example of the connection part of serial type DAC and the output circuits 50J-50M. It is a timing chart showing operation | movement of each part in FIG. 1 is a circuit block diagram of a multi-tone display device according to an embodiment of the present invention. FIG. 38 is a circuit block diagram illustrating a video signal driving circuit of the multi-gradation display device illustrated in FIG. 37. FIG. 39 is a timing chart showing the operation of the video signal driving circuit of FIG. 38. FIG. It is a conceptual diagram for demonstrating the output order of the digital video data from the gate array GA. FIGS. 41A and 41B are conceptual diagrams for explaining a modified example of the video signal line driving circuit according to the present invention, in which FIG. 41A corresponds to the basic form shown in FIG. 38 and FIG. 41B corresponds to the modified example. It is a conceptual diagram corresponding to the modification of the video signal line drive circuit by this invention. FIG. 4A shows a block configuration of a double speed operation shift register, and FIG. 4B shows a schematic circuit thereof. FIG. 4A shows a block configuration of a double speed operation shift register, and FIG. 4B shows a schematic circuit thereof. It is a block diagram showing the Example of the video signal line drive circuit by this invention. It is a timing chart showing the specific example of operation | movement of the display apparatus of a present Example. 3 is a conceptual diagram illustrating a modification example of a shift register 21. FIG. 48 is a timing chart illustrating operation of the shift register illustrated in FIG. 47. FIG. 7 is a schematic diagram for explaining a driving circuit of a liquid crystal display device to which a gamma correction circuit is added, in which FIG. (A) is a timing chart of a gate array for supplying a signal to the driving circuit having a six-signal line selection configuration; (b) is a conceptual diagram of a drive circuit with a 6-signal line selection configuration, (c) is a timing chart of a gate array for supplying a signal to the drive circuit with an 8-signal line selection configuration, and (d) is an 8-signal line selection. It is a conceptual diagram of the drive circuit of a structure. It is a block diagram showing the more detailed specific example of the drive circuit of 6 signal line selection structure. 1 is a schematic diagram showing a driving circuit of a “block sequential scanning type” sample-and-hold type (hereinafter abbreviated as S / H type) liquid crystal display device. FIG. 52 is a timing chart for explaining the operation principle of the video signal drive circuit VD of FIG. 51. FIG. It is a conceptual diagram showing the structure of the capacity | capacitance array type DAC used in the conventional liquid crystal display device.

Explanation of symbols

10, 10A-10C DAC
DESCRIPTION OF SYMBOLS 11 Switch selection circuit 19 Buffer amplifier 20 Image display part 21, 31 Shift register 24, 34 Sampling switch 27 Video signal line 28 Scan line 29 Pixel TFT
32 Video signal line 33 Sampling switch control lines 50A to 50M Output circuit (amplifier circuit)
80 Gamma correction circuit VD Video signal drive circuit SD Scan line drive circuit Clc Liquid crystal capacitance Cs Auxiliary capacitance

Claims (13)

A plurality of signal lines and scanning lines arranged orthogonally to each other, and pixel switching elements respectively provided at intersections of the signal lines and the scanning lines, and 2 based on m-bit data (m is a plurality) Drive circuit for a display device that performs gradation display of the power of m,
A data distribution circuit to which the m-bit data is supplied;
A data latch circuit for sequentially storing the m-bit data and outputting it at a predetermined timing;
A gamma correction circuit for storing an output from the data latch circuit and outputting the output at a predetermined timing;
A digital-to-analog converter that stores the output from the gamma correction circuit and outputs the output at a predetermined timing;
In an amplifier circuit that amplifies the output from the digital-analog converter circuit, and a drive circuit for a display device,
The amplifier circuit is an amplifier circuit that inputs an analog video signal supplied from the digital-analog converter circuit and outputs a video display signal to an output line,
An input comparison circuit that inputs the analog video signal and the video display signal and uniquely determines an output voltage according to a voltage difference between them;
A first amplifier circuit for inputting the output voltage and determining a logic output having a logic level corresponding to the output voltage;
A current source that inputs the first logic output and outputs a current to the output line as the display signal according to the logic output;
An output circuit having,
The input comparison circuit has a current circuit composed of a first transistor and a second transistor connected in series between a first power supply and a second power supply,
Either the analog video signal or the video display signal is selectively input to the gate of either the first or the second transistor,
A drive circuit for a display device, wherein the output voltage is output from a connection point between the first transistor and the second transistor . The input comparison circuit includes a transistor,
The display device driving circuit according to claim 1, wherein the analog video signal is input to a gate of the transistor. A second amplifier circuit for inputting the output voltage and determining a logic output having a logic level corresponding to the output voltage;
The current source outputs a current to the output line according to the logic output from the first amplifier circuit, and discharges the output line according to the logic output from the second amplifier circuit. The drive circuit for a display device according to claim 1, wherein the drive circuit is a display device.   3. The display device drive circuit according to claim 2, wherein an input capacity of the amplifier circuit is 10% or less of an output capacity of the digital-analog converter circuit.   The drive circuit for a display device according to claim 1, wherein the common electrode potential is different for each predetermined period. A drive circuit for a display device according to any one of claims 1 to 5;
Liquid crystal controlled by the pixel switching element;
With
A display device characterized in that an operating threshold value of the liquid crystal is 2.5 volts. A drive circuit for a display device according to any one of claims 1 to 5;
Liquid crystal controlled by the pixel switching element;
With
A display device characterized in that an operating threshold value of the liquid crystal is 1.5 volts. A drive circuit for a display device according to any one of claims 1 to 5;
A light source provided on the back side as viewed from the image observation surface;
With
A transmissive display device. A drive circuit for a display device according to any one of claims 1 to 5;
A reflector provided on the back side as viewed from the image observation surface;
With
A reflective display device that displays an image by reflecting external light incident from the image observation surface side by the reflector. A drive circuit for a display device according to any one of claims 1 to 5;
A light source provided on the back side as viewed from the image observation surface;
A reflector provided on the back side as viewed from the image observation surface;
With
A display device that displays an image by transmitting light emitted from the light source or reflecting external light incident from the image observation surface side by the reflector. A drive circuit for a display device according to any one of claims 1 to 5;
A pixel switching element provided for each display pixel;
With
The display device, wherein the driving circuit and the pixel switching element include the same semiconductor layer provided on the same substrate and deposited on the substrate. A drive circuit for a display device according to any one of claims 1 to 5,
A pixel switching element provided for each display pixel,
The driving circuit and the pixel switching element are provided on the same substrate and include the same semiconductor layer deposited on the substrate, and the light emission luminance is changed according to an analog voltage written to the pixel. A display device that performs display.   The error diffusion means for diffusing an error of the plurality of capacitors by sharing a plurality of capacitors provided corresponding to the plurality of signal lines by the plurality of signal lines is provided. The display apparatus as described in any one.

Images