JP3368819B2 - LCD drive circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit of a matrix type liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal drive circuit which is composed of a semiconductor integrated circuit and applies a video signal to a liquid crystal display device has been manufactured by using a high breakdown voltage diffusion process with a breakdown voltage of 10 V or more. This is based on the voltage of the common electrode of the liquid crystal to prevent deterioration of the liquid crystal when driving the liquid crystal .
This is because it is necessary to alternately apply the negative voltage and the negative voltage to the data line for AC driving.

FIG. 11 shows an example of a conventional liquid crystal drive circuit disclosed in Japanese Patent Laid-Open No. 63-304229. Figure 1
1, the liquid crystal drive circuit is configured by a semiconductor integrated circuit, and includes a shift register circuit group 21, a data register circuit group 22 that latches n-bit video data in parallel, and data of the data register circuit group 22. Data latch circuit group 23 for latching the data with a latch signal, a decoder 24 for selecting a 2 ^n- value gradation voltage input from the outside by n-bit video data, a level shift circuit group 25, and 2 ⁿ analog And a switch 26. Each of the output terminals selects one value from the 2 ^n- value gradation voltages by an analog switch and applies a predetermined voltage to the liquid crystal. To perform AC driving, the gradation voltage input from the outside is changed for each line or frame.

As described above, the liquid crystal drive circuit uses the voltage of the common electrode of the liquid crystal as a reference to write positive and negative voltages to the data line.
Since it is alternately applied to the liquid crystal, a withstand voltage that is at least twice the threshold voltage of the liquid crystal is required. Specifically, since the threshold voltage of the liquid crystal is usually about 4 to 5V, the liquid crystal drive circuit is manufactured by using a diffusion process having a high withstand voltage of 10V or more in order to perform AC driving.

[0005]

SUMMARY OF THE INVENTION Including the above-mentioned example,
The conventional liquid crystal drive circuit has the following problems.

The first problem is that the chip size is large when the semiconductor integrated circuit is used. This is because the number of analog switches increases as the number of gradations increases. For example, in case of 8 bits, each output has 256
Requires analog switches. Further, the load on the liquid crystal data line is increased (100 pF or more) due to the increase in size and definition of the liquid crystal panel, and the liquid crystal writing time is shortened (6
In VGA of 40 × 480 pixels, one horizontal period is about 30 μs
ec is about 16 μs for 1028 × 768 pixel XGA
It is necessary to lower the on-resistance of the switch due to (shortening to ec), and for this reason the transistor size is increased.

The second problem is high power consumption. This is because one output requires n level shift circuits, and the current consumption there becomes extremely large. Usually, the level shift circuit has a disadvantage that the operation speed is slower than that of other logic circuits and the transient current becomes very large. For example, if the number of output terminals of the driving IC is 384 and 256 gradations (8 bits), a transient current of about 1 mA flows in one level shift circuit, and therefore a maximum of 3
A transient current of 84 × 8 × 1 mA = 3.72 A will flow, and if the wiring resistance is high, the voltage drop will be large and the operation will be hindered.

An object of the present invention is to provide a liquid crystal drive circuit which can be formed by a semiconductor integrated circuit having a small chip size.

Another object of the present invention is to provide a liquid crystal drive circuit which has a simple structure, can be miniaturized, and can be integrated with low power consumption.

[0010]

A liquid crystal drive circuit of the present invention selects a first reference voltage and a second reference voltage from a plurality of gray scale voltages according to video data, and forms a pair of first and second reference voltages. And the third reference voltage are input to one input terminal, the output terminal and the other input terminal are connected by the first capacitance means, and one terminal of the second capacitance means is connected to the other. A first operational amplifier connected to the input terminal of
A fourth reference voltage having a voltage value different from that of the third reference voltage is input to one input terminal, the output terminal and the other input terminal are connected by the third capacitance means, and one of the fourth capacitance means is connected. A second operational amplifier whose terminal is connected to the other input terminal; and the first reference voltage and the second reference voltage output from the first and second gradation selection circuits, respectively. Input selection means for selectively inputting to the other terminal of the second capacitance means and the other terminal of the fourth capacitance means, an output from the first operational amplifier, and an output from the second operational amplifier. includes a switch means for outputting an output selectively, has an output selection circuit for outputting from the output terminal alternately output from the first and second operational amplifier by the switch means, said first and second 2 operational amplifier gain
Is greater than 1 and the outputs from the first and second operational amplifiers are positive and negative output voltages having a positive and negative amplitude relationship with each other with respect to the voltage of the common electrode of the liquid crystal display device. which outputs an output alternately to the data lines of the liquid crystal display device, for AC driving the liquid crystal display device
Is.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A liquid crystal drive circuit according to an embodiment of the present invention will be described below with reference to the drawings .

[0012] Figure 1 is a schematic diagram showing the entire of the liquid crystal driving circuit according to an embodiment of the present invention. FIG. 2 is a schematic circuit diagram showing a main part of a reference example of the present liquid crystal drive circuit. Figure 3
FIG. 6 is a timing chart for explaining the operation of the present liquid crystal drive circuit. The main part of the liquid crystal drive circuit of the present invention will be described later.
This is shown in the schematic circuit diagram of FIG. Figure in the following description
This will be described with reference to the second reference example.

Referring to FIG. 1, the liquid crystal drive circuit according to the present embodiment comprises a shift register circuit 10, a data register circuit 11 for latching video data in parallel, and a data latch for collectively latching the video data. A circuit 12, a decoder circuit 13, a gradation selection circuit 14, a switched capacitor circuit 15 including an output amplifier, and an output selection circuit 1
6, a gradation voltage generation circuit 17, and a timing control circuit 1
8, a data buffer circuit 19, a liquid crystal panel 27 which is a liquid crystal display device, and a vertical scanning circuit 28.

The voltage supplied to each circuit is as follows. The low-side voltage VSS1 of all circuits is VSS1 = VSS2 = 0
V. The shift register circuit 10, the data register circuit 11, the data latch circuit 12, the decoder circuit 13, the data buffer circuit 19, the timing control circuit 18, a part of the switched capacitor circuit 15, and the high-order side voltage of the gradation voltage generation circuit 17. VDD1 is set to VDD1 = 3.0V. The voltage VDD2 on the high side of the operational amplifier and output selection circuit 16 is VDD2 = 10V. In addition, the liquid crystal display device 2
7 common electrode voltage VCOM = 5V. However, each voltage described above is merely an example, and it goes without saying that another voltage may be used.

Next, the operation of the present liquid crystal drive circuit will be described with reference to FIGS. 1 to 3 by taking the case where the video signal is 8 bits as an example.

When the start pulse signal SPR or SPL is input to the shift register circuit 10, the video signals D1 to Dm are sequentially output from the data register circuit 1 by the shift register circuit 10 in synchronization with the clock signal.
It is transferred and held in 1. The held data is transferred and held in the data latch circuit 12 at the rising edge of the latch signal STB to the timing control circuit 18 (FIG. 3), and transferred to the decoder circuit 13 in the next stage. For this data, the upper 5 bits of the 8-bit video signal are selected by the gradation selection circuit 14 shown in FIG.
5 becomes the upper reference voltage and the lower reference voltage. Also, the bottom 3
For the bit, one value is selected from the eight voltage values by the switched capacitor circuit 15, and at the fall of the latch signal STB to the timing control circuit 18, the output terminal Y1,
Y2, ... de of a liquid crystal display device (not shown) from Y2n-1, Y2n
A predetermined voltage is applied to the data line.

Next, the structure and operation of the present liquid crystal drive circuit will be described in more detail.

FIG. 4 is a circuit diagram showing a detailed structure of the gradation voltage generating circuit 17. The gradation voltage generating circuit 17 is composed of a resistor string circuit or the like, divides the liquid crystal reference voltages VR1 to VRk supplied from the outside by resistance division, and outputs V1 and V1.
.., V32 of 32 value gradation voltages are generated. In addition,
Although FIG. 4 shows an example in which two voltages of liquid crystal reference voltages VR1 and VRk are supplied, a plurality of kinds of voltages of reference voltages VR1 to VRk may be supplied to finely supply the divided voltage. In the case where the liquid crystal display device 27 to which the present liquid crystal drive circuit is applied is a TFT, with respect to the reference voltage value supplied from the outside of the grayscale voltage generation circuit 17, the amount of charge transfer when the TFT is turned off is in the TFT. It is preferable that the gradation voltage generating circuit 17 is configured by two systems and the liquid crystal reference voltage VRk supplied from the outside is made different between the positive side output and the negative side output because it varies depending on the input voltage. Although the gradation voltage generating circuit 17 requires relative accuracy, the relative accuracy when manufactured with a semiconductor has a capability of 16 bits or more, so that it can be easily realized with accuracy of 5 to 8 bits.

FIG. 5 is a circuit diagram showing a detailed structure of the gradation selection circuit 14, showing the contents of each block shown in the gradation selection circuit 14 of FIG. Gradation selection circuit 14a, 1
Each of 4b is composed of 32 switches (analog switches). The gradation selection circuit 14a receives the video signals D1 to D1 from the voltages V0 to V31 of the gradation voltage generation circuit 17.
One value is selected based on the data of the upper 5 bits of 8 bits in Dm and used as the upper reference voltage of the switched capacitor circuit 15. Similarly, the gradation selection circuit 14b selects one value from the voltages V1 to V32 of the gradation voltage generation circuit 17 based on the upper 5 bits of 8 bits of the video signals D1 to Dm, and selects one value under the switched capacitor circuit 15. Use as reference voltage. Here, due to the switch at the connection between the gradation selection circuits 14a and 14b and the switched capacitor circuit 15, there are a pair of parts of the gradation selection circuits 14a and 14b for each output, the upper reference voltage and the lower reference voltage, respectively. It is supplied as a reference voltage. At this time, the upper reference voltage is a reference when a positive voltage is applied to the liquid crystal panel 27, and the lower reference voltage is a reference when a negative voltage is applied. For example, if the upper reference voltages are V0, V1, V2, ..., V31, the lower reference voltages are selected to be V1, V2, V3 ,.

Next, the switched capacitor circuit 15 and the operational amplifiers AMP1 and AMP2 included therein will be described. When describing the switched capacitor circuit 15, reference will be made to FIGS.

The basic circuit configuration of each operational amplifier AMP1 and AMP2 in the switched capacitor circuit 15 is as follows.
This is as shown in FIG. In the circuit configuration shown in FIG. 6A, the relationship between the input voltage VIN and the output voltage VOUT is represented by the equations and graphs shown in FIGS. 6B and 6C. According to FIG. 2, corresponding to C2 of FIG. 6 (a), the switches corresponding to 3 bits from the decoder circuit 13 turn on / off the capacitances of 4C, 2C, C, and AMP1, AM.
The amplification degree of P2 changes. Operational amplifier AMP1, AMP
The capacitance of the capacitor between the two inputs and outputs will be described as C1.

The reference voltage value VIN of the switched capacitor circuit 15 is supplied from the gradation selection circuit 14 and the supplied high voltage is VDD1 = 3V, so that the range is VIN = 0 to 0.
It becomes 3V.

Common electrode voltage of liquid crystal display device VCOM = 5V
On the other hand, in order to output a positive voltage of 5 to 10 V, the capacitance ratio of the switched capacitor circuit 15 is set to C2 / C1 = 5 /
3. Set the non-inverting input voltage of the operational amplifier AMP1 to VREF1 =
By setting it to 3.75V, the target output voltage range can be obtained. At this time, similarly, the capacitance of the capacitor between the input and output of the operational amplifiers AMP1 and AMP2 is set to a value of 8 (5/3) C. The capacitance of the input terminals of the operational amplifiers AMP1 and AMP2 at the right end in FIG. 2 is the timing control start, for example, when the output of the decoder 13 is “000”.
The connection relationship is as shown in, and the lower reference voltage has a capacity of 7C +
C is applied to the input terminal of AMP1. When the output of the decoder 13 is "111", the upper reference voltage is
The capacitance 7C + C is applied to the input terminal of AMP1.

On the other hand, in order to output the negative voltage of 0 V to 5 V, C2 / C1 = 5/3 and the non-inverting input voltage of the operational amplifier AMP2 may be set to VREF2 = 1.875V.

Further, when VDD2 = 8V and VCOM = 4V, by setting VIN = 0 to 2.4V and VREF1 = 3.0V, a positive side output of 4 to 8V is obtained and VIN = 0 to 2. Four
V and VREF2 = 1.5V, negative side output 0-4V
Is obtained.

As described above, since the non-inverting input voltages VREF1 and VREF2 of the operational amplifier and the liquid crystal reference voltages VR1 to VRn can be externally controlled, the positive and negative output voltage ranges for driving the liquid crystal display device can be easily controlled. You can
The absolute accuracy of the reference voltage of the operational amplifier may be about 8 + 1 bits, which can be realized by a commercially available DC-DC converter.

Next, the operation of the present liquid crystal drive circuit will be described with reference to FIGS.

When the latch signal STB, which is an input signal to the timing control circuit 18, is in the H state, the switch of the output selection circuit 16 and the switch between the gradation selection circuits 14a and 14b and the switched capacitor circuit 15 are in the OFF state (Hi. −
z). At this time, the switch between the inverting input terminal and the output of the operational amplifier of the switched capacitor circuit 15 is turned on, and the odd output is reset to the non-inverting input voltage VREF1 and the even output is reset to VREF2.

When the polarity signal POL is H, the latch signal STB
Is switched to L (low), the gradation selection circuits 14a, 1
The voltages selected by the upper 5 bits of the video signal in 4b are applied to the input section switches of the switched capacitor circuit 15 to become the upper reference voltage and the lower reference voltage, respectively, and the state of FIG. 2 is obtained. At this time, the switched capacitor circuit 15
Controls ON / OFF of the switches of the plurality of capacitors 4C, 2C, C, C connected to the inverting input terminal of the operational amplifier, and selects the lower 3 bits of data of the video signal,
Selects and outputs a voltage according to the digital data of the video signal. According to the video signal supplied from the data latch circuit 12 for the video signal, the switched capacitor circuit 1 is output from the decoder circuit 13 in accordance with the data of the lower 3 bits of the video signal.
By converting a plurality of decoders in 5 into, for example, four switch control signals, the capacitors 4C, 2C,
The on / off of the C and C switches is controlled to select the voltage according to the digital data of the video signal.

In FIG. 2, each decoder of the gradation selection circuit 14 is composed of enhancement type and depletion type FET arrays, as shown in FIG. 10A. Type and depletion type arrays are used as set values to obtain a desired output value. As an example, by using depletion type and enhanced type MOS transistors as 3 bits, an analog switch can have a decoder function. Therefore, the decoder circuit 13 can be omitted.
Although FIG. 10A shows an example of the N-type MOSFET array, a P-type MOSFET array can be similarly configured.

In FIG. 10A, the data latch circuit 12
3 bits LSB1 to LSB3 and their inversion signals are applied, and the gradation voltage generating circuit 17 is applied to the left input terminal.
VX1 to VX8 corresponding to the 32 output terminals are connected, and a predetermined output is obtained at the output Q thereof. For example, when LSB1 to LSB3 in FIG.
The value of VX1 is obtained at the output Q, and LSB1 to LSB3
When is "010", the value of VX3 is obtained at the output Q. In this way, the switches inside the gradation selection circuit 14 and the switched capacitor circuit 15 may be directly controlled.

Here, when the polarity signal POL supplied from the timing control circuit 18 is H, the output selection circuit 16
Is a positive voltage with reference to the liquid crystal common electrode voltage VCOM of the liquid crystal display device 27 from the operational amplifier AMP1 through an odd output terminal.
It operates to output the side voltage to the data line . From the operational amplifier AMP2, the liquid crystal
Data voltage of the negative voltage with reference to the electrode voltage VCOM
Output . On the other hand, when the polarity signal POL is L, a negative voltage is output to the data line from the operational amplifier AMP2 through the odd output terminal with reference to the liquid crystal common electrode voltage VCOM. From the operational amplifier AMP1, the voltage on the positive side with reference to the liquid crystal common electrode voltage VCOM is output through the even output terminal.
Output to the data line . In addition, from FIG. 3, the polarity signal POL
Is inverted to L and the output terminals of the operational amplifiers AMP1 and AMP2 maintain the previous state during the H period of the latch signal STB. In this manner, the two systems of operational amplifiers are shared by the two terminals, and switch control is performed so as to output positive and negative voltages in time series, whereby the liquid crystal display device is AC-driven.

7 and 8 show examples of internal configurations of the operational amplifiers AMP1 and AMP2 in FIG. 2 (indicated by arrows in the operational amplifier in FIG. 2). In FIG. 7, the operational amplifier includes differential input stages N-1 and N-2, and current mirrors P-1 and P-2 serving as loads on the differential input stages.
And an output stage P-3 that receives one output of the differential input stages N-1 and N-2, and a phase compensation capacitor CAMP1.
And current sources I0 and I1. Further, in FIG. 8, the operational amplifier is a differential input stage P-4, P-5.
And a current mirror N-3, which is a load of the differential input stage,
N-4, an output stage N-5 which receives the output of one of the differential input stages P-4 and P-5, and a phase compensation capacitor CAM.
It is composed of P2 and current sources I2 and I3.

In the present liquid crystal drive circuit, operational amplifiers of different types having different differential input stages are used. When the positive voltage is output to the data line with reference to the liquid crystal common electrode voltage VCOM, the differential input stage transistors N-1 and N-2 are set to Nch as shown in FIG. You can maximize the output. Also, with the liquid crystal common electrode voltage VCOM as a reference
Then, when the negative voltage is output to the data line , as shown in FIG. 8, the differential input stage transistors P-4 and P-5 are used.
By setting Pch to Pch, the maximum output can be made to the low potential side.
These two systems of operational amplifiers are shared by two terminals, and by performing switch control, the liquid crystal can be AC-driven with a wide dynamic range .

Next, a description will be given of a liquid crystal driving circuit according to an embodiment of the present invention.

[0036] Figure 9 is a schematic view showing a main part of a liquid crystal driving circuit according to an embodiment of the present invention. Referring to FIG. 9, the liquid crystal drive circuit according to the present embodiment is different from the embodiments and reference examples shown in FIGS. 1 and 2 in the configuration of gradation selection circuit 14 ′ and switched capacitor circuit 15 ′. . The gradation selection circuit 14 ′ has 8 bits of analog switches, that is, 256 analog switches for the 5-bit input shown in FIG. 2, and only one value is selected from the 256 values there, and the switched capacitor circuit 15 ′ is selected. And the reference voltage. The non-inverting input voltages VREF1, VREF2, etc. of the operational amplifier in the switched capacitor circuit 15 ′ may be the same voltages as in the first embodiment, but in the second embodiment they operate as so-called inverting amplifiers. In the switched capacitor circuit 15 ', the reference voltage from the gradation selection circuit 14' is switched to the switched capacitor by the circuit shown in FIG. A corresponding output voltage is obtained on the positive side and the negative side, and is output from the output selection circuit 16 to, for example, the odd-numbered and even-numbered signal lines of the liquid crystal panel 27.

The merit of this embodiment is that it has a monotonic increasing property. This is because there is no bit error in the switched capacitor circuit 15 'because the voltage is selected by the resistance strings circuit for all the video data. As a disadvantage, in the first embodiment, the number of switches is 64 × 2 (upper reference voltage, lower reference voltage) for each output and 12
In contrast to the eight chips, the second embodiment doubles the number to 256, which requires a large chip area. However, since the configuration of the switched capacitor circuit 15 ′ is simpler than that of the first embodiment, depending on the unit capacitance value (1C) in the switched capacitor circuit 15 ′, the same or similar chip as that of the first embodiment may be used. It is possible to reduce the area of.

[0038]

The liquid crystal drive circuit according to the present invention includes a switched capacitor circuit including a pair of operational amplifiers having different reference voltages, and an output which is output from a pair of output terminals by switch-controlling each output of the pair of operational amplifiers. With a selection circuit, liquid
The positive and negative output voltages having a positive and negative amplitude relationship with each other based on the voltage of the common electrode of the crystal display device are alternately output to the data line from the pair of output terminals of the output selection circuit, and the liquid crystal display is performed according to the image data. Since the device is AC-driven, the following effects are obtained.

Since the decoder circuit and the gradation selection circuit operate at a voltage of 3 V, they can be manufactured by a low breakdown voltage diffusion process,
Since the transistor can be small, the chip size can be small.

Since the level shift circuit is unnecessary, the size is small and the power consumption is lower than that of the conventional circuit. Particularly, since a large current does not transiently flow, the wiring width of the power supply wiring such as GND may be thin, and the chip size can be further reduced.

[Brief description of drawings]

It is a conceptual diagram showing a configuration of a liquid crystal driving circuit according to the embodiment of the present invention; FIG.

FIG. 2 is a schematic diagram showing a configuration of a main part of a reference example of the liquid crystal drive circuit shown in FIG.

FIG. 3 is a timing chart for explaining the operation of the liquid crystal drive circuit shown in FIG.

4 is a diagram showing a configuration of a grayscale voltage generation circuit in the liquid crystal drive circuit shown in FIG.

5 is a diagram showing a configuration of a gradation selection circuit in the liquid crystal drive circuit shown in FIG.

6A to 6C are diagrams for explaining the operation of the switched capacitor circuit in the liquid crystal drive circuit shown in FIG.

7 is a circuit diagram showing an internal configuration of an operational amplifier included in a switched capacitor circuit in the liquid crystal drive circuit shown in FIG.

8 is a circuit diagram showing an internal configuration of an operational amplifier included in a switched capacitor circuit in the liquid crystal drive circuit shown in FIG.

It is a schematic diagram showing the configuration of a main part of a liquid crystal driving circuit according to the embodiment of the present invention; FIG.

FIG. 10 is an explanatory diagram showing a circuit example and an operation example of the FET array according to the embodiment of the present invention.

FIG. 11 is a schematic diagram showing a configuration of a liquid crystal drive circuit according to a conventional example.

[Explanation of symbols]

10,21 Shift register circuit 11,22 Data register circuit 12,23 Data latch circuit 13, 24 Decoder circuit 14, 14 'gradation selection circuit 15,15 'switched capacitor circuit 16 Output selection circuit 17 Grayscale voltage generation circuit 18 Timing control circuit 19 Data buffer circuit 25 level shift circuit group 26 analog switches 27 LCD panel 28 Vertical scanning circuit

Claims (4)

(57) [Claims] 1. A first reference voltage and a second reference voltage are respectively selected from a plurality of gray scale voltages according to video data.
The first and second gradation selection circuits forming a pair, and the third reference voltage are input to one input terminal, the output terminal and the other input terminal are connected by the first capacitance means, and the second capacitance A first operational amplifier whose one terminal is connected to the other input terminal, and a fourth reference voltage having a voltage value different from the third reference voltage is input to one input terminal, and an output terminal A second operational amplifier having the other input terminal connected to the third capacitance means and one terminal of the fourth capacitance means connected to the other input terminal; and the first and second gradation selections. Input for selectively inputting the first reference voltage and the second reference voltage output from the circuit to the other terminal of the second capacitance means and the other terminal of the fourth capacitance means, respectively. Selecting means, output from the first operational amplifier and output from the second operational amplifier Includes a switch means for outputting a force selectively,
An output selection circuit for alternately outputting the outputs from the first and second operational amplifiers from the output terminal by the switch means, and the gains of the first and second operational amplifiers are greater than one.
In both cases, the outputs from the first and second operational amplifiers are
Positive and negative output voltages having a positive and negative amplitude relationship with each other with reference to the voltage of the common electrode of the liquid crystal display device, and outputting the output alternately to the data line of the liquid crystal display device,
A liquid crystal drive circuit, characterized in that the liquid crystal display device is driven by an alternating current. 2. When the video data is M bits,
2. The first and second grayscale selection circuits are each composed of 2M analog switches.
The liquid crystal drive circuit described in 1. 3. The first and second grayscale selection circuits output the predetermined number of divided voltages output from a grayscale voltage generating circuit that obtains a predetermined number of divided voltages by resistance division of a liquid crystal reference voltage. 1
The liquid crystal drive circuit according to claim 1 or 2, wherein a value is selected and output. 4. The liquid crystal according to claim 1, wherein the first and second gray scale selection circuits are composed of enhancement type and depletion type transistor arrays. Drive circuit.