KR101202981B1 - Source driver driving circuit for LCD - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a source driver driving circuit for a liquid crystal display device, and more particularly, to a source driver driving circuit for a liquid crystal display device, which reduces an area of a circuit portion and further reduces errors by precise driving.

To this end, the present invention comprises: a first converter for converting an input N-bit digital signal into an analog signal, and converting the digital signal into an analog signal for the upper M bits; By presenting a source driver driver circuit for a liquid crystal display device including a digital-analog converter having a second converter for converting the digital signal to the lower (NM) bit into an analog signal, Reduces the area of the digital-to-analog converter and reduces the size of the driver IC, maintains the gamma correction function, and reduces the error voltage due to accurate voltage addition to enable high gradation.

Description

Source driver driving circuit for LCDs

1 is a block diagram showing a basic configuration of a general liquid crystal display device

Fig. 2 is a view schematically showing the configuration of the liquid crystal panel in the configuration of Fig. 1

3 is a block diagram illustrating the structure and operation of a general source driver.

4 is a view for explaining an internal structure of a ROM-type D / A converter configured in a general source driver.

5 is a block diagram schematically illustrating the structure of a source driver employing a hybrid type D / A converter configured in a general source driver.

FIG. 6 is a block diagram showing the configuration of a D / A converter included in one channel constituting a source driver driving circuit for a liquid crystal display according to the present invention.

FIG. 7 is a block diagram illustrating in more detail a configuration of a D / A converter included in one channel of a source driver driving circuit for a liquid crystal display according to the present invention.

FIG. 8 is a circuit diagram illustrating a D / A converter of a source driver driving circuit for a liquid crystal display according to an exemplary embodiment of the present invention. In particular, a circuit diagram illustrating the second converter shown in FIGS. 6 to 7 is illustrated.

FIG. 9 is a diagram for explaining comparison of channel sizes and transconductances (gm) of a differential input stage configured in a voltage divider and an adder circuit and a differential input stage configured in an operational amplifier in a second converter circuit according to an exemplary embodiment of the present invention.

10A to 10D are circuit diagrams partially shown for explaining the operation of the second conversion unit according to the embodiment of the present invention, respectively.

11A to 11C are simulation output graphs respectively demonstrating the operation of the D / A converter of the source driver driving circuit for the liquid crystal display according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

100: D / A converter 110: the first converter

112: D / A converter 120: second conversion unit

122: voltage division and addition circuit 124: operational amplifier

SW_N, SW_P: switch

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit, and more particularly, to a source driver driving circuit for a liquid crystal display device which further reduces an output error by reducing an area of a circuit portion and driving precisely.

Among display devices, liquid crystal display devices have advantages of small size, thinness and low power consumption and are used in notebook computers, office automation devices, audio / video devices, and the like. In particular, an active matrix type liquid crystal display device using a thin film transistor (hereinafter referred to as "TFT") as a switching element is suitable for displaying dynamic images.

1 is a block diagram showing a basic configuration of a general liquid crystal display device, which is largely divided into a liquid crystal panel 2 and an LCM driving circuit portion 26. [

In each configuration, the interface 10 includes data (RGB Data) and control signals (input clock, horizontal synchronizing signal, vertical synchronizing signal, data enable) input to the LCM driving circuit unit 26 from a driving system such as a personal computer. Signals) and the like are supplied to the timing controller 12. LVDS (Low Voltage Differential Signal) interface and TTL interface are mainly used for data and control signal transmission from the drive system. In addition, the interface function may be collected and used together with the timing controller 12 in a single chip.

2, the liquid crystal panel 2 includes a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn intersecting each other on a substrate using a glass to form a plurality of pixel regions, A thin film transistor (TFT) and a liquid crystal (LC) are formed in the region to display a screen.

The timing controller 12 drives the source driver 18 of the plurality of drive integrated circuits and the gate driver 20 of the plurality of gate driver integrated circuits by using a control signal input through the interface 10. Generate a control signal for In addition, the data input through the interface 10 is transmitted to the source driver 18.

The reference voltage generator 16 generates reference voltages of a digital to analog converter (DAC) used in the source driver 18. The reference voltages are set by the manufacturer based on the transmittance-voltage characteristics of the panel.

The source driver 18 selects reference voltages of the input data in response to control signals input from the timing controller 12, and supplies the selected reference voltage to the liquid crystal panel 2 to control the rotation angle of the liquid crystal molecules. In addition, the source driver 18 may be configured in plural in the form of an IC chip, and may include the reference voltage generator 16 according to the type of chip.

The gate driver 20 performs on / off control of thin film transistors (TFTs) arranged on the liquid crystal panel 2 in response to control signals input from the timing controller 12. The gate driver 20 controls the gate on the liquid crystal panel 2. By sequentially enabling the lines GL1 to GLn by one horizontal synchronizing time, the thin film transistors TFT on the liquid crystal panel 2 are sequentially driven by one line, so that the analog image signals supplied from the source driver 18 It is applied to the pixels connected to the thin film transistors (TFTs). A plurality of gate drivers 20 may also be configured in the form of IC chips.

The power supply voltage generating unit 14 supplies the operating power of each of the components and generates and supplies the common electrode voltage of the liquid crystal panel 2.

The configuration and operation of the source driver 18 in the above configuration will be described in detail with reference to the drawings of FIG. 3.

The source driver 18 is generally composed of a shift register 18a, a sampling latch portion 18b, a holding latch portion 18c, a DAC 18d, and an output circuit portion 18e as shown.

The shift register 18a receives the start pulse signal SPin and the clock signal CLK from the timing controller 12. The shift register 18a receives a new start pulse signal SPout in the next stage in accordance with the clock signal CLK. Shift (output) sequentially into registers. At this time, the start pulse signal SP is a signal synchronized with video data RGB data.

Although not shown, the sampling latch unit 18b receives video data (RGB Data) temporarily stored in a storage such as a data latch memory and is divided in time by an output signal of each stage of the shift register 18a. Samples the transmitted RGB data and stores it. At this time, the video data (RGB Data) stored in the data latch memory is a digital video signal of 6 bits each of R, G, and B.

The video data sampled by the sampling latch unit 18b is stored in the holding latch unit 18c, and is input from the timing controller 12 when the video data of one horizontal period is input to the holding latch unit 18c. The latch is latched down by the latch signal LS. At this time, the holding latch 18c holds the video data for one horizontal period received until new video data (RGB Data) is input from the sampling latch 18b, and the data holding is performed. During the period of time, new video data of one horizontal period is inputted to the shift register 18a and the sampling latch unit 18b.

The video data output from the holding latch unit 18c is input to the D / A converter 18d, and the D / A converter 18d is provided with a plurality of reference voltages VGMAs generated by the reference voltage generator 16. Are converted into an analog voltage to be output to the liquid crystal panel 2 and output.

The analog video data output from the D / A converter 18d improves the current driving force at the output circuit unit 18e and inverts the data polarity for each pixel or line for each frame by the polarity control signal POL. . In this case, the data polarity inversion by the polarity control signal POL may be performed by the D / A converter 18d, and the output circuit unit 18e is usually configured using an operational amplifier OP-AMP.

The source driver 18 for outputting video data to the data lines DL1 to DLm of the liquid crystal panel 2 through the general configuration as described above is configured to convert each pixel from the input N-bit digital video data (Digital RGB data). In order to obtain analog video data (Analog RGB data) to be applied to the N-bit D / A converter (Digital to Analog Converter) is provided.

The D / A converter (DAC) is configured in each source driver, and a ROM-type resistive thermal D / A converter, which is easy to configure in a driver, is mainly adopted due to a simple structure.

FIG. 4 shows the internal structure of the ROM-type D / A converter. In particular, FIG. 4 is a simplified structure of a resistor string decoder constituting an N-bit decoder using a plurality of ROM-type switches.

The N switches (SW) switches a column (SW_1, SW_2, ..., SW_N ) having a dog, and is provided with a 2 ^N, to open said switch is increased 2-fold each time increasing the number of bits is 1, so the configuration in the source driver The area is also increased by 2 times. When the N-bit resistive string decoder of this structure is applied to the fabrication of high gray scale driver ICs, the size of the driver ICs increases due to the increase of the decoder area and the number of driver ICs produced per wafer for IC manufacturing decreases. Will cause an increase.

In order to improve the shortcomings of the D / A converter employing such a resistive string decoder, a proposed hybrid D / A converter (Hybrid-type DAC) combining the resistive string decoder and the capacitor type decoder is proposed.

FIG. 5 is a block diagram schematically illustrating the structure of a source driver 30 employing a hybrid D / A converter.

From the characteristics of the configuration, it can be seen that the D / A converter 34 for N-bit video data processing is composed of two types of D / A converters. The M-bit resistive string type D / A converter 34a and (NM ) -Bit capacitor type D / A converter 34b. In this case, N and M are natural numbers and have a relationship of N> M.

The M-bit resistive string D / A converter 34a performs decoding on the upper M-bits of the N-bit digital video data output from the holding latch unit 33 and the (NM). ) -Bit capacitor type D / A converter 34b is implemented to perform decoding on the remaining (NM) -bit digital video data.

The hybrid type D / A converter 34 having the above structure can reduce the size of the source driver due to the advantage that the number of switch rows is reduced compared to the ROM-type resistive-type D / A converter described above with reference to FIG. There is an advantage.

However, the switched capacitor logic of the internal capacitors of the (NM) -bit capacitor type D / A converter 34b has various characteristics due to the capacitor element, for example, channel charge injection, and charge. Due to charge feed through and mismatch between capacitors, it is difficult to accurately predict the output voltage.

In addition, the M-bit resistive thermal D / A converter 34a recognizes the (NM) -bit capacitor type D / A converter 34b as a capacitive load, causing a delay in driving. In order to improve this, since the switching transistors included in each of the resistance strings inside the M-bit resistive string type D / A converter 34a need to use a large-capacity transistor having a large channel size so that a driving delay does not occur, it is disposed at the front end. There is a limit in reducing the size of the M-bit resistive thermal D / A converter 34a.

In the above-described reality, the present invention is one method for implementing a display device with a miniaturization and thinning trend, and is advantageous for high gradation while further reducing the size of a driving circuit element, especially a source driver, and also compared to a conventional circuit. It is an object of the present invention to propose a source driver driving circuit which operates to enable further reduction of power consumption and accurate output prediction.

In order to achieve the above object, the present invention includes a first conversion unit for converting the input N-bit digital signal into an analog signal, for converting the digital signal from the upper M bit to an analog signal; A source driver driving circuit for a liquid crystal display device including a digital-to-analog converter having a second converter for converting the digital signal from a lower (N-M) bit into an analog signal is provided.

 In addition, the present invention is a driving circuit for receiving an N-bit digital signal and outputting it to the liquid crystal panel, the shift register for receiving and outputting the main clock signal; A latch unit configured to receive and latch the N-bit digital signal in response to the main clock signal; A first conversion unit for converting the upper M bits from the digital signal output from the latch unit into an analog signal, and a second conversion for converting the digital signal into the analog signal for the lower (NM) bits A digital-to-analog converter having a unit; The present invention proposes a source driver driving circuit for a liquid crystal display device including an output circuit unit for receiving the analog signal and determining and outputting the polarity of the signal to form one channel.

The first converter is a resistance string type digital-analog converter.

The second converter may include a voltage division and addition circuit having a plurality of differential input terminals, and an operational amplifier connected to the voltage division and addition circuit and receiving a first driving voltage and a second driving voltage. .

The voltage division and addition circuit may include a plurality of NMOS differential input terminals and a plurality of PMOS differential input terminals.

The plurality of NMOS differential input terminals and the plurality of PMOS differential input terminals are configured to have the same number.

The operational amplifier is characterized in that it is provided with one NMOS differential input terminal and one PMOS differential input terminal.

The transconductance of each differential input stage of the voltage division and addition circuit is smaller than the transconductance of the operational amplifier differential input stage.

The operational amplifier is characterized in that the operational amplifier having a single gain negative feedback connection.

The first driving voltage is a high level voltage, and the second driving voltage is a low level voltage.

Each of the plurality of differential input terminals of the voltage division and addition circuit may be configured to determine a circuit connection with the operational amplifier according to an input digital signal code.

N is a natural number larger than M.

Each of the differential input terminals configured in the voltage division and addition circuit and the operational amplifier receives one or more of the analog signals output from the first converter.

Each of the differential input stages of the voltage division and addition circuit receives two analog signals sequentially output from the first converter.

Hereinafter, with reference to the accompanying drawings will be described for the present invention and preferred embodiments thereof.

FIG. 6 is a block diagram illustrating a configuration of a digital-analog converter (hereinafter, referred to as a D / A converter) included in one channel of a source driver driving circuit for a liquid crystal display according to the present invention.

According to the present invention as described above, in order to cope with the trend of miniaturization, thinning, and high gradation of the liquid crystal display device, a conventional D / A converter, a capacitor type D / A converter, or a hybrid type D / A by the above combination In order to overcome the limitation of the area occupied by the converter in the circuit, a part of the D / A conversion part is replaced by a circuit having a relatively small configuration area. Thus, the D / A conversion part 100 has a first conversion. The unit 110 and the second conversion unit 120.

The first converter 110 performs an analog conversion on the upper M bits of the digital signal of the N-bit digitally coded digital signal, the second converter 120 is the upper M bits of the digital signal Performs conversion to analog signal for the lower (NM) bit except for. M is any natural number but M <N.

This configuration is illustrated in more detail in FIG. 7, which shows a preferred circuit configuration of the D / A converter 100 configured in each channel of the source driver driving circuit for displaying an image of the liquid crystal display proposed in the present invention. .

The first conversion unit 110 constitutes a conventional DAC (Conventional DAC) 112, and the second conversion unit 120 includes a voltage splitting and adding circuit ( 122) and the operational amplifier (124) is combined. At this time, the D / A converter 112 to the first converter 110 is a resistive thermal D / A converter.

In addition, the voltage division and addition circuit 122 includes a plurality of NMOS differential input stages and a plurality of PMOS differential input stages, and the operational amplifier 124 performs a single gain negative feedback amplification operation. Floating current source output stage and rail to rail input stage, which are widely used in IC, are preferably provided with NMOS differential input stage and PMOS differential input stage in the internal circuit. Here, each of the differential input stages of the voltage division and addition circuit 122 receives a gradation output continuously output from the first converter 110 and circuits the operational amplifier 124 according to the (NM) bit digital code. Enemy connection is determined.

As described above, when a part of the resistive thermal D / A converter having a large configuration area is replaced by a circuit having a relatively small configuration area, the size of the source driver circuit (or IC) can be reduced. When using the same circuit area as a conventional D / A converter, there is an advantage that the circuit can be configured to convert even a higher bit number digital signal (that is, a high gradation signal).

Hereinafter, a preferred embodiment of the present invention will be described.

FIG. 8 is a circuit diagram of a D / A converter 100 of a source driver driving circuit for a liquid crystal display according to an exemplary embodiment of the present invention. In particular, voltage division constituting the second converter 120 shown in FIGS. And a circuit diagram illustrating the addition circuit 122 and the operational amplifier 124. In the present embodiment, an example and operation of a specific circuit of the resistive string DAC applied to the first converter 110 shown in FIGS. 6 to 7 are omitted.

Referring to the circuit shown, the second conversion unit 120 for converting a digital signal into an analog signal is composed of a voltage division and addition circuit 122 and an operational amplifier 124 composed of a plurality of differential input stages. And the addition circuit 122 is an exemplary circuit in which a circuit is configured to be suitable for decoding of 2 bits of lower bits (that is, when NM = 2).

The differential input stage configured in the voltage division and addition circuit 122 includes a continuous gray level signal (DAC (n), DAC (n + 1): the first conversion unit (DAC (n), converted and output from the first conversion unit 110). A plurality of NMOS differential input stages (NMOS_1 to NMOS_3) and PMOS differential input terminals (PMOS_1 to PMOS_3) each composed of a pair of the same type transistors to receive the nth and n + 1th output gray voltages} of 110) are respectively configured. Different types of differential input stages have the same number, and for convenience of operation description, one NMOS differential input stage and a PMOS differential input stage corresponding to the configuration position and role thereof are grouped into one differential input pair and a plurality of differential input pairs (A , B, C). The number of configurations of the differential input pairs A, B, and C varies depending on the number of lower bit codes of the digital signal input from the second converter 120. In this embodiment, the DAC operation for the lower two bits is performed. Therefore, among the four code combinations of the 2-bit digital signal, the differential input pairs A, B, and C to be operated corresponding to three codes except for one code of the differential input pair provided to the operational amplifier 124 are divided in voltage. And an addition circuit 122.

In the present invention, each of the plurality of differential input stage has a switch (SW_N2, SW_N1, SW_N0, SW_P2, SW_P1, SW_P0) for controlling the circuit connection with the operational amplifier 124, each switch constitutes a differential input stage Each of the transistor pairs is configured to switch driving of the N-type transistor differential input stages (ie, switching control of SW_N2, SW_N1, SW_N0) or switching of driving of the P-type transistor differential input stages (ie , SW_P2, SW_P1, and SW_P0 should be controlled by a signal output from a separate configuration such as a timing controller. In the embodiment of the present invention, the respective switches (SW_N2, SW_N1, SW_N0, SW_P2, SW_P1) , A description of a separate configuration for the control of (SW_P0).

In addition, the switching signal of each of the switches SW_N2, SW_N1, SW_N0, SW_P2, SW_P1, SW_P0 is determined by the digital code of the lower (NM) bit input to the second converter 120. The switching operation of each differential input pair (A, B, C) is determined by the code combination of the bit digital signal, the codes 00, 01, 10, and 11.

The operational amplifier 124 is a commonly used operational amplifier having a single gain negative feedback connection for receiving a high level first driving voltage VDD and a low level second driving voltage VSS for driving. In this case, the differential input pair D composed of one NMOS differential input terminal NMOS_0 and one PMOS differential input terminal PMOS_0 in the operational amplifier 124 circuit is used for each differential input pair of the voltage division and addition circuit 122. In order to perform operations in the operational amplifier like A, B, and C, the switch has switches SW_N and SW_P for controlling the connection with the internal circuits of the operational amplifier 124. The selection of the switches SW_N and SW_P is performed by liquid crystal. It is selected according to the voltage level of the common voltage of the output signal Vout to be output to the panel.

As the most important element in configuring the second conversion unit 120 according to the embodiment of the present invention configured as described above, each of the differential input stages configured in the voltage division and addition circuit 122 and the operational amplifier 124 It is necessary to adjust the channel size {W / L: W (channel width), L (channel length)} for the constituent transistor. That is, this is related to the number of lower digital signal bits input to the second converter 120, which is an element that controls the number of differential input pairs configured in the voltage division and addition circuit 122, and also the determined differential. This is because the ratio of divided voltages must be adjusted according to the number of input pairs.

Accordingly, in the present embodiment, as shown in (a) and (b) of FIG. 9, only the signal conversion for the lower two bits is performed by the second converter 120, and the differential input pair D of the operational amplifier 124 is used. The transistor channel size of each differential input terminal constituting the differential input pair (A, B, C) of the voltage division and addition circuit 122 is assumed that the transistor channel size constituting each differential input terminal of? Is set to "1/4". Accordingly, the amount of steady state current of each of the differential input terminals NMOS_1 to NMOS_3 and PMOS_1 to PMOS_3 of the voltage division and addition circuit 122 is 1/4 of the current compared to the differential input terminals NMOS_0 and PMOS_0 in the operational amplifier 124. Will shed. Therefore, the transconductance (gm) of each of the differential input terminals NMOS_1 to NMOS_3 and PMOS_1 to PMOS_3 of the voltage division and addition circuit 122 is calculated as shown in Equations 1 and 2 below. This is 1/4 of the transconductance gm of the differential input terminals NMOS_0 and PMOS_0 of the amplifier 124.

....(식 1)

... (Equation 1)

..... (식 2)

..... (Equation 2)

That is, the continuous gray level signal voltages DAC (n) and DAC (s) which are converted by the first conversion unit 110 and input to the differential input pairs A, B, and C of the voltage division and addition circuit 122. n + 1)} voltage difference (hereinafter, V _LSB ) is divided into four, and each of the differential input _stages has a current difference of (1/4) × gm × 1 × V _LSB . Here, the V _LSB is a voltage difference {DAC (n + 1) -DAC (n)} between the continuous gray signal voltage DAC (n) and DAC (n + 1), which is a voltage level of the lowest gray level.

Hereinafter, an operation of the second converter 120 according to the present invention configured as described above will be described with reference to FIGS. 10A to 10D.

In the embodiment of the present invention, the NMOS and PMOS differential input terminals of the voltage division and addition circuit 122 are selected such that the NMOS differential input terminal is driven when the output signal Vout to be output to the liquid crystal panel needs to be higher than the common voltage VCOM. When the output signal Vout to be output to the liquid crystal panel needs to be lower than the common voltage VCOM, the switches SW_N2, SW_N1, SW_N0, SW_P2, SW_P1, and SW_P0 are selected to drive the PMOS differential input terminal. The same applies to the switches SW_N and SW_P of the differential input pair D in the operational amplifier 124. In order to select an NMOS or PMOS differential input terminal through a series of switch control as described above, it is to avoid the limitation of the input range according to the capacity of the operational amplifier 124 by each differential input terminal.

Each of the switches SW_N2, SW_N1, SW_N0, SW_P2, SW_P1, SW_P0 exemplifies a switching state according to an input 2-bit digital signal code. When the code of the input digital signal is "00", the operational amplifier 124 ) SW_N (when Vout is higher than VCOM) or SW_P (when Vout is lower than VCOM) is ON. ② SW_N and SW_N0 (when Vout is higher than VCOM) when the input digital signal code is "01". Or SW_P, SW_P0 (when Vout is lower than VCOM) is on and ③ SW_N, SW_N0, SW_N1 (when Vout is higher than VCOM) or SW_P, SW_P0, SW_P1 (when the input digital signal code is "10"). Vout is lower than VCOM) and ④ SW_N, SW_N0, SW_N1, SW_N2 (when Vout is higher than VCOM) or SW_P, SW_P0, SW_P1, SW_P2 (if Vout is higher than VCOM). Vout is lower than VCOM).

Accordingly, when the output signal Vout needs to be higher than the common voltage VCOM, operations of the input digital signal codes are illustrated in FIGS. 10A to 10D, respectively.

FIG. 10A illustrates the voltage division and addition circuit 122 when the output voltage of the first converter 110 is higher than the common voltage VCOM. Connection switching pattern with the operational amplifier 124 for B, C).

Referring to the circuit operation, only (SW_N) is turned on to operate as a differential input terminal to the operational amplifier 124, so that the output voltage (Vout) output to the data line of the liquid crystal panel is 1 times the input signal DAC ( n) is output as it is.

FIG. 10B illustrates a switching pattern of the voltage division and addition circuit 122 and the operational amplifier 124 when the code of the input digital signal is "01" when the output voltage Vout is higher than the common voltage VCOM. Referring to the circuit operation, (SW_N) and (SW_N0) are turned on to operate as a differential input terminal to the operational amplifier 124, so that the output voltage of the differential input terminal of the operational amplifier 124 and the DAC (n) Even if the same, the current of 1 / 4xgmx1xV _LSB flows further to the differential input terminal (i.e., in the AA direction) added by the on switching of the switch SW_N0. Accordingly, since the single gain negative feedback operational amplifier 124 outputs a single gain, an additional current of 1/4 × gm × 1 × V _LSB flows in the BB direction to offset the current difference. Increases (Vout) by 1/4 x V _LSB . Accordingly, the final output voltage Vout output to the data line is DAC (n) + 1/4 × V _LSB .

10C and 10D show calculations with the voltage division and addition circuit 122 when the input digital signal code is " 10 " and " 11 ", respectively, when the output voltage Vout is higher than the common voltage VCOM. The switching pattern of the amplifier 124.

According to the operation principle of the operational amplifier 124 as shown in FIG. 10B, the output voltage Vcom becomes DAC (n) + _2/4 × V _LSB and DAC (n) + 3/4 × V _LSB , respectively.

Up to now, the case where only the N-type differential input terminals are selected and operated because the output voltage Vout applied to the liquid crystal panel in the D / A converter of the source driver driving circuit according to the present invention is higher than the common voltage VCOM. However, in the D / A converter according to the present invention, when the output voltage Vout applied to the liquid crystal panel is lower than the common voltage VCOM, SW_N is off and SW_P is on. Only P-type differential inputs are selected. Accordingly, the SW_P0, SW_P1, and SW_P2 are driven on in the aforementioned manner, and the input digital codes of the (NM) bit digital signals input to the second converter 120 are "00", "01", " 10 "," 11 ", the final output voltage for each digital code input is DAC (n), DAC (n) -1 / 4 × V _LSB , DAC (n) -2 / 4 × V _LSB , DAC (n) -3/4 x V _LSB .

In addition, in the present invention, the V _LSB value is a value representing the DAC (n + 1) -DAC (n) value and is changed according to the digital value N rather than a fixed constant. Therefore, the D / A converter 100 according to the present invention can display a gamma curve by automatically resetting the added or subtracted voltage size according to the digital code N. FIG.

11A to 11C are simulation output graphs showing the operation of the D / A conversion unit 100 among the source driver driving circuits for the liquid crystal display according to the present invention proposed as described above, and FIG. 11A is an output output to the liquid crystal panel. The voltage Vout is 10V and 5V, respectively, based on the common voltage (7.5V), and FIG. 11B shows that the output voltage Vout output to the liquid crystal panel is 8V and 7V, respectively, based on the common voltage (7.5V). 11C illustrates a case where the output voltage Vout output to the liquid crystal panel is 14.5V and 0.5V based on the common voltage 7.5V, respectively.

 The experimental program used was tested using HSPICE which is widely used as an electric circuit simulation tool, and the experimental conditions are shown in Table 1 below.

line time 20㎲ (WXGA) load condition 20㏀, 90㎊ power supply voltage 15V (IPS mode) static current per one OP-AMP 15,16,17,18 ㎂ inversion type dot inversion added voltage 0V, 10㎷, 20㎷ and 30㎷

<Table 1>

The simulation output graph shown by the second converter 120 according to the present invention when the voltage input to the data line is required (10V, 5V), (8V, 7V), (14.5V, 0.5V). It shows the output, and in each case can be seen that the voltage of 10mV, 20mv, 30mv is added accurately over all the output DC level, it can be seen that the operation of the D / A converter 100 according to the present invention is very sophisticated. .

The biggest effect of the source driver driving circuit for the liquid crystal display according to the present invention as described above is to reduce the area occupied by the digital-to-analog converter in the liquid crystal display driving circuit to reduce the size of the driving IC and at the same time to accurately add voltage. There is an advantage to enable high gradation representation by reducing the error voltage.

Claims (26)

In order to convert the input N-bit digital signal into an analog signal, A first converter configured to convert the digital signal into an analog signal for upper M bits; A digital-to-analog converter having a second converter for converting the digital signal from the (N-M) bit to an analog signal, The second conversion unit, And a voltage dividing and adding circuit having a plurality of differential input terminals, and an operational amplifier connected to the voltage dividing and adding circuit and receiving a first driving voltage and a second driving voltage. Driving circuit The method according to claim 1, And the first converter is a resistive column type digital-analog converter. delete The method according to claim 1, The voltage dividing and adding circuit includes a plurality of NMOS differential input terminals and a plurality of PMOS differential input terminals. The method according to claim 4, The plurality of NMOS differential input terminals and the plurality of PMOS differential input terminals are configured to have the same number of source driver driving circuits for the liquid crystal display device. The method according to claim 1, The operational amplifier has a NMOS differential input terminal and a PMOS differential input terminal therein, the source driver driving circuit for the liquid crystal display device The method according to any one of claims 1, 2 and 4 to 6, The transconductance of each differential input stage of the voltage division and addition circuit is smaller than the transconductance of the operational amplifier differential input stage. The method according to claim 1, And the operational amplifier is an operational amplifier having a single gain negative feedback connection. The method according to claim 1, Wherein the first driving voltage is a high level voltage, and the second driving voltage is a low level voltage. The method according to claim 1, Each of the plurality of differential input terminals of the voltage division and addition circuit has a circuit connection determined with the operational amplifier according to an input digital signal code. The method according to claim 1, N is a natural number greater than M, the source driver driving circuit for the liquid crystal display device The method of claim 7, wherein The voltage dividing and adding circuit and each of the differential input terminals configured in the operational amplifier receive one or more of the analog signals output from the first converting unit. The method according to any one of claims 1 to 2, Each of the differential input terminals of the voltage division and addition circuit receives two analog signals sequentially output from the first conversion unit. As a driving circuit for receiving an N-bit digital signal and outputting it to a liquid crystal panel, A shift register configured to receive and output a main clock signal; A latch unit configured to receive and latch the N-bit digital signal in response to the main clock signal; A first conversion unit for converting the upper M bits from the digital signal output from the latch unit into an analog signal, and a second conversion for converting the digital signal into the analog signal for the lower (NM) bits A digital-to-analog converter having a unit; Output circuit unit for receiving the analog signal to determine the output polarity of the signal Form a channel, including The second conversion unit, And a voltage dividing and adding circuit having a plurality of differential input terminals, and an operational amplifier connected to the voltage dividing and adding circuit and receiving a first driving voltage and a second driving voltage. Driving circuit The method of claim 14, And the first converter is a resistive column type digital-analog converter. delete The method of claim 14, The voltage dividing and adding circuit includes a plurality of NMOS differential input terminals and a plurality of PMOS differential input terminals. The method according to claim 17, The plurality of NMOS differential input terminals and the plurality of PMOS differential input terminals are configured to have the same number of source driver driving circuits for the liquid crystal display device. The method of claim 14, The operational amplifier has a NMOS differential input terminal and a PMOS differential input terminal therein, the source driver driving circuit for the liquid crystal display device The method according to any one of claims 14, 15 and 17-19, The transconductance of each differential input stage of the voltage division and addition circuit is smaller than the transconductance of the operational amplifier differential input stage. The method of claim 14, And the operational amplifier is an operational amplifier having a single gain negative feedback connection. The method of claim 14, Wherein the first driving voltage is a high level voltage, and the second driving voltage is a low level voltage. The method of claim 14, Each of the plurality of differential input terminals of the voltage division and addition circuit has a circuit connection determined with the operational amplifier according to an input digital signal code. The method of claim 14, N is a natural number greater than M, the source driver driving circuit for the liquid crystal display device The method of claim 20, The voltage dividing and adding circuit and each of the differential input terminals configured in the operational amplifier receive one or more of the analog signals output from the first converting unit. The method according to any one of claims 14 to 15, Each of the differential input terminals of the voltage division and addition circuit receives two analog signals sequentially output from the first conversion unit.

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