JPH10260664A - Liquid crystal driving circuit and liquid crystal device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal driving circuit which can be constituted with a semiconductor integrated circuit small in chip size and low in power consumption. SOLUTION: This device has a switched capacitor circuit 15 including a couple of operational amplifiers AMP1 and AMP2 having mutually different reference voltages and an output selecting circuit 16 which outputs the outputs of the operational amplifiers AMP1 and AMP2 from a couple of output terminals under switch control. A positive and a negative output voltage having mutually positive/negative amplitude relation based upon a voltage a half as high as a liquid crystal driving voltage or the voltage of the common electrode of the liquid crystal display device are outputted alternately from a couple of output terminals of the output selecting circuit 16 to the common electrode of the liquid crystal display device, which is driven on an AC basis according to video data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit of a matrix type liquid crystal display device and a device therefor.

[0002]

2. Description of the Related Art A liquid crystal drive circuit which is constituted by a semiconductor integrated circuit and applies a video signal to a liquid crystal display device has conventionally been manufactured by using a high withstand voltage diffusion process with a withstand voltage of 10 V or more. This is because, when driving the liquid crystal, in order to prevent the deterioration of the liquid crystal, it is necessary to alternately apply a positive voltage and a negative voltage to the common electrode of the liquid crystal to perform AC driving.

FIG. 11 shows an example of a conventional liquid crystal driving circuit disclosed in Japanese Patent Application Laid-Open No. 63-304229. FIG.
1, this liquid crystal drive circuit is formed of a semiconductor integrated circuit, and includes a shift register circuit group 21, a data register circuit group 22 for latching n-bit video data in parallel, and a data register circuit group 22. , A decoder 24 for selecting a 2 ⁿ -valued gray scale voltage externally input by n-bit video data, a level shift circuit group 25, and 2 ⁿ analog circuits. And a switch 26. Each output terminal selects one value from 2 ⁿ -valued gradation voltages by an analog switch, and applies a predetermined voltage to the liquid crystal. For AC driving, the gray scale voltage input from the outside is changed for each line or each frame.

As described above, the liquid crystal driving circuit alternately applies positive and negative voltages to the common electrode of the liquid crystal, and thus requires a withstand voltage of at least twice the threshold voltage of the liquid crystal. Specifically, since the threshold voltage of the liquid crystal is usually about 4 to 5 V, the liquid crystal drive circuit has been manufactured by using a diffusion process with a high withstand voltage of 10 V or more for AC driving.

[0005]

SUMMARY OF THE INVENTION Including the above example,
The conventional liquid crystal driving circuit has the following problems. A first problem is that the chip size is large when configured with a semiconductor integrated circuit. This is because the number of analog switches increases as the number of gradations increases. For example, in the case of 8 bits, each output requires 256 analog switches. In addition, the load on the liquid crystal data line increases due to the increase in the size and definition of the liquid crystal panel (100p).
F or more) and shortening of the liquid crystal writing time (640 × 480)
In the VGA of the pixel, one horizontal period is about 30 μsec.
In the case of a 028 × 768 pixel XGA, it is shortened to about 16 μsec), so that it is necessary to lower the on-resistance of the switch, and to increase the transistor size.

A second problem is that power consumption is high. This is because one output requires n level shift circuits, and the current consumption there becomes very large. Normally, the level shift circuit has a drawback that the operation speed is slower than other logic circuits and the transient current is extremely large. For example, if the number of output terminals of the driving IC is 384 and 256 gradations (8 bits), a transient current of about 1 mA flows through one level shift circuit.
A transient current of 84.times.8.times.1 mA = 3.72 A flows. If the wiring resistance is high, the voltage drop increases, which hinders the operation.

An object of the present invention is to provide a liquid crystal driving circuit which can be constituted by a semiconductor integrated circuit having a small chip size.

Another object of the present invention is to provide a liquid crystal drive circuit which can be miniaturized with a simple structure and which can be integrated and has low power consumption.

[0009]

According to the present invention, there is provided a switched capacitor circuit including a pair of operational amplifiers having different reference voltages from each other, and each output of the pair of operational amplifiers is controlled by switching the output terminals of the pair. An output selection circuit for outputting positive and negative output voltages having a positive / negative amplitude relationship with each other based on a half of the liquid crystal drive voltage from a pair of output terminals of the output selection circuit. A liquid crystal driving circuit and a liquid crystal device, which alternately output to the common electrode and drive the liquid crystal display device in accordance with the video data.

According to the present invention, there is further provided a switched capacitor circuit including a pair of operational amplifiers having different reference voltages, and an output selection circuit for controlling each output of the pair of operational amplifiers and outputting the output from a pair of output terminals. And a positive and negative output voltage having a positive and negative amplitude relationship with respect to each other with respect to the voltage of the common electrode of the liquid crystal display device from the pair of output terminals of the output selection circuit to the common electrode of the liquid crystal display device. A liquid crystal drive circuit and a liquid crystal device are provided, which alternately output a liquid crystal display device and alternately drive the liquid crystal display device according to video data. According to the present invention, the gray scale selection circuit for selecting the gray scale voltage according to the video data and outputting the selected gray scale voltage to the switched capacitor circuit includes analog switches for the number of gray scales. The liquid crystal drive circuit is characterized in that a voltage is used as a reference voltage for two operational amplifiers of the switched capacitor circuit.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a liquid crystal drive circuit according to an embodiment of the present invention will be described with reference to the drawings.

[First Embodiment] FIG. 1 is a schematic diagram showing an entire liquid crystal driving circuit according to a first embodiment of the present invention.
FIG. 2 is a schematic circuit diagram showing a main part of the present liquid crystal drive circuit. FIG. 3 is a timing chart for explaining the operation of the present liquid crystal drive circuit.

Referring to FIG. 1, a liquid crystal drive circuit according to the present embodiment includes a shift register circuit 10, a data register circuit 11 for latching video data in parallel, and a data latch for latching the video data collectively. Circuit 12, a decoder circuit 13, a gradation selection circuit 14, a switched capacitor circuit 15 including an output amplifier, and an output selection circuit 1.
6, the gradation voltage generation circuit 17, and the timing control circuit 1
8, a data buffer circuit 19, a liquid crystal panel 27 which is a liquid crystal display device, and a vertical scanning circuit 28.

The voltage supplied to each circuit is as follows. The lower voltage VSS1 of all circuits is VSS1 = VSS2 = 0.
V. Shift register circuit 10, data register circuit 11, data latch circuit 12, decoder circuit 13, data buffer circuit 19, timing control circuit 18, part of switched capacitor circuit 15, and higher voltage of gradation voltage generating circuit 17 VDD1 is set to VDD1 = 3.0V. The higher voltage VDD2 of the operational amplifier and output selection circuit 16 is set to VDD2 = 10V. In addition, the liquid crystal display device 2
7, the common electrode voltage VCOM = 5V. However, each of the above voltages is an example, and it goes without saying that other voltages may be used.

Next, the operation of the present liquid crystal drive circuit will be described with reference to FIGS.

When the start pulse signal SPR or SPL is input to the shift register circuit 10, the video signals D1 to Dm are sequentially output from the data register circuit 1 at each output by the shift register circuit 10 in synchronization with the clock signal.
1 and held. The held data is transferred and held by the data latch circuit 12 at the rise of the latch signal STB to the timing control circuit 18 (FIG. 3), and transferred to the next-stage decoder circuit 13. With respect to this data, the upper 5 bits of the 8-bit video signal are selected by the gray scale selection circuit 14 shown in FIG.
5 becomes the upper reference voltage and the lower reference voltage. Also, the lower three
As for the bit, one value is selected from eight voltage values in the switched capacitor circuit 15, and the output terminals Y1 and Y1 are output when the latch signal STB to the timing control circuit 18 falls.
A predetermined voltage is applied from Y2,..., Y2n-1, Y2n to a common electrode of a liquid crystal display (not shown).

Next, the configuration and operation of the present liquid crystal drive circuit will be described in more detail.

FIG. 4 is a circuit diagram showing a detailed configuration of the gradation voltage generation circuit 17. The grayscale voltage generation circuit 17 is composed of a resistor string circuit or the like, divides the liquid crystal reference voltages VR1 to VRk supplied from the outside by resistance division, and generates V1 and V1.
, V32 are generated. In addition,
FIG. 4 shows an example in which two voltages of the liquid crystal reference voltages VR1 and VRk are supplied. However, a plurality of types of voltages such as reference voltages VR1 to VRk may be supplied to minutely supply a divided voltage. When the liquid crystal display device 27 to which the present liquid crystal drive circuit is applied is a TFT, the amount of charge movement when the TFT is turned off is related to the reference voltage value supplied from outside the gradation voltage generation circuit 17 to the TFT. Since the voltage varies depending on the input voltage, it is preferable that the grayscale voltage generation circuit 17 be configured with two systems so that the liquid crystal reference voltage VRk supplied from the outside is different between the positive output and the negative output. Although the gray scale voltage generation circuit 17 requires relative accuracy, the relative accuracy in the case of manufacturing with a semiconductor has a capability of 16 bits or more, so that it can be easily realized with 5 to 8 bits accuracy.

FIG. 5 is a circuit diagram showing a detailed configuration of the gradation selection circuit 14, and shows the contents of each block shown in the gradation selection circuit 14 of FIG. Tone selection circuit 14a, 1
4b is composed of 32 switches (analog switches). The gray scale selection circuit 14a converts the voltages V0 to V31 of the gray scale voltage generation circuit 17 into video signals D1 to D1.
One value is selected based on the upper 5 bits of 8 bits in Dm, and is set as the upper reference voltage of the switched capacitor circuit 15. Similarly, the gradation selection circuit 14b selects one value from the voltages V1 to V32 of the gradation voltage generation circuit 17 based on the upper 5 bits of the 8 bits of the video signals D1 to Dm. Reference voltage. Here, each part of the gradation selection circuits 14a and 14b has a pair for each output by a switch at a connection portion between the gradation selection circuits 14a and 14b and the switched capacitor circuit 15, and the respective parts have upper reference voltage and lower reference voltage. It is supplied as a reference voltage. At this time, the upper reference voltage is a reference when a positive voltage is applied to the liquid crystal panel 27, and the lower reference voltage is a reference when a negative voltage is applied. For example, if the upper reference voltages are V0, V1, V2,..., V31, the lower reference voltages are selected to be V1, V2, V3,.

Next, the switched capacitor circuit 15 and the operational amplifiers AMP1 and AMP2 included therein will be described. In describing the switched capacitor circuit 15, FIGS. 6A to 6C are referred to.

The basic circuit configuration of each of the operational amplifiers AMP1 and AMP2 in the switched capacitor circuit 15 is as follows.
This is as shown in FIG. In the circuit configuration shown in FIG. 6A, the relationship between the input voltage VIN and the output voltage VOUT is expressed by equations and graphs shown in FIGS. 6B and 6C. According to FIG. 2, the capacity of 4C, 2C, and C is turned on / off by the switch corresponding to 3 bits from the decoder circuit 13 corresponding to C2 in FIG.
The amplification degree of P2 changes. Operational amplifiers AMP1, AMP
The description will be made assuming that the capacitance of the capacitor between the input and output of the second is C1.

The reference voltage value VIN of the switched capacitor circuit 15 is supplied from the gradation selection circuit 14, and the supplied higher voltage is VDD1 = 3V.
It becomes 3V.

The common electrode voltage VCOM = 5 V of the liquid crystal display device
In order to output a positive side voltage of 5 to 10 V, the capacitance ratio of the switched capacitor circuit 15 must be C2 / C1 = 5 /
3. When the non-inverting input voltage of the operational amplifier AMP1 is VREF1 =
By setting the voltage to 3.75 V, a desired output voltage range can be obtained. At this time, similarly, the capacitance of the capacitor between the input and output of the operational amplifiers AMP1 and AMP2 is set to a value of 8 (5/3) C. The capacitance at the right end of the input terminals of the operational amplifiers AMP1 and AMP2 in FIG. 2 is the timing control start. For example, when the output of the decoder 13 is “000”,
The connection relationship shown in FIG. 7 is obtained, and the lower reference voltage is the capacitance 7C +
C is applied to the input terminal of AMP1. If the output of the decoder 13 is "111", the upper reference voltage is
The capacitance 7C + C is applied to the input terminal of AMP1.

On the other hand, in order to output the negative voltage OV to 5V, C2 / C1 = 5/3 and the non-inverting input voltage of the operational amplifier AMP2 should be VREF2 = 1.875V.

Further, when VDD2 = 8V and VCOM = 4V, by setting VIN = 0 to 2.4V and VREF1 = 3.0V, a positive side output of 4 to 8V is obtained, and VIN = 0 to 2.V. 4
V and VREF2 = 1.5V, negative output O to 4V
Is obtained.

As described above, since the non-inverting input voltages VREF1 and VREF2 of the operational amplifier and the liquid crystal reference voltages VR1 to VRn can be externally controlled, the positive and negative output voltage ranges for driving the liquid crystal display device can be easily controlled. Can be.
The absolute accuracy of the reference voltage of the operational amplifier may be about 8 + 1 bits, and can be realized by a commercially available DC-DC converter.

Next, the operation of the present liquid crystal drive circuit will be described with reference to FIGS.

When the latch signal STB, which is an input signal to the timing control circuit 18, is at the H level, the switches of the output selection circuit 16 and the switches between the gradation selection circuits 14a, 14b and the switched capacitor circuit 15 are turned off (Hi). −
z). At this time, the switch between the inverting input terminal and the output of the operational amplifier of the switched capacitor circuit 15 is turned on, and the odd output is reset to the non-inverting input voltage VREF1 and the even output is reset to VREF2.

When the polarity signal POL is H and the latch signal STB
Is switched to L (low), the gradation selection circuits 14a, 1
The voltage selected by the upper 5 bits of the video signal in 4b is applied to the input switch of the switched capacitor circuit 15, and becomes the upper reference voltage and the lower reference voltage, respectively, as shown in FIG. At this time, the switched capacitor circuit 15
Controls the on / off of the switches of the plurality of capacitors 4C, 2C, C, C connected to the inverting input terminal of the operational amplifier, and selects the lower 3 bits of the video signal,
A voltage corresponding to the digital data of the video signal is selected and output. In accordance with the video signal supplied from the data latch circuit 12 for the video signal, the switched capacitor circuit 1 is output from the decoder circuit 13 in accordance with the lower three bits of the video signal.
5, by converting the signals into, for example, four switch control signals, the respective capacitors 4C, 2C,
On / off of switches C and C are controlled to select a voltage according to digital data of a video signal.

In FIG. 2, each decoder of the gradation selection circuit 14 has the circuit configuration of the gradation selection circuit 14 as shown in FIG. 10A, which is composed of an enhancement type and a depletion type FET array. A desired output value can be obtained by setting the arrangement of the type and the depletion type as a set value. For example, by using a depletion type and an enhanced type MOS transistor as 3 bits, the analog switch has a decoder function. Thus, the decoder circuit 13 can be made unnecessary.
Although FIG. 10A shows an example of an N-type MOSFET array, a P-type MOSFET array can be similarly configured.

In FIG. 10A, the data latch circuit 12
And the inverted signals thereof are applied, and the left input terminal is connected to the gray scale voltage generation circuit 17.
VX1 to VX8 corresponding to the 32 output terminals are connected, and a predetermined output is obtained as the output Q. For example, when LSB1 to LSB3 in FIG.
The value of VX1 is obtained as the output Q, and LSB1 to LSB3
Is "010", the value of VX3 is obtained at the output Q. In this way, the switches inside the gradation selection circuit 14 and the switched capacitor circuit 15 may be directly controlled.

Here, when the polarity signal POL supplied from the timing control circuit 18 is H, the output selection circuit 16
Operates to output a voltage on the positive side with respect to the liquid crystal common electrode voltage VCOM of the liquid crystal display device 27 from the operational amplifier AMP1 through the odd output terminal. A voltage on the negative side with respect to VCOM is output from the operational amplifier AMP2 through an even output terminal. On the other hand, when the polarity signal POL is L, a voltage on the negative side with respect to the liquid crystal common electrode voltage VCOM is output from the operational amplifier AMP2 through the odd output terminal. A voltage on the negative side with respect to VCOM is output from the operational amplifier AMP1 through an even output terminal. Note that the polarity signal POL is shown in FIG.
Are inverted to L, and the output terminals of the operational amplifiers AMP1 and AMP2 maintain the previous state during the H period of the latch signal STB. In this manner, the liquid crystal display device is AC-driven by sharing the two operational amplifiers with the two terminals and performing switch control so as to output positive and negative voltages in time series.

Next, FIGS. 7 and 8 show examples of the internal configuration of the operational amplifiers AMP1 and AMP2 in FIG. 2 (the operational amplifiers in FIG. 2 are indicated by arrows), respectively. In FIG. 7, the operational amplifier includes differential input stages N-1 and N-2 and current mirrors P-1 and P-2 serving as loads on the differential input stages.
An output stage P-3 which receives one output of the differential input stages N-1 and N-2 as an input; and a phase compensation capacitor CAMP1.
And current sources I0 and I1. In FIG. 8, the operational amplifiers are differential input stages P-4 and P-5.
And a current mirror N-3 serving as a load of the differential input stage.
N-4, an output stage N-5 having one output of the differential input stages P-4 and P-5 as inputs, and a phase compensation capacitor CAM.
P2 and current sources I2 and I3.

In the present liquid crystal driving circuit, the differential input stages use different types of operational amplifiers. In the case of outputting on the positive side with respect to the liquid crystal common electrode voltage VCOM, as shown in FIG.
By setting the transistors N-1 and N-2 of the differential input stage to Nch, the output can be maximized to the high potential side. In the case of outputting on the negative side with respect to the liquid crystal common electrode voltage VCOM, FIG.
As described above, by setting the transistors P-4 and P-5 of the differential input stage to Pch, the output can be maximized to the low potential side. The liquid crystal can be AC driven with a wide dynamic range by sharing these two operational amplifiers with two terminals and controlling the switches.

[Second Embodiment] Next, a liquid crystal drive circuit according to a second embodiment of the present invention will be described.

FIG. 9 is a schematic diagram showing a main part of a liquid crystal drive circuit according to the second embodiment of the present invention. Referring to FIG.
The liquid crystal drive circuit according to the present embodiment is different from the first embodiment shown in FIGS. 1 and 2 in the configuration of the gradation selection circuit 14 'and the switched capacitor circuit 15'. The gradation selection circuit 14 'has eight analog switches for the 5-bit input shown in FIG. 2, that is, 256 analog switches, and selects only one of the 256 values therefrom, and the switched capacitor circuit 15' Of the reference voltage. The non-inverting input voltages VREF1, VREF2, etc. of the operational amplifier in the switched capacitor circuit 15 'may be the same voltage as in the first embodiment, but the second embodiment operates as a so-called inverting amplifier.
In the switched capacitor circuit 15 ', the gray scale selection circuit 1
6A via a switch for distributing the reference voltage from 4 'to, for example, an odd-numbered liquid crystal panel and an even-numbered liquid crystal panel.
The output voltage corresponding to the switched capacitor is obtained on each of the positive side and the negative side by the circuit shown in FIG.

The merit of the second embodiment is that it has a monotonic increase. This is because there is no bit error in the switched capacitor circuit 15 'because the voltage is selected for all video data by the resistor strings circuit. As a disadvantage, in the first embodiment, the number of switches is 12 × 64 × 2 (upper reference voltage, lower reference voltage) for each output.
In the second embodiment, the number is doubled to 256, which is eight, which is a large chip area. However, since the configuration of the switched capacitor circuit 15 'is simpler than that of the first embodiment, depending on the unit capacitance value (1C) in the switched capacitor circuit 15', the chip is almost the same as or more than that of the first embodiment. Can be reduced in area.

[0038]

The liquid crystal drive circuit according to the present invention comprises a switched capacitor circuit including a pair of operational amplifiers having different reference voltages, and an output for controlling each output of the pair of operational amplifiers to output from an output terminal of the pair. And a positive / negative output voltage having a positive / negative amplitude relationship with respect to a voltage of 液晶 of the liquid crystal driving voltage or a voltage of a common electrode of the liquid crystal display device. Since the signals are alternately output from the terminals to the common electrode of the liquid crystal display device and the liquid crystal display device is AC-driven according to the video data, the following effects are obtained.

Since the decoder circuit and the gradation selection circuit operate at a voltage of 3 V, they can be manufactured by a low breakdown voltage diffusion process.
Since the transistor may be small, the chip size may be small.

Since a level shift circuit is not required, the circuit is small and consumes less power than a conventional circuit. In particular, since a large current does not flow transiently, the wiring width of the power supply wiring such as GND may be narrow, and the chip size is further reduced.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing a configuration of a liquid crystal drive circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a configuration of a main part of the liquid crystal drive circuit shown in FIG.

FIG. 3 is a timing chart for explaining the operation of the liquid crystal drive circuit shown in FIG.

FIG. 4 is a diagram showing a configuration of a gradation voltage generation circuit in the liquid crystal drive circuit shown in FIG.

FIG. 5 is a diagram showing a configuration of a gradation selection circuit in the liquid crystal drive circuit shown in FIG.

FIGS. 6A to 6C are diagrams illustrating the operation of the switched capacitor circuit in the liquid crystal drive circuit shown in FIG. 2;

7 is a circuit diagram showing an internal configuration of an operational amplifier included in a switched capacitor circuit in the liquid crystal drive circuit shown in FIG.

8 is a circuit diagram showing an internal configuration of an operational amplifier included in a switched capacitor circuit in the liquid crystal drive circuit shown in FIG.

FIG. 9 is a schematic diagram showing a configuration of a main part of a liquid crystal drive circuit according to a second embodiment of the present invention.

FIG. 10 is an explanatory diagram showing a circuit example and an operation example of the FET array according to the embodiment of the present invention.

FIG. 11 is a schematic diagram showing a configuration of a liquid crystal drive circuit according to a conventional example.

[Explanation of symbols]

 10, 21 shift register circuit 11, 22 data register circuit 12, 23 data latch circuit 13, 24 decoder circuit 14, 14 'gradation selection circuit 15, 15' switched capacitor circuit 16 output selection circuit 17 gradation voltage generation circuit 18 Timing control circuit 19 Data buffer circuit 25 Level shift circuit group 26 Analog switch 27 Liquid crystal panel 28 Vertical scanning circuit

Claims (10)

[Claims] 1. A switched capacitor circuit including a pair of operational amplifiers having different reference voltages from each other, and an output selection circuit for switching each output of the pair of operational amplifiers and outputting the output from a pair of output terminals, Positive and negative output voltages having a positive / negative amplitude relationship with respect to a half of the liquid crystal drive voltage are alternately output from a pair of output terminals of the output selection circuit to a common electrode of the liquid crystal display device. And a liquid crystal driving circuit for driving the liquid crystal display device in accordance with video data. 2. A switched capacitor circuit including a pair of operational amplifiers having different reference voltages from each other, and an output selection circuit that switches each output of the pair of operational amplifiers and outputs the output from a pair of output terminals, Positive and negative output voltages having a positive and negative amplitude relationship with respect to the voltage of the common electrode of the liquid crystal display device are alternately output from the output terminals of the pair of output selection circuits to the common electrode of the liquid crystal display device. And a liquid crystal driving circuit for driving the liquid crystal display device in accordance with video data. 3. A grayscale selection circuit for selecting a grayscale voltage according to video data and outputting the selected grayscale voltage to the switched capacitor circuit is constituted by analog switches for the number of grayscales. 3. The liquid crystal drive circuit according to claim 1, wherein the reference voltages of the two operational amplifiers of the switched capacitor circuit are used. 4. A shift register that is driven based on a clock triggered by a start signal, a data register that transfers and holds an input digital video signal by the shift register, and an odd-numbered data register based on each bit data of the data register. A gradation selection circuit for generating an even reference voltage, a switched capacitor circuit having at least two operational amplifiers for generating a capacitor divided voltage by using the odd / even reference voltages as inputs, and an output of the switched capacitor circuit by the two operational amplifiers An output selection circuit for switching the odd / even reference signal lines to odd / even vertical signal lines, wherein the switched capacitor circuit has at least two operational amplifiers for amplifying the odd / even reference voltage through a capacitor. LCD drive circuit. 5. A gradation selection circuit comprising: a gradation voltage generation circuit that obtains a predetermined number of divided voltages by dividing a liquid crystal reference voltage by resistance dividing the predetermined number of divided voltages into one by way of the predetermined number of switches; 5. The liquid crystal drive circuit according to claim 4, wherein a value is selected and output. 6. The two operational amplifier of the switched capacitor circuit includes an operational amplifier having a transistor of a differential input stage as an n-type channel and an output stage of a p-channel, and an output of the transistor of the differential input stage as a p-type channel. 5. An operational amplifier having an n-channel stage.
Or the liquid crystal driving circuit according to 5. 7. A shift register that is driven based on a clock triggered by a start signal, a data register that transfers and holds an input digital video signal by the shift register, and an odd number / bit number based on each bit data of the data register. A gradation selection circuit for generating an even reference voltage, a switched capacitor circuit having at least two operational amplifiers for generating a capacitor divided voltage by using the odd / even reference voltages as inputs, and an output of the switched capacitor circuit by the two operational amplifiers An output selection circuit for switching to the odd / even vertical signal lines of the liquid crystal panel, a liquid crystal panel circuit having a liquid crystal panel driven by the output selection circuit, and a vertical scanning circuit for driving horizontal lines of the liquid crystal panel. Wherein the switched capacitor circuit is A liquid crystal driving device which is characterized in the serial odd and even reference voltage to have at least two operational amplifiers of the capacitor ratio amplified through the capacitor. 8. A gradation selection circuit, comprising: a gradation voltage generation circuit for obtaining a predetermined number of divided voltages by dividing a liquid crystal reference voltage by resistance; 8. The liquid crystal driving device according to claim 7, wherein a value is selected and output. 9. The operational amplifier of the switched-capacitor circuit includes a transistor of a differential input stage as an n-type channel and an output stage of a p-channel when the output of the differential capacitor is a positive output with respect to a common voltage of the liquid crystal panel. 9. The liquid crystal driving device according to claim 7, wherein when the common voltage of the liquid crystal panel is output on the negative side, the transistor of the differential input stage is a p-type channel and the output stage is an n-channel. apparatus. 10. The enhancement type and depletion type FET arrays connected to the gradation selection circuit select one value of the predetermined number of divided voltages by the gradation selection circuit based on data of the data register. The liquid crystal driving device according to claim 7, wherein the liquid crystal driving device outputs the signal.