JP2009157393A - Data driver and display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data driver of a display apparatus which achieves small footprint and cost reduction. <P>SOLUTION: The data driver includes: a zero point compensation capacitor R1 in series to a phase compensation capacitor C1 between an output node N12 of an input differential amplification stage and an output node N11 of a post amplification stage; and a control circuit 20 for changing over the resistance value of the zero point compensation capacitor R1. The control circuit 20 changes over the resistance value of the zero point compensation capacitor R1 to a first resistance value and a second resistance value greater than the first resistance value in accordance with the on and off of an output switch 10 for controlling the connection of an output terminal N11 of an amplifier circuit and a data line 962. A plurality of amplifier circuits and driver output terminals are divided into at least a first group and a second group, and the plurality of amplifier circuits change over resistance values of zero point compensation capacitors in manners different by groups. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data driver and a display device using the data driver.

  Recently, the demand for liquid crystal display devices as a large-screen liquid crystal television is increasing in addition to mobile phones (mobile phones, cellular phones), notebook PCs, and monitors. As these liquid crystal display devices, active matrix liquid crystal display devices capable of high-definition display are used. First, a typical configuration of an active matrix drive type liquid crystal display device will be outlined with reference to FIG. In FIG. 11, the main configuration connected to one pixel of the liquid crystal display unit is schematically shown by an equivalent circuit.

  In general, a display unit 960 of an active matrix liquid crystal display device includes a semiconductor substrate in which transparent pixel electrodes 964 and thin film transistors (TFTs) 963 are arranged in a matrix (for example, in the case of a color SXGA panel, 1280 × 3 pixel columns × 1024). A pixel row), a counter substrate in which one transparent electrode 967 is formed on the entire surface, and a structure in which liquid crystal is sealed between the two substrates facing each other.

  The TFT 963 having the switching function is controlled to be turned on / off by a scanning signal. When the TFT 963 is turned on, a gradation signal voltage corresponding to the video data signal is applied to the pixel electrode 964, and each pixel electrode 964 and the counter substrate electrode Even after the TFT 963 is turned off due to the potential difference with the 967 and the TFT 963 is turned off, the potential difference is held for a certain period by the liquid crystal capacitor 965 and the auxiliary capacitor 966 to display an image.

  On the semiconductor substrate, data lines 962 for sending a plurality of level voltages (gradation signal voltages) to be applied to the pixel electrodes 964 and scanning lines 961 for sending scanning signals are wired in a grid pattern (in the color SXGA panel). In this case, the number of data lines is 1280 × 3 and the number of scanning lines is 1024), and the scanning lines 961 and the data lines 962 have a large capacity due to the capacity generated at the intersection or the liquid crystal capacity sandwiched between the counter substrate electrodes. Sexual load.

  Note that the scanning signal is supplied from the gate driver 970 to the scanning line 961, and the gradation signal voltage is supplied to each pixel electrode 964 from the data driver 980 through the data line 962. The gate driver 970 and the data driver 980 are controlled by the display controller 950, and necessary clock CLK, control signal, power supply voltage, and the like are supplied from the display controller 950, and video data is supplied to the data driver 980. At present, video data is mainly digital data.

  Rewriting of data for one screen is performed in one frame period (usually about 0.017 seconds), and is sequentially selected for each pixel line (each line) in each scanning line. A grayscale voltage signal is supplied from the line.

  Note that the gate driver 970 only needs to supply at least a binary scanning signal, while the data driver 980 needs to drive the data line with a multi-level gradation voltage signal corresponding to the number of gradations. It is said. Therefore, the data driver 980 includes a digital-analog conversion circuit (DAC) including a decoder that converts video data into an analog voltage and an output amplifier that amplifies and outputs the analog voltage to the data line 962.

  FIG. 12A shows a connection configuration of the output buffer of the data driver 980 and the data line 962 in FIG. An output switch SW10 is provided between the output terminal N9 of the output buffer 90 and the driver output terminal P09 to which the data line 962 is connected. The output switch SW10 is generally provided in a data driver of a liquid crystal display device for the purpose of preventing transition noise generated in a circuit such as a decoder from being transmitted to a data line when video data changes.

  FIG. 12B is a diagram illustrating a state of the control signal S1 for controlling on / off of the output switch SW10 and the switch SW10. Referring to FIG. 12B, a period T1 and a period T2 are provided in one data period, the output switch SW10 is turned off from the start of one data period to the period T1, and the data of the output signal of the output buffer 90 Transmission to line 962 is cut off. In the period T2, the output switch SW10 is turned on, and the output signal of the amplifier circuit (amplifier circuit) 90 is output to the data line. The period T1 is set to a period according to the convergence time of the transition noise.

  An amplifier circuit having a general voltage follower configuration can be used for the output buffer in FIG. The amplifier circuit 90 in FIG. 12A includes a current source M15 having a first terminal connected to the lower power supply VSS, and an N-channel transistor (N-channel MOS transistor) having a common source connected to the second terminal of the current source M15. ) A differential pair composed of M11 and M12, a current mirror composed of P-channel transistors (P-channel MOS transistors) M13 and M14 connected between the output pair of the differential pair (M11 and M12) and the high-side power supply VDD, A P-channel transistor M16 having a gate connected to the output end node N12 of the current mirror (M13, M14), a source connected to the higher power supply VDD2, and a drain connected to the amplifier output terminal N9, a lower power supply VSS and an amplifier And a current source M17 connected between the output terminal N9. In this specification, a differential pair composed of the transistors Ma and Mb is referred to as a differential pair (Ma, Mb). A current mirror composed of the transistors Mc and Md is referred to as a current mirror (Mc, Md).

  In the amplifier circuit 90, the inverting input terminal (gate of the transistor M11) of the differential pair (M11, M12) is connected to the amplifier output terminal N9, and the non-inverting input terminal (gate of the transistor M12) of the differential pair (M11, M12). ) Is input with the voltage Vin selected by a decoder (not shown) according to the video data.

  A phase compensation capacitor C1 and a zero compensation resistor R1 are connected in series between the gate (node N12) and the drain (amplifier output terminal N9) of the P-channel transistor M16. Yes. By inserting a zero compensation resistor R1 in series with the phase compensation capacitor C1, zero (zero) is created in the frequency characteristic, the band is improved, the phase margin is increased, and the operation of the amplifier is stabilized. This is effective in suppressing the capacitance value (and hence the size) of the phase compensation capacitor C1 having a relatively large area in the chip.

  Between the amplifier output terminal N9 of the amplifier circuit 90 and the data line 962, an output switch SW10 that is on / off controlled by a control signal S1 is connected.

  Since the amplifier circuit 90 is provided in the number corresponding to the number of outputs in the data driver 980 of FIG. 11, in the multi-output data driver LSI, it is important for cost reduction to configure the amplifier circuit 90 with a small area. .

  FIG. 13 is a diagram illustrating a configuration of another amplifier that can be used as the amplifier circuit 90 in FIG. FIG. 13 is a diagram showing a configuration of a class AB output circuit disclosed in Patent Document 2 described later. Referring to FIG. 13, in this class AB output circuit, the output stage has a P-channel transistor M85 connected between the high-order power supply VDD and the output terminal ND1, and an N-connector connected between the output terminal ND1 and the low-order power supply VSS. A channel transistor M86, and has high charge capability and discharge capability for the output terminal ND1. The gate NP1 of the P-channel transistor M85 is connected to the output terminal of the driver 89 that receives the input signal Vin, and performs the charging operation of the output Vout of the amplifier. The change of the input signal Vin is transmitted to the gate NN1 of the N-channel transistor M86 through the intermediate stage (M81, M82), and the discharge operation of the output Vout of the amplifier is performed.

  The intermediate stage is composed of P-channel and N-channel floating current sources M81 and M82 and current sources M83 and M84. The P-channel and N-channel floating current sources M81 and M82 are supplied with bias voltages BP8 and BN8 respectively at their gates. Are connected between the gates (NP1, NN1) of the transistors M85, M86. The current source M83 is connected between the high power supply VDD and the gate NP1 of the P-channel transistor M85, and the current source M84 is connected between the low power supply VSS and the gate NN1 of the N-channel transistor M86. The total current of the floating current sources M81 and M82 is set to a current substantially equal to each of the current sources M83 and M84.

  The operation of the class AB output circuit of FIG. 13 will be described below. When the terminal NP1 changes to the low potential side according to the input voltage Vin, the P-channel transistor M85 performs a charging operation. Immediately after the change of the terminal NP1, the current of the N-channel floating current source M82 does not change, but since the current of the P-channel floating current source M81 decreases, the terminal NN1 changes to the low potential side, and the N-channel transistor M86 discharges. The operation is stopped. For this reason, the class AB output circuit of FIG. 13 can perform a high-speed charging operation. Note that when the terminal NN1 changes to the low potential side, the current of the N-channel floating current source M82 begins to increase. Therefore, the potential of the terminal NN1 once changes to the low potential side and then gradually rises again to increase the steady state potential. Get closer to.

  On the other hand, when the terminal NP1 changes to the high potential side according to the input voltage Vin, the charging operation of the P-channel transistor M85 is stopped. Immediately after the change of the terminal NP1, the current of the N-channel floating current source M82 does not change, but since the current of the P-channel floating current source M81 increases, the terminal NN1 changes to the high potential side and the N-channel transistor M86 is discharged. Perform the action. For this reason, the class AB output circuit of FIG. 13 is capable of high-speed discharge operation.

  Further, regarding the idling current (static current consumption) of the intermediate stage, if the relationship between the total current of the floating current sources M81 and M82 and the current of the current sources M83 and M84 is maintained, the respective current values can be made sufficiently small. it can.

  Comparing the amplifier circuit 90 in FIG. 12A and the class AB output circuit in FIG. 13, the discharge capability of the amplifier circuit 90 in FIG. 12A depends on the current value of the current source M17 with respect to the discharge operation. In order to realize a fast discharge operation, the current value of the current source M17 must be increased.

  In contrast, the class AB output circuit of FIG. 13 has a current value that is sufficiently small and does not increase the current value particularly, although current flows through the floating current sources M81 and M82 and the current sources M83 and M84 in the intermediate stage. Both can be operated at high speed. That is, the class AB output circuit in FIG. 13 is suitable for driving a display panel having a large load capacity with low power consumption.

  The class AB output circuit of FIG. 13 does not describe a phase compensation capacitor or a zero compensation resistor, but between the output node NP1 (gate of the P-channel transistor M85) of the driver 89 and the output terminal Vout, A series circuit of a phase compensation capacitor C and a zero compensation resistor R1 can be connected and used.

  FIG. 14 is a diagram illustrating a configuration of an operational amplifier disclosed in Patent Document 2 described later. FIG. 14 shows that the phase compensation capacitance is controlled by on / off control of the switches S1 and S2 connected in series with the phase compensation capacitors C1 and C4 according to the respective states in order to stably operate in two states having different gains. In this configuration, the capacitance value is switched. By switching the capacitance value according to two states having different gains, the operational amplifier is stably operated in each state.

Japanese Patent Publication No. 6-91379 (FIG. 1) JP 61-296805 (FIG. 1)

  It is desirable that the data driver of the liquid crystal display device can be widely used for various display panels having different screen sizes and resolutions. Therefore, the output buffer (amplifier circuit 90) of the data driver is optimal so that the data line capacity (load capacity) can be driven in the range of several tens of picofarads (one pico is the minus 12th power of 10) to several hundred picofarads. It has become.

  As described with reference to FIGS. 12A and 12B, the output switch SW10 is disposed between the output terminal of the output buffer (amplifier circuit 90) and the data line 962. In the period T1 immediately after the start of the data period, the switch SW10 is turned off. At this time, the load capacity of the amplifier circuit 90 in the period T1 is substantially zero.

  In the period T1, there is no problem even if some variation occurs in the output signal of the amplifier circuit 90, but the output of the amplifier circuit 90 must be stabilized by the end of the period T1. For example, when the output signal of the amplifier circuit 90 oscillates during the period T1, oscillation noise may be amplified and transmitted to the data line 962 at the moment of switching from the period T1 to the period T2. For this reason, the amplifier circuit 90 must be stably operated through the periods T1 and T2.

  Therefore, the amplifier circuit 90 is optimized so as to stably operate in a range of several hundred picofarads from a state where the load capacitance is zero.

  As is well known, whether or not the amplifier circuit operates stably can be based on the phase margin, and the larger the phase margin, the more stable the amplifier output.

  However, in order to ensure a sufficient phase margin when the load capacitance is in the range of zero to several hundred picofarads, the capacitance value of the phase compensation capacitor C1 of the amplifier circuit 90 must be sufficiently large.

  As shown in FIG. 12A, even if the zero compensation resistor R1 is used, there is a limit to the effect of suppressing the capacitance value of the phase compensation capacitor C1 (refer to the description of FIG. 10 described later for details).

  When the capacitance value of the phase compensation capacitor C1 is increased, there is a problem that the area of the amplifier circuit 90 is increased and the cost of the data driver LSI is increased.

  Further, when the capacitance value of the phase compensation capacitor C1 is increased, the bandwidth and speed of the amplifier circuit 90 are reduced. Specifically, the slew rate of the output of the amplifier circuit 90 is reduced.

  In order to avoid the decrease in the slew rate, the idling current (static current consumption) of the amplifier circuit 90 must be increased. For this reason, the power consumption of the amplifier circuit 90 increases and the power consumption of the data driver LSI increases.

  Further, when the class AB output circuit of FIG. 13 is used in place of the amplifier circuit 90 of FIG. 12A, the same problem as that of FIG. 12A occurs.

  On the other hand, when the operational amplifier of FIG. 14 is used in place of the amplifier circuit 90 of FIG. 12A, the on / off control of the switches S1 and S2 is performed in response to the on / off of the output switch SW10, and the phase The capacitance value of the compensation capacitor can be switched. However, when a voltage signal of a different level corresponding to the image data is amplified and output for each output period, the operational amplifier of FIG. 14 charges or discharges the connected capacitor or connects the connected capacitor when switching the capacitance value. There is a problem that large noise is generated in the output signal due to potential fluctuation of the terminal through the terminal. In particular, when the state is switched in a short time, there is a problem that the output signal cannot be stabilized within a predetermined period (period T1 or T2 in FIG. 12B).

  Further, the method of switching the capacitance value of the phase compensation capacitor does not reduce the area of the phase compensation capacitor and does not lead to the cost reduction effect of the driver LSI.

  Accordingly, an object of the present invention is to provide a data driver for a display device that saves area and reduces costs.

  Another object of the present invention is to provide a data driver of a display device that reduces power consumption.

  Furthermore, another object of the present invention is to provide a display device with low cost and low power consumption by using the data driver.

  In order to solve the above-described problems, the invention disclosed in the present application is generally configured as follows.

A data driver according to the present invention is a data driver having an amplifier circuit that receives a voltage signal based on input data and amplifies and outputs it to a driver output terminal,
A plurality of the amplifier circuit and the driver output terminal, respectively,
The amplifier circuit is
An input differential stage;
An amplification stage that amplifies and outputs to the output terminal of the amplification circuit based on the output of the input differential stage;
A phase compensation capacitor and a zero compensation resistor connected between one output node of the input differential stage and an output terminal of the amplification stage;
A control circuit that switches and controls the resistance value of the zero compensation resistor to one of at least two resistance values different from each other in accordance with a control signal;
With
The plurality of amplifier circuits and the driver output terminals are divided into at least a first group and a second group,
In the plurality of amplifier circuits, the resistance value of the zero compensation resistor that is different for each group is switched.

  In the present invention, the phase compensation capacitor and the zero compensation resistor are connected in series between one output node of the input differential amplifier stage and one output node of the subsequent amplifier stage of the amplifier circuit in the amplifier circuit. Connected to form.

  In the present invention, it further includes an output switch connected between the output terminal of the amplifier circuit and the data driver output terminal and controlled to be turned on and off by a second control signal. The switching of the resistance value of the zero compensation resistor is controlled in association with ON and OFF.

In the present invention, when the output switch is off, the control circuit sets the zero compensation resistor to a smaller resistance value between the first resistance value and the second resistance value, which are different from each other,
When the output switch is on, the zero compensation resistor is set to a larger resistance value of the first resistance value and the second resistance value.

  In the present invention, the control circuit includes a switch transistor that is connected between two voltage dividing nodes including both ends of the zero compensation resistor and that is on / off controlled based on the control signal input to the control end. ing.

  In the present invention, the zero compensation resistor includes at least two transistors that are set in an ON state and are cascode-connected, and the control circuit is in parallel with one of the two transistors that are cascode-connected. And a switch transistor that inputs the control signal to the control terminal.

  In the present invention, the zero compensation resistor includes a first resistor and a second resistor connected in series, and the control circuit includes one of the first resistor and the second resistor. It is good also as a structure provided with the switch transistor which is connected in parallel and inputs the said control signal into a control terminal.

In the present invention, the amplifier circuit includes:
A first differential pair receiving an input signal at a first input;
A current source connected to a first power source and supplying current to the differential pair;
A load circuit connected between the output pair of the differential pair and a second power supply;
An amplification stage in which an input terminal is connected to at least one of connection nodes between the output pair of the differential pair and the load circuit, and an output terminal is connected to an output terminal of the amplifier circuit;
And a signal at the output terminal of the amplifier circuit is fed back to a second input of the differential pair, and the zero compensation resistor and the phase compensation capacitor are connected to the output terminal of the amplifier circuit, and the amplifier stage. And a connection node with the load circuit are connected in series.

  In the present invention, the amplification stage includes a first output transistor connected between a control node at a connection node between the output pair of the differential pair and the load circuit, and connected between a second power source and the output terminal. And a second current source connected between the output terminal and a first power source.

In the present invention, a second current source connected between the first power source and a first node;
A floating current source circuit connected between the first node and the second node;
A third current source connected between the second node and the second power source;
A first output transistor connected between the second power supply and the output terminal, a connection node between the output pair of the differential pair and the load circuit, and a control terminal connected to the second node;
A second output transistor connected between the first power supply and the output terminal and having a control terminal connected to the first node. The floating current source circuit includes two floating current sources having different conductivity types juxtaposed between the first node and the second node.

In the present invention, the amplifier circuit includes:
A first differential pair receiving a first input signal at a first input;
A first current source connected to a first power supply and supplying a current to the first differential pair;
A first load circuit connected between an output pair of the first differential pair and a second power source;
An input terminal is connected to at least one of connection nodes between the output pair of the first differential pair and the first load circuit, and an output terminal is connected to a first output terminal of the amplifier circuit. An amplification stage, and
A signal at the first output terminal of the amplifier circuit is fed back to a second input of the first differential pair, and the first set of the zero compensation resistor and the phase compensation capacitor is the amplifier circuit. Are connected in series with each other between the output terminal and a connection node between the first amplification stage and the first load circuit.

Further, the amplifier circuit includes:
A second differential pair receiving a second input signal at the first input;
A second current source connected to the second power source and supplying a current to the second differential pair;
An output pair of the second differential pair, a second load circuit connected between the first power source, an output pair of the second differential pair, and the second load circuit A second amplification stage having an input terminal connected to at least one of the connection nodes and an output terminal connected to a second output terminal of the amplifier circuit;
A signal from the second output terminal of the amplifier circuit is fed back to a second input of the second differential pair, and the second set of the zero compensation resistor and the phase compensation capacitor is the amplifier circuit. Are connected in series to each other between the output terminal and a connection node between the second amplification stage and the second load circuit.
The control circuit switches the resistance value of the zero compensation resistor of the first set to a first resistance value or a second resistance value different from the first resistance value according to a first control signal. And control to switch the resistance value of the second set of the zero compensation resistors to a third resistance value or a fourth resistance value different from the third resistance value in accordance with a second control signal. .

In the present invention, a first output switch connected between a first output terminal of the amplifier circuit and a first driver output terminal;
A second output switch connected between a second output terminal of the amplifier circuit and a second driver output terminal;
A third output switch connected between the first output terminal of the amplifier circuit and the second driver output terminal;
And a fourth output switch connected between the second output terminal of the amplifier circuit and the first driver output terminal.

In the present invention, a third current source connected between the first power source and the first node;
A first floating current source circuit connected between the first node and the second node;
A fourth current source connected between the second node and a second power source;
A control terminal is connected between the second power source and the first output terminal, a connection node between the output pair of the first differential pair and the first load circuit, and the second node. A first output transistor;
A second output transistor connected between the first power supply and the first output terminal and having a control terminal connected to the first node;
A fifth current source connected between the second power source and a third node;
A second floating current source circuit connected between the third node and the fourth node;
A sixth current source connected between the fourth node and the first power source;
A third output transistor connected between the second power source and the second output terminal and having a control terminal connected to the third node;
A control terminal is connected between the first power supply and the second output terminal, and a connection node between the output pair of the second differential pair and the second load circuit and the fourth node. And a fourth output transistor. The first floating current source circuit includes two floating current sources having different conductivity types arranged in parallel between the first node and the second node. The second floating current source circuit includes two floating current sources having different conductivity types arranged in parallel between the third node and the fourth node.

  In the present invention, a plurality of amplifier circuits are provided corresponding to each of a plurality of driver output terminals, and the plurality of amplifier circuits are grouped into at least a first group and a second group, and a plurality of the amplifier circuits are provided. The resistance value of the zero compensation resistor is switched for each group, and the plurality of amplifier circuits and the driver output terminals forming the first group are connected to data lines of the driver output terminals, respectively. The one or more amplifier circuits and the driver output terminals forming the second group are not connected to the driver output terminals.

  The differential amplifier circuit according to the present invention includes a differential amplifier having a zero compensation resistor in series with a phase compensation capacitor between one output node of the first stage of differential amplification and a predetermined output node of the subsequent amplifier stage. And a control circuit that variably controls the resistance value of the zero compensation resistor in accordance with a control signal.

  In the present invention, the control circuit switches the resistance value of the zero compensation resistor between large and small according to the magnitude of the load capacitance connected to the output terminal of the differential amplifier circuit based on the control signal.

  The display device according to the present invention includes the data driver of the present invention as a data driver for driving the data lines.

  According to the present invention, an amplifier circuit having a phase compensation capacitor and a zero compensation resistor is used as an output buffer of a data driver, and the zero compensation resistor is switched to an optimum resistance value in accordance with a change in the capacitance value of the load capacitor. Thus, the capacitance value of the phase compensation capacitor can be reduced while maintaining the phase margin.

  In addition, according to the present invention, since the resistance value of the zero compensation resistor is switched between the same potential terminals, almost no noise is generated in the output signal of the amplifier circuit at the time of switching.

  Further, according to the present invention, the area of the amplifier circuit can be reduced by reducing the capacitance value of the phase compensation capacitor, and the area saving and cost reduction of the data driver of the display device can be realized.

  Furthermore, according to the present invention, the idling current (static current consumption) of the amplifier circuit necessary for maintaining a predetermined slew rate can be reduced by reducing the capacitance value of the phase compensation capacitor. As a result, the power consumption of the data driver of the display device can be reduced.

  And according to this invention, the display apparatus which can implement | achieve area saving (low cost) and low electric power can be provided.

It is a figure which shows the structure of one Embodiment of the data driver of this invention. It is a figure explaining switch control of one embodiment of the data driver of the present invention. It is a figure which shows the structure of one Example of the data driver of this invention. It is a timing diagram explaining switch control of one example of the data driver of the present invention. It is a figure which shows the structure of the 2nd Example of the data driver of this invention. It is a figure which shows the structure of the 3rd Example of the data driver of this invention. It is a figure which shows the structure of the 4th Example of the data driver of this invention. It is a timing diagram explaining switch control of the 4th example of the data driver of the present invention. It is a figure which shows one Example of the display apparatus of this invention. It is a figure for demonstrating the relationship between the zero point compensation resistance value and phase margin in this invention. It is a figure which shows the structure of the conventional liquid crystal display device. (A) is a figure which shows the connection structure of a data driver, an output buffer, and a data line, (B) is a figure which shows switch control. 10 is a diagram illustrating a configuration of an output circuit disclosed in Patent Document 2. FIG. It is a figure which shows the structure of the operational amplifier circuit disclosed by patent document 2. FIG.

  The above-described present invention will be described below with reference to the accompanying drawings in order to describe it in more detail.

  FIG. 1 is a diagram showing the configuration of the first exemplary embodiment of the present invention. FIG. 1 is a diagram illustrating a configuration of an output buffer of a data driver of a liquid crystal display device.

  In the present embodiment, the resistance value of the zero compensation resistor R1 is controlled by an amplifier circuit (see FIG. 12A) including a phase compensation capacitor C1 and a zero compensation resistor R1 connected in series to the phase compensation capacitor C1. A control circuit 20 is provided.

  The amplifier circuit according to the present embodiment is a differential circuit including a current source M15 having a first terminal connected to the lower power supply VSS and N-channel transistors M11 and M12 having a common source connected to a second terminal of the current source M15. A current mirror (current mirror) including a pair (denoted as a differential pair (M11, M12)), and an output pair of the differential pair (M11, M12) and a P-channel transistor M13, M14 connected between the higher power supply VDD (Denoted as M13, M14)), a gate connected to the output end node N12 of the current mirror (M13, M14), a source connected to the higher power supply VDD, and a drain connected to the amplifier output terminal N11 A channel transistor M16 and a current source M17 connected between the lower power supply VSS and the amplifier output terminal N11 are provided. In the amplifier circuit, the inverting input terminal (gate of the transistor M11) of the differential pair (M11, M12) is connected to the amplifier output terminal N11, and the non-inverting input terminal (gate of the transistor M12) of the differential pair (M11, M12). Is supplied with a voltage Vin selected by a decoder (not shown) according to the video data.

  A phase compensation capacitor C1 and a zero compensation resistor R1 are connected in series between the gate (node N12) and drain (amplifier output terminal N11) of the P-channel transistor M16.

  Further, an output switch SW10 that is on / off controlled by a control signal S1 is provided between the output terminal N11 of the amplifier circuit and the data line 962.

  The control circuit 20 switches the zero point compensation resistor R1 to a different first or second resistance value depending on the value of the control signal S2. One of the first and second resistance values may be zero ohms (the resistance value between the resistance terminals is 0 ohm and the resistance is not provided or both ends of the resistance are short-circuited).

  The control signal S2 is a control signal that is linked to the control signal S1 that performs on / off control of the output switch SW10, and the resistance value of the zero compensation resistor R1 is switched in response to the on / off control of the output switch SW10. .

  FIG. 2 shows the control of the switch SW10 by the control signal S1 and the control circuit 20 by the control signal S2 in one data period in which the signal voltage Vin corresponding to one data of the gradation signal is amplified and output to the data line 962. One data period has a period T1 and a period T2.

  In the period T1, the switch SW10 is turned off, and the output terminal N11 of the amplifier circuit and the driver output terminal P01 are not connected. At this time, the load capacity of the amplifier circuit is almost zero. In the period T1, the control circuit 20 sets the zero compensation resistor R1 to a relatively small resistance value (first resistance value).

  The period T1 is set in a relatively short time immediately after switching of each data period, which is a period for preventing transition noise generated in the decoder from being transmitted to the data line 962 at the time of switching data.

  In a period T2 after the period T1, the switch SW10 is turned on, the output terminal N11 of the amplifier circuit and the driver output terminal P01 are connected, and the signal voltage Vin is amplified and output to the data line 962. At this time, the load capacity of the amplifier circuit becomes the load capacity of the data line 962.

  In the period T2, the control circuit 20 switches the zero compensation resistor R1 to a resistance value (second resistance value) higher than that in the period T1.

  Thus, the amplifier circuit can be stably operated while maintaining a high phase margin through the periods T1 and T2.

  Note that the switching of the resistance values of the switch SW10 and the zero compensation resistor R1 may be controlled by synchronous control or timing shifted by a predetermined time.

  Next, control of the load capacity of the amplifier circuit and the resistance value of the zero compensation resistor R1 will be described below.

  FIG. 10 is a diagram showing the relationship between the resistance value of the zero compensation resistor R1 and the phase margin of the amplifier circuit 90 of FIG. FIG. 10 shows a characteristic curve for each capacitance value of the load capacitance. The phase compensation capacitor C1 is a constant value.

  According to the analysis result by the present inventor, each characteristic curve in FIG. 10 shows that the phase margin increases as the zero compensation resistance value increases, but the phase margin tends to decrease when the predetermined resistance value is exceeded. Have.

  Further, in each characteristic curve of FIG. 10, the zero compensation resistance value at which the phase margin is maximized tends to shift to the high resistance side as the load capacity increases.

  Furthermore, the relationship between the phase compensation capacitor C1 and each characteristic curve has a tendency to shift to the high phase margin side while maintaining the shape of each characteristic curve when the capacitance value of the phase compensation capacitor C1 increases.

  Here, based on the result of FIG. 10, consider the case where the optimum value of the zero compensation resistor R1 of the amplifier circuit 90 of FIG.

  In the period T1 and the period T2 in FIG. 12B, the resistance value of the zero compensation resistor R1 is constant. Therefore, in order to ensure a phase margin of a certain level or more with respect to a load capacity of zero to several hundred picofarads (pF), the zero compensation resistance value near the region A in FIG. 10 must be set. This is because when the zero compensation resistance value is larger than the region A, the phase margin at the load capacitance of 1 fF or less decreases, and when the zero compensation resistance value is smaller than the region A, the phase margin at the load capacitance of 10 pF to 30 pF. This is because of a decrease. If the phase margin in the region A is not sufficient, the phase margin must be increased by increasing the capacitance value of the phase compensation capacitor C1.

  On the other hand, when the optimum value of the zero compensation resistor R1 of the amplifier circuit of FIG. 1 is set based on FIG. 10, different zero compensation resistors can be set in the periods T1 and T2 of FIG. .

  In the period T1 in FIG. 2, since the load capacitance is substantially zero, the first resistance value can be set to the zero compensation resistance value near the region C in FIG. In the region C, a high phase margin can be obtained for a load capacitance of 1 pF or less.

  Further, in the period T2 in FIG. 2, the load capacitance is several tens of picofarads to several hundred picofarads, and therefore the second resistance value can be set to the zero compensation resistance value in the vicinity of the region B in FIG. In the region B, a high phase margin can be obtained for a load capacitance of 10 pF or more.

  Regions B and C in FIG. 10 have a higher phase margin than region A. Therefore, for the same phase compensation capacitor C1, the amplifier circuit of this embodiment shown in FIG. 1 can obtain a higher phase margin than the amplifier circuit of FIG.

  Further, when the amplifier circuit of FIG. 1 realizes a sufficiently high phase margin and has an operation margin, the capacitance value of the phase compensation capacitor C1 of the amplifier circuit of FIG. 1 can be reduced to reduce the area. . When the capacitance value of the phase compensation capacitor C1 is reduced, the slew rate can be maintained even if the idling current of the amplifier circuit is reduced. Therefore, power consumption can be reduced.

  In the above-described embodiment, the case where the second resistance value of the zero compensation resistor R1 secures a phase margin of a certain level or more in common with respect to a load capacity of several tens of picofarads to several hundred picofarads has been described. However, you may further provide the 3rd resistance value according to the range of load capacity.

  Regarding the area of the zero compensation resistor, the zero compensation resistor R1 can be formed by an arbitrary resistance element. Therefore, if a high resistance element is used, it can be realized with a smaller area than the phase compensation capacitor C1. Further, when the zero compensation resistor is formed of a transistor, it can be realized with a smaller area than the phase compensation capacitor C1. When the zero compensation resistor is formed of a transistor, the zero compensation resistance value slightly varies according to the output voltage of the amplifier circuit shown in FIG. 1, and the size needs to be taken into consideration.

  Further, regarding noise due to switching of the resistance value of the zero compensation resistor R1, the zero compensation resistor R1 and the phase compensation capacitor C1 of the amplifier circuit of FIG. 1 are connected in series.

  For this reason, in the output stable state of the amplifier circuit, both ends of the zero compensation resistor R1 have the same potential. Even if the resistance value is switched between the same potential terminals, noise hardly occurs in the output signal of the amplifier circuit at the time of switching.

  As described above, the output buffer of the data driver in FIG. 1 realizes a high phase margin by switching the zero compensation resistor R1 to the optimum resistance value according to the periods T1 and T2, and through the periods T1 and T2. A stable operation of the amplifier circuit can be realized. For this reason, the capacitance value of the phase compensation capacitor C1 is reduced, and the area of the amplifier circuit can be reduced. In addition, the power consumption of the amplifier circuit can be reduced. Thereby, area saving, cost reduction, and further power consumption reduction of the data driver of the display device can be realized. A description will be given below in connection with specific examples.

  FIG. 3 is a diagram showing a configuration of an embodiment of the output buffer of the data driver of FIG. FIG. 3 shows a specific configuration of the zero compensation resistor R1 and the control circuit 20 of FIG. Other components are the same as those in FIG.

  Referring to FIG. 3, the zero compensation resistor R1 of FIG. 1 is composed of two resistors R11 and R12 connected in series. The control circuit 20 includes a switch SW1 connected between both ends of the resistor R12. The on / off state of the switch SW1 is controlled by a control signal S2.

  FIG. 4 is a timing chart showing control of the switches SW10 and SW1 by the control signals S1 and S2 in one data period of the output buffer of FIG. One data period includes a period T1 and a period T2.

  In the period T1, the control signals S1 and S2 are controlled to a low level and a high level, respectively, and the output switch SW10 and the switch SW1 are turned off and on, respectively. At this time, the switch SW1 short-circuits both ends of the resistor R12, and the zero compensation resistor is only the resistor R11.

  In the period T2, the control signals S1 and S2 are controlled to a high level and a low level, respectively, and the output switch SW10 and the switch SW1 are turned on and off, respectively. At this time, the zero compensation resistance is a combined resistance of the resistors R11 and R12, and is controlled to be switched to a resistance value higher than the period T1. The resistor R12 may have a positive resistance value, and the resistor R11 may have a resistance value including zero ohms.

  As described above, the output buffer of the data driver in FIG. 3 realizes a high phase margin by switching the zero compensation resistor to the optimum resistance value according to the period T1 and the period T2, and the amplifier circuit of the amplifier circuit through the period T1 and the period T2. Stable operation can be realized. For this reason, the capacitance value of the phase compensation capacitor C1 can be reduced, and the area of the amplifier circuit can be reduced. In addition, the power consumption of the amplifier circuit can be reduced. Thereby, area saving, cost reduction, and further power consumption reduction of the data driver of the display device can be realized.

  FIG. 5 is a diagram showing the configuration of the data driver of the second embodiment of the present invention. In this embodiment, the output buffer of the data driver shown in FIG. 3 is changed. Referring to FIG. 5, in this embodiment, the zero compensation resistors R11 and R12 and the switches SW10 and SW1 shown in FIG. 3 are constituted by transistors. The other components are the same as those shown in FIG.

  In FIG. 5, the switch SW10 is composed of a CMOS switch (CMOS transfer gate), and the control signal S1 and its complementary signal S1B are applied to the gates of the NMOS transistor M31 and the PMOS transistor M32 of the CMOS switch.

  Each of the zero compensation resistors R11 and R12 is composed of a PMOS transistor having a low power supply voltage VSS applied to the gate terminal, and the on-resistance of the PMOS transistor is used as the zero compensation resistor. A bias voltage different from the lower power supply voltage VSS may be applied to the gate terminal.

  Note that the zero compensation resistors R11 and R12 may be composed of CMOS transistors. In the case of the CMOS configuration, the higher power supply voltage VDD is applied to the gate terminal of the NMOS transistor.

  Note that the resistance value of the transistor resistance (the ON resistance of the MOS transistor) varies depending on the output voltage of the amplifier circuit. For this reason, when the transistor resistance is used, the element size and the applied voltage to each control terminal are set so that the change in the transistor resistance value is within the vicinity of the set zero compensation resistance value.

  FIG. 6 is a diagram showing the configuration of the third embodiment of the output buffer of the data driver of FIG. The amplifier circuit of FIG. 6 has a configuration in which the class AB output circuit of FIG. 13 is applied, and the zero compensation resistor and the control circuit 20 have the same configuration as FIG.

  Referring to FIG. 6, the amplifier circuit of FIG. 6 includes a differential input stage, an intermediate stage, and an output stage. The differential input stage includes an N-channel differential pair (M11, M12), a current source M15 having one end connected to the lower power supply VSS and supplying current to the N-channel differential pair (M11, M12), and an N-channel The output pair of the differential pair (M11, M12) and the P-channel current mirror (M13, M14) connected between the higher power supply VDD. The signal voltage Vin is input to the non-inverting input terminal (gate of M12) of the input pair of the N-channel differential pair (M11, M12), and the inverting input terminal (gate of M11) is connected to the amplifier output terminal N11.

  The amplifying stage has a charging operation in which the input ends (connection points of M12 and M14) of the P-channel current mirror (M13, M14) are connected to the gate, and are connected between the high-level power supply VDD and the output end N11 of the amplifier circuit. And an amplifying transistor M18 having a discharging action connected between the output terminal N11 of the amplifier circuit and the lower power supply VSS.

  The intermediate stage includes floating current sources M51 and M52 and current sources M53 and M54. The floating current source M51 includes a P-channel transistor M51 having a gate to which a bias voltage BP1 is input, a source connected to the gate N12 of the amplification transistor M16, and a drain connected to the gate terminal N13 of the amplification transistor M18. The floating current source M52 includes an N-channel transistor M52 having a gate to which a bias voltage BN1 is input, a drain connected to the gate terminal N12 of the amplification transistor M16, and a source connected to the gate terminal N13 of the amplification transistor M18.

  The current source M53 is connected between the high power supply VDD and the gate terminal N12 of the amplification transistor M16. The current source M54 is connected between the lower power supply VSS and the gate terminal N13 of the amplification transistor M18.

  The total current of the floating current source M51 and the floating current source M52 is set to a current substantially equal to each of the current source M53 and the current source M54.

  The amplifier circuit shown in FIG. 6 is an application of the class AB output circuit of FIG. 13, and the driver 89 of FIG. 13 is replaced with a differential input stage. Therefore, the amplifier circuit shown in FIG. 6 also has the characteristics of the class AB output circuit of FIG. That is, since the current values flowing through the floating current sources M81 and M82 in the intermediate stage and the current sources M83 and M84 can be suppressed to be sufficiently small, a high-speed charging operation and a high-speed discharging operation can be realized with a relatively small idling current.

  In the circuit shown in FIG. 6, as in FIG. 3, the zero compensation resistors R11 and R12 and the phase compensation capacitor C1 are connected in series between the gate terminal N12 of the amplification transistor M16 and the output terminal N11 of the amplifier circuit. It is connected. Further, as the control circuit 20, a switch SW1 that short-circuits both ends of the resistor R12 is connected.

  The zero compensation resistors R11 and R12 and the switch SW1 may be configured by transistors as in FIG.

  Further, the relationship between the zero compensation resistance value and the phase margin of the amplifier circuit of FIG. 6 is substantially the same as that of FIG. The relationship between the zero compensation resistance value and the absolute value of the phase margin in each characteristic curve in FIG. 10 varies depending on the amplifier circuit, but the tendency of each characteristic curve described in FIG. 10 is the same.

  Therefore, the output buffer of the data driver shown in FIG. 6 also realizes a high phase margin by switching the zero compensation resistance to the optimum resistance value according to the periods T1 and T2, and through the periods T1 and T2, High-speed stable operation of the amplifier circuit can be realized. For this reason, the capacitance value of the phase compensation capacitor C1 can be reduced, and the area of the amplifier circuit can be reduced. In addition, the power consumption of the amplifier circuit can be reduced. Thereby, area saving, cost reduction, and further power consumption reduction of the data driver of the display device can be realized.

  FIG. 7 is a diagram showing the configuration of the fourth embodiment of the output buffer of the data driver of FIG. FIG. 7 shows a configuration of an output buffer for two outputs of a data driver suitable for liquid crystal driving that performs dot inversion driving.

  Recently, a dot inversion driving method capable of improving image quality has been adopted as a driving method for a large-screen display device such as a liquid crystal television. The dot inversion driving method is a driving method in which the counter substrate electrode voltage VCOM is a constant voltage and the voltage polarities held in adjacent pixels are opposite to each other in the display unit (display panel) 960 in FIG. For this reason, in the same data period, the voltage polarity output to the adjacent data lines (962-1, 962-2) becomes a positive electrode and a negative electrode with respect to the counter substrate electrode voltage VCOM. Also, the polarity of the voltage output to one data line is inverted every predetermined data period.

  Referring to FIG. 7, the output buffer of the present embodiment includes a positive amplifier 110, a negative amplifier 120, and an output switch circuit 130. The positive amplifier 110 amplifies and outputs the positive gradation voltage Vout1 to the amplifier output terminal N11 based on the positive reference voltage V1. The negative amplifier 120 amplifies and outputs the negative gradation voltage Vout2 to the amplifier output terminal N21 based on the negative reference voltage V2. The counter substrate electrode voltage VCOM is a voltage in the vicinity of the middle between the high-potential power supply VDD and the low-potential power supply VSS.

  The positive amplifier 110 has the same configuration as that of the amplifier circuit of FIG. 6, the input voltage Vin is set to the positive reference voltage V1, and the control signal for controlling the switch SW11 is only S21. .

  The negative amplifier 120 is configured to have a polarity opposite to that of the positive amplifier 110. Hereinafter, the negative amplifier will be described.

  The negative amplifier 120 includes a differential input stage, an intermediate stage, and an output stage. The differential input stage includes a P-channel differential pair (M21, M22), a current source M25 having one end connected to the high-order power supply VDD and supplying current to the P-channel differential pair (M21, M22), and a P-channel The output pair of the differential pair (M21, M22) and an N-channel current mirror (M23, M24) connected between the lower power supply VSS. The negative reference voltage V2 is input to the non-inverting input terminal (M22 gate) of the input pair of the P-channel differential pair (M21, M22), and the inverting input terminal (M21 gate) is connected to the amplifier output terminal N21. .

  In the amplification stage, the input end (the connection point of M22 and M24) of the N-channel current mirror (M23, M24) is connected to the gate, and the amplification of the discharge action is connected between the amplifier output terminal N21 and the lower power supply VSS. A transistor M26, and a charging amplification transistor M28 connected between the higher power supply VDD and the amplifier output terminal N21 are provided.

  The intermediate stage includes floating current sources M61 and M62 and current sources M63 and M64. The floating current source M61 includes a P-channel transistor M61 having a gate to which the bias voltage BP2 is input, a drain connected to the gate terminal N22 of the amplification transistor M26, and a source connected to the gate terminal N23 of the amplification transistor M28. The floating current source M62 includes an N-channel transistor M62 having a gate to which the bias voltage BN2 is input, a source connected to the gate terminal N22 of the amplification transistor M26, and a drain connected to the gate terminal N23 of the amplification transistor M28.

  The current source M63 is connected between the high-potential power supply VDD and the gate N23 of the amplification transistor M28. The current source M64 is connected between the gate N22 of the amplification transistor M26 and the low-order power supply VSS.

  The total current of the floating current sources M61 and M62 is set to a current substantially equal to each of the current sources M63 and M64.

  The negative amplifier 120 includes zero compensation resistors R21 and R22 and a phase compensation capacitor C2 connected in series between the gate terminal N22 of the amplification transistor M26 and the amplifier output terminal N21. In addition, a switch SW2 that short-circuits both ends of the resistor R22 by the control signal S22 is connected.

  The output switch circuit 130 includes switches SW11 and SW12 connected between the amplifier output terminal N11 and the driver output terminals P1 and P2, and switches SW21 and SW22 connected between the amplifier output terminal N21 and the driver output terminals P1 and P2. I have. The switches SW11 and SW22 are on / off controlled by a control signal S11, and the switches SW12 and SW21 are on / off controlled by a control signal S12. Adjacent data lines 962-1 and 962-2 are connected to the driver output terminals P1 and P2.

  FIG. 8 is a timing chart showing control of each switch by the control signals S11, S12, S21, and S22 in the first and second data periods of the output buffer of FIG. Each data period consists of at least two periods.

  The first data period is divided into a period T11 and a period T12.

In period T11,
The control signals S11 and S12 are both set to a low level,
The control signals S21 and S22 are both controlled to a high level,
The switches SW11, SW12, SW21, SW22 are all turned off,
Both switches SW1 and SW2 are turned on.

  At this time, the switch SW1 short-circuits both ends of the resistor R12 of the positive amplifier 110, and the zero compensation resistor is only the resistor R11. In addition, the switch SW2 short-circuits both ends of the resistor R22 of the negative amplifier 120, and the zero compensation resistor is only the resistor R21.

In period T12,
The control signals S11 and S12 are controlled to a high level and a low level, respectively.
Switches SW11 and SW22 are on,
The switches SW12 and SW21 are turned off.
The control signals S21 and S22 are both controlled to a low level,
Both switches SW1 and SW2 are turned off.

  At this time, the zero compensation resistance of the positive amplifier 110 is a combined resistance of R11 and R12, and the zero compensation resistance of the negative amplifier 120 is a combined resistance of R21 and R22, and is controlled to have a higher resistance than the period T11. Further, a positive tone signal and a negative tone signal are supplied to the data line 962-1 and the data line 962-2, respectively.

  The second data period is divided into a period T21 and a period T22.

  In the period T21, the same control as in the period T11 is performed.

In period T22,
The control signals S11 and S12 are controlled to low level and high level,
The switches SW11 and SW22 are off,
The switches SW12 and SW21 are turned on.
The control signals S21 and S22 are both controlled to a low level,
Both switches SW1 and SW2 are turned off.

  At this time, the zero point compensation resistances of the positive amplifier 110 and the negative amplifier 120 are controlled to be higher than the period T21. In addition, a negative gradation signal and a positive gradation signal are supplied to the data line 962-1 and the data line 962-2, respectively.

  The positive amplifier 110 and the negative amplifier 120 in FIG. 7 are obtained by applying the class AB output circuit in FIG. 13 to the present invention, similarly to the amplifier circuit in FIG. The positive amplifier 110 and the negative amplifier 120 in FIG. 7 can realize a fast charge operation and a fast discharge operation with a relatively small idling current, as in the amplifier circuit in FIG.

  Further, the positive amplifier 110 and the negative amplifier 120 in FIG. 7 have a relationship between the zero compensation resistance value and the phase margin substantially the same as those in FIG. Therefore, the output buffer of the data driver in FIG. 7 also realizes a high phase margin by switching the zero compensation resistance to the optimum resistance value according to the period T1 and the period T2, and the positive amplifier 110 through the period T1 and the period T2. In addition, high-speed stable operation of the negative amplifier 120 can be realized.

  Therefore, the phase compensation capacitors C1 and C2 can be reduced, and the respective amplifier areas can be reduced. In addition, the power consumption of each amplifier can be reduced. Thereby, area saving, cost reduction, and further power consumption reduction of the data driver of the display device can be realized.

  Note that the positive amplifier 110 and the negative amplifier 120 in FIG. 7 can be replaced with the amplifier circuits in FIGS. Even in such a case, the area and cost of a data driver using the same and the effects described in the drawings can be reduced, and further, the power consumption can be reduced.

  FIG. 9 is a diagram illustrating a configuration of a data driver including the output buffer of FIG. FIG. 9 is a block diagram showing the main part of the data driver.

  Referring to FIG. 9, the data driver includes a latch address selector 81, a latch 82, a level shifter 83, a reference voltage generation circuit 140, positive and negative decoders 111 and 121, positive and negative amplifiers 110 and 120, An output switch circuit 130 is included.

  The latch address selector 81 determines the data latch timing based on the clock signal CLK. The latch 82 latches the video digital data based on the timing determined by the latch address selector 81, and outputs the data to the decoders 111 and 121 all at once via the level shifter 83 according to the STB signal (strobe signal). To do. The latch address selector 81 and the latch 82 are logic circuits, and are generally configured with a low voltage (0 V to 3.3 V).

  The reference voltage generation circuit 140 includes a positive reference voltage generation circuit 112 and a negative reference voltage generation circuit 122. The positive decoder 111 is supplied with the reference voltage of the positive reference voltage generation circuit 112, selects a reference voltage corresponding to the input data, and outputs the selected reference voltage to the positive amplifier 110. The negative decoder 121 is supplied with the reference voltage of the negative reference voltage generation circuit 122, selects a reference voltage corresponding to the input data, and outputs the selected reference voltage to the negative amplifier 120. The positive and negative amplifiers 110 and 120 amplify and output the gradation signals based on the reference voltages output from the positive and negative decoders 111 and 121, respectively, and supply the gradation signals to the output switch circuit 130. The output switch circuit 130 is provided for every even number of driver output terminals P1, P2,..., Ps, and outputs the output voltages of the positive and negative amplifiers 110 and 120 in accordance with the control signals S1 and S2. Switch to 2 terminal and output.

  The data driver shown in FIG. 9 can apply the amplifier circuits shown in FIGS. 1, 3, 5, 6, and 7 to realize area saving (cost reduction) and low power consumption. If the data driver shown in FIG. 9 is used for the data driver 980 of the liquid crystal display device shown in FIG. 11, it is possible to reduce the cost and power consumption of the liquid crystal display device.

  In FIG. 11, when the number of data lines in the display unit 960 is large, the data driver 980 includes a plurality of data driver LSIs. For this reason, some driver output terminals of the end data driver LSI may remain. The amplifier circuit that drives the surplus driver output terminal is preferably stopped, but may be put in an operating state. At this time, the present invention can be applied in order to stably operate the amplifier circuit.

  That is, in the data driver of the present invention, the zero compensation resistor is fixedly controlled to one of the first and second resistance values for the amplifier circuit that drives the driver output terminal to which the data line is not connected. good. In this case, the resistance value of the zero compensation resistor is switched and controlled on a group basis between the first amplifier circuit group to which the data line is connected and the second amplifier circuit group to which the data line is not connected.

  Although the present invention has been described with reference to the above-described embodiments, the present invention is not limited to the configurations of the above-described embodiments, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, including modifications.

According to the present invention, the following configuration is obtained.
(Appendix 1)
A data driver having an amplifier circuit that receives a voltage signal based on input data and amplifies and outputs it to a driver output terminal,
The amplifier circuit includes a phase compensation capacitor and a zero compensation resistor;
A control circuit that switches and controls the resistance value of the zero compensation resistor to one of at least two resistance values different from each other in accordance with a control signal;
A data driver characterized by comprising:
(Appendix 2)
The phase compensation capacitor and the zero compensation resistor are connected in series between one output node of the input differential amplification stage and one output node of the subsequent amplification stage in the amplifier circuit. The data driver according to appendix 1, characterized by:
(Appendix 3)
An output switch connected between the output terminal of the amplifier circuit and the data driver output terminal and controlled to be turned on and off by a second control signal;
The data driver according to claim 1, wherein the control circuit controls switching of a resistance value of the zero compensation resistor in association with turning on and off of the output switch.
(Appendix 4)
When the output switch is off, the control circuit sets the zero compensation resistor to a smaller resistance value between the first resistance value and the second resistance value, which are different from each other.
2. The data driver according to claim 1, wherein when the output switch is on, the zero compensation resistor is switched to a larger resistance value of the first resistance value and the second resistance value.
(Appendix 5)
The control circuit includes a switch transistor that is connected between two voltage dividing nodes including both ends of the zero compensation resistor and that is on / off controlled based on the control signal input to the control end. The data driver according to appendix 1, characterized by:
(Appendix 6)
The zero compensation resistor comprises at least two transistors set in an on state and connected in cascode;
The control circuit includes a cascode-connected switch transistor that is connected in parallel to one of the two transistors and that inputs the control signal to a control terminal. Data driver.
(Appendix 7)
The zero compensation resistor comprises a first resistor and a second resistor connected in series;
The control circuit includes a switch transistor that is connected in parallel to one of the first resistor and the second resistor and that inputs the control signal to a control terminal. The described data driver.
(Appendix 8)
The amplifier circuit is
A differential pair receiving an input signal at a first input;
A first current source connected to a first power source and supplying current to the differential pair;
A load circuit connected between the output pair of the differential pair and a second power supply;
An amplification stage in which an input terminal is connected to at least one of connection nodes between the output pair of the differential pair and the load circuit, and an output terminal is connected to an output terminal of the amplifier circuit;
With
A signal at the output terminal of the amplifier circuit is fed back to the second input of the differential pair,
The additional point 1 is characterized in that the zero compensation resistor and the phase compensation capacitor are connected in series between an output terminal of the amplifier circuit and a connection node between the amplifier stage and the load circuit. Data driver.
(Appendix 9)
The amplification stage has a connection node between the output pair of the differential pair and the load circuit connected to a control terminal, a first output transistor connected between a second power supply and the output terminal, and the output terminal And a second current source connected between the first power supply and the data driver according to appendix 8.
(Appendix 10)
A second current source connected between the first power source and a first node;
A floating current source circuit connected between the first node and the second node;
A third current source connected between the second node and the second power source;
A first output transistor connected between the second power supply and the output terminal, a connection node between the output pair of the differential pair and the load circuit, and a control terminal connected to the second node;
A second output transistor connected between the first power supply and the output terminal and having a control terminal connected to the first node;
The data driver according to appendix 8, characterized by comprising:
(Appendix 11)
The amplifier circuit is
A first differential pair receiving a first input signal at a first input;
A first current source connected to a first power supply and supplying a current to the first differential pair;
A first load circuit connected between an output pair of the first differential pair and a second power source;
An input terminal is connected to at least one of connection nodes between the output pair of the first differential pair and the first load circuit, and an output terminal is connected to a first output terminal of the amplifier circuit. Amplification stage,
With
A signal at the first output terminal of the amplifier circuit is fed back to the second input of the first differential pair,
The first set of the zero compensation resistor and the phase compensation capacitor is connected in series between the output terminal of the amplifier circuit and a connection node between the first amplifier stage and the first load circuit. And
A second differential pair receiving a second input signal at the first input;
A second current source connected to the second power source and supplying a current to the second differential pair;
A second load circuit connected between the output pair of the second differential pair and the first power supply;
An input terminal is connected to at least one of connection nodes between the output pair of the second differential pair and the second load circuit, and an output terminal is connected to a second output terminal of the amplifier circuit. Amplification stage,
With
A signal of the second output terminal of the amplifier circuit is fed back to the second input of the second differential pair,
The second set of the zero compensation resistor and the phase compensation capacitor is connected in series between the output terminal of the amplifier circuit and a connection node between the second amplifier stage and the second load circuit. And
The control circuit switches and controls the resistance value of the zero compensation resistor of the first set to a first resistance value or a second resistance value different from the first resistance value according to a control signal,
The resistance value of the zero compensation resistor of the second set is controlled to be switched to a third resistance value or a fourth resistance value different from the third resistance value according to a second control signal. The data driver according to appendix 1, which is characterized.
(Appendix 12)
A first output switch connected between a first output terminal of the amplifier circuit and a first driver output terminal;
A second output switch connected between a second output terminal of the amplifier circuit and a second driver output terminal;
A third output switch connected between the first output terminal of the amplifier circuit and the second driver output terminal;
A fourth output switch connected between the second output terminal of the amplifier circuit and the first driver output terminal;
The data driver according to appendix 11, characterized by comprising:
(Appendix 13)
A third current source connected between the first power source and the first node;
A first floating current source circuit connected between the first node and the second node;
A fourth current source connected between the second node and a second power source;
A control terminal is connected between the second power source and the first output terminal, a connection node between the output pair of the first differential pair and the first load circuit, and the second node. A first output transistor;
A second output transistor connected between the first power supply and the first output terminal and having a control terminal connected to the first node;
A fifth current source connected between the second power source and a third node;
A second floating current source circuit connected between the third node and the fourth node;
A sixth current source connected between the fourth node and the first power source;
A third output transistor connected between the second power supply and the second output terminal and having a control terminal connected to the third connection node;
A control terminal is connected between the first power supply and the second output terminal, and a connection node between the output pair of the second differential pair and the second load circuit and the fourth node. A fourth output transistor;
The data driver according to appendix 11, characterized by comprising:
(Appendix 14)
With multiple driver output terminals,
A plurality of amplifier circuits corresponding to each of the plurality of driver output terminals;
The plurality of amplifier circuits are grouped into at least a first group and a second group,
The data driver according to claim 1, wherein the plurality of amplifier circuits are switched in resistance value of the zero compensation resistor for each group.
(Appendix 15)
Multiple amplifier circuits connected to the driver output terminal to which the data line is connected form a group,
The one or more amplifier circuits connected to the driver output terminal not connected to the data line form a group different from the one group, and the resistance value of the zero compensation resistor is switched for each group. The data driver according to appendix 1, which is characterized.
(Appendix 16)
A differential amplifier circuit having a zero compensation resistor in series with a phase compensation capacitor between one output node of the first stage of the differential amplification and a predetermined output node of the subsequent amplification stage,
A differential amplifier circuit comprising a control circuit that variably controls a resistance value of the zero compensation resistor in accordance with a control signal.
(Appendix 17)
The supplementary note 16 is characterized in that the control circuit switches the resistance value of the zero compensation resistor between large and small in accordance with the magnitude of the load capacitance connected to the output terminal of the differential amplifier circuit based on the control signal. Differential amplifier circuit.
(Appendix 18)
18. A data driver comprising the differential amplifier circuit according to appendix 16 or 17.
(Appendix 19)
A display device comprising a unit pixel including a pixel switch and a display element at an intersection of a data line and a scanning line, wherein a signal of the data line is written to the display element through a pixel switch turned on by the scanning line. ,
A plurality of the driver output terminals are connected corresponding to the plurality of data lines, and the data driver according to any one of appendices 1 to 15 and 18 is provided as a data driver for driving the plurality of data lines. Display device.
(Appendix 20)
A plurality of data lines extending parallel to each other in one direction;
A plurality of scanning lines extending in parallel with each other in a direction orthogonal to the one direction;
A plurality of pixel electrodes arranged in a matrix at intersections of the plurality of data lines and the plurality of scanning lines;
With
Corresponding to each of the plurality of pixel electrodes, one input of a drain and a source is connected to the corresponding pixel electrode,
A plurality of transistors, wherein the other input of the drain and source is connected to the corresponding data line, and a gate is connected to the corresponding scan line;
A gate driver for supplying a scanning signal to each of the plurality of scanning lines;
A data driver for supplying gradation signals corresponding to input data to the plurality of data lines;
With
The display device comprising the data driver according to any one of appendices 1 to 7, wherein a plurality of driver output terminals are connected corresponding to the plurality of data lines. .

1 to 10, 14, 15, 15 ', 16, 16' MOS transistor 11 Terminal 12 Power supply line (+)
13 Power line (-)
20 control circuit 81 latch address selector 82 latch 83 level shifter 89 driver 90 output buffer (amplifier circuit)
DESCRIPTION OF SYMBOLS 110 Positive amplifier 111 Positive decoder 112 Positive reference voltage generation circuit 120 Negative amplifier 121 Negative decoder 122 Negative reference voltage generation circuit 130 Output switch circuit 140 Reference voltage generation circuit 950 Display controller 960 Display part 961 Scan line 962, 962-1, 962- 2 Data line 963 Thin film transistor (TFT)
964 Pixel electrode 965 Liquid crystal capacitance 966 Auxiliary capacitance 967 Transparent electrode (counter substrate electrode)
970 Gate driver 980 Data driver C1 Phase compensation capacitor BN1, BN2, BP1, BP2 Bias voltage M11, M12, M31, M18, M23, M24, M26, M31, M86 N-channel transistors M13, M14, M16, M21, M22, M28 M32, M85 P-channel transistor M15, M17, M53, M54, M83, M84 Current source M51, M61, M81 Floating current source (P-channel transistor)
M52, M62, M82 Floating current source (N-channel transistor)
N11, N21 Amplifier circuit output terminal P01 Data driver output terminal R11, R12 Zero compensation resistor S1, S2, S11, S12, S21, S22 Control signal SW10 Output switch SW1 Switch SW11, SW12, SW21, SW22 Switch V1 Positive reference voltage V1 Negative Reference voltage Vin Input signal Vout Output signal of amplifier circuit

Claims (9)

A data driver having an amplifier circuit that receives a voltage signal based on input data and amplifies and outputs it to a driver output terminal,
A plurality of the amplifier circuit and the driver output terminal, respectively,
The amplifier circuit is
An input differential stage;
An amplification stage that amplifies and outputs to the output terminal of the amplification circuit based on the output of the input differential stage;
A phase compensation capacitor and a zero compensation resistor connected between one output node of the input differential stage and an output terminal of the amplification stage;
A control circuit that switches and controls the resistance value of the zero compensation resistor to one of at least two resistance values different from each other in accordance with a control signal;
With
The plurality of amplifier circuits and the driver output terminals are divided into at least a first group and a second group,
A data driver, wherein the plurality of amplifier circuits are switched in resistance values of the zero compensation resistors which are different for each group. A plurality of the amplifier circuits and the driver output terminals forming the first group are connected to data lines of the driver output terminals,
2. The data driver according to claim 1, wherein a data line is not connected to the driver output terminal of the one or more amplifier circuits and the driver output terminal forming the second group. The amplifier circuit is
An output switch connected between the output terminal of the amplification stage and the data driver output terminal and controlled to be turned on and off by a second control signal;
One data period corresponding to the input data includes a first period and a second period after the first period,
The output switch is turned off in the first period and turned on in the second period;
The data driver according to claim 1, wherein the control circuit controls switching of a resistance value of the zero compensation resistor in association with ON / OFF of the output switch. The amplifier circuit of the first group includes:
In the first period, the zero compensation resistance is set to a smaller resistance value of the first resistance value and the second resistance value,
In the first period, the zero compensation resistor is controlled to be switched to a larger resistance value between the first resistance value and the second resistance value,
The amplifier circuits of the second group are:
4. The data driver according to claim 3, wherein the zero compensation resistor is fixedly controlled to one of the first resistance value and the second resistance value throughout the one data period.   The control circuit includes a switch transistor that is connected between two voltage dividing nodes including both ends of the zero compensation resistor and that is on / off controlled based on the control signal input to the control end. The data driver according to any one of claims 1 to 4, wherein: The zero compensation resistor comprises at least two transistors set in an on state and connected in cascode;
The control circuit includes a cascode-connected switch transistor connected in parallel to one of the two transistors and inputting the control signal to a control terminal. The data driver according to any one of 1 to 4. The zero compensation resistor comprises a first resistor and a second resistor connected in series;
The control circuit includes a switch transistor that is connected in parallel to one of the first resistor and the second resistor and that inputs the control signal to a control terminal. The data driver according to 1 to 4. A display device comprising a unit pixel including a pixel switch and a display element at an intersection of a data line and a scanning line, wherein a signal of the data line is written to the display element through a pixel switch turned on by the scanning line. ,
A display including the data driver according to claim 1, wherein a plurality of the driver output terminals are connected corresponding to the plurality of data lines, and the data driver drives the plurality of data lines. apparatus. A plurality of data lines extending parallel to each other in one direction;
A plurality of scanning lines extending in parallel with each other in a direction orthogonal to the one direction;
A plurality of pixel electrodes arranged in a matrix at intersections of the plurality of data lines and the plurality of scanning lines;
With
Corresponding to each of the plurality of pixel electrodes, one input of a drain and a source is connected to the corresponding pixel electrode,
A plurality of transistors, wherein the other input of the drain and source is connected to the corresponding data line, and a gate is connected to the corresponding scan line;
A gate driver for supplying a scanning signal to each of the plurality of scanning lines;
A data driver for supplying gradation signals corresponding to input data to the plurality of data lines;
With
The display comprising the data driver according to claim 1, wherein a plurality of driver output terminals are connected corresponding to the plurality of data lines. apparatus.

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