KR102680692B1 - Data Driver and Display Apparatus including the Data Driver - Google Patents

Abstract

A display device according to an embodiment of the present invention includes a display panel that displays an image, and a data driver that supplies a data voltage through a data line connected to the display panel, and the data driver precharges an internal node based on the data voltage. After that, the data voltage is output through the data line connected to the display panel.

Description

Data driver and display apparatus including the data driver}

The present invention relates to a data driver and a display device including the same.

As information technology develops, the market for display devices, which are a connecting medium between users and information, is growing. Accordingly, the use of display devices such as Organic Light Emitting Display Apparatus (OLED), Quantum Dot Display Apparatus (QDD), and Liquid Crystal Display Apparatus (LCD) is increasing. .

The display devices may include a display panel including subpixels, a driver that outputs a driving signal to drive the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

The above display devices display images by transmitting light or emitting light directly when driving signals, such as scan signals and data signals, are supplied to the subpixels formed on the display panel. It becomes possible.

Some of the above display devices have many advantages, such as electrical and optical characteristics such as fast response speed, high brightness, and wide viewing angle, as well as mechanical characteristics that can be implemented in a flexible form. However, when implementing a high-resolution display device, improvements are needed to smoothly apply the data voltage.

The present invention provides a data driver suitable for high resolution by improving slew-rate characteristics when outputting a data voltage, and a display device including the same.

A display device according to an embodiment of the present invention includes a display panel that displays an image, and a data driver that supplies a data voltage through a data line connected to the display panel, and the data driver operates an internal node based on the data voltage. After pre-charging, the data voltage is output through the data line connected to the display panel.

In addition, a display device according to an embodiment of the present invention includes a display panel that displays an image, an output buffer unit that buffers the data voltage to be supplied to the display panel, and an output unit that controls the output of the data voltage transmitted from the output buffer unit. It includes a data driver having a switch unit, and the data voltage is precharged at an internal node by an output buffer unit and then output through a turned-on output switch unit.

In addition, the data driver according to an embodiment of the present invention includes a data latch unit that latches the data signal, a decoder unit that converts the data signal output from the data latch unit into a data voltage and outputs it, and an output from the decoder unit. It includes an output buffer unit that precharges and buffers the internal node based on the data voltage, and an output switch unit that controls the output of the data voltage output from the output buffer unit.

The present invention has the effect of providing a display device suitable for high resolution by improving the slew rate characteristics when outputting a data voltage. Additionally, the present invention has the effect of improving display quality by improving slew rate characteristics. Additionally, the present invention has the effect of reducing the possibility of slew rate deviation between output channels.

The effects of the present specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

Since the content of the invention described in the problem to be solved, the means for solving the problem, and the effect described above do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the invention.

1 is a block diagram schematically showing a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram schematically showing the subpixel shown in FIG. 1.
Figure 3 is a block diagram schematically showing an organic light emitting display device according to an embodiment of the present invention.
FIG. 4 is a diagram schematically showing the configuration of the subpixel shown in FIG. 3.
Figure 5 is a diagram showing the arrangement of a gate-in-panel scan driver according to an embodiment of the present invention.
Figure 6 is a diagram showing the first configuration of a device related to a gate-in-panel type scan driver.
Figure 7 is a diagram showing a second configuration of a device related to a gate-in-panel type scan driver.
Figure 8 is a diagram showing the first configuration of a device related to a data driver according to the first embodiment of the present invention.
FIG. 9 is a diagram showing a second configuration of a device related to a data driver according to the first embodiment of the present specification.
10 and 11 are diagrams for explaining the device configuration and operation of the data driver according to the first embodiment of the present specification.
Figure 12 is a diagram showing slew rate waveform characteristics when outputting a data voltage according to the first embodiment.
Figure 13 is a diagram for comparing and explaining the slew rate waveform characteristics when outputting the data voltage of the experimental example and the first embodiment.
Figure 14 is a diagram showing the device configuration of the data driver according to the second embodiment of the present invention.
Figure 15 is a diagram showing the device configuration of the data driver according to the third embodiment of the present invention.

Hereinafter, specific details for implementing the present invention will be described with reference to the attached drawings.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms, and only the present embodiments make the disclosure of the present invention complete, and are known to those skilled in the art in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shape, area, ratio, angle, number, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'comprises', 'has', 'consists of', etc. mentioned in the present invention are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., 'immediately' or 'directly' Unless used, non-consecutive cases may also be included.

When an element or layer is referred to as “on” another element or layer, it includes instances where the other layer or other element is directly on top of or interposed between the other elements.

Additionally, first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

In describing the components of this specification, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be directly connected or connected to that other component, but there are no other components between each component. It should be understood that may be “interposed” or that each component may be “connected,” “combined,” or “connected” through other components.

Like reference numerals refer to like elements throughout the specification.

The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the area and thickness of the components shown.

Each feature of the various embodiments of the present invention can be combined or combined with each other partially or entirely, and various technical interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. It may be possible.

In this specification, “display device” refers to a liquid crystal module (LCM), an organic light emitting module (OLED module), and a quantum dot module including a display panel and a driver for driving the display panel. It may include a display device. And, electronic devices including laptop computers, televisions, computer monitors, automotive displays, or other types of vehicles that are complete products or final products including LCM, OLED, and QD modules. It may also include a set electronic device or set apparatus, such as an equipment display, a mobile electronic device such as a smartphone, or an electronic pad.

Accordingly, the display device in this specification may include the display device itself in a narrow sense, such as an LCM, OLED, QD module, etc., and a set device that is an application product or end-consumer device including an LCM, OLED, QD module, etc.

And, in some cases, the LCM, OLED, and QD modules consisting of the display panel and driving unit are expressed as a “display device” in the narrow sense, and the electronic device as a finished product including the LCM, OLED, and QD modules is a “set device.” It can also be expressed separately. For example, a display device in the narrow sense includes a display panel of liquid crystal (LCD), organic light emitting (OLED), or quantum dot (Quantum Dot), and a source PCB, which is a control unit for driving the display panel, and the set device is connected to the source PCB. It may be a concept that further includes a set PCB, which is a set control unit that is electrically connected and controls the entire set device.

The display panel used in this embodiment is of all types, such as a liquid crystal display panel, an organic light emitting diode (OLED) display panel, a quantum dot display panel (QD), and an electroluminescent display panel. A display panel may be used. Also, the display panel used in the display device according to the embodiment of the present specification is not limited to the shape or size of the display panel.

FIG. 1 is a block diagram schematically showing a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is a circuit diagram schematically showing the subpixel shown in FIG. 1.

As shown in Figures 1 and 2, the liquid crystal display device includes an image supply unit 110, a timing control unit 120, a scan driver 130, a data driver 140, a display panel 150, and a backlight unit 170. and a power supply unit 180.

The image supply unit 110 (or host system) outputs various driving signals in addition to image data signals supplied from the outside or image data signals stored in internal memory. The image supply unit 110 supplies data signals and various driving signals to the timing control unit 120.

The timing control unit 120 includes a gate timing control signal (GDC) for controlling the operation timing of the scan driver 130, a data timing control signal (DDC) for controlling the operation timing of the data driver 140, and various synchronization signals ( Outputs the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync). The timing control unit 120 supplies the data signal DATA supplied from the image supply unit 110 along with the data timing control signal DDC to the data driver 140. The timing control unit 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited to this.

The scan driver 130 outputs a scan signal (or scan voltage) in response to a gate timing control signal (GDC) supplied from the timing controller 120. The scan driver 130 supplies scan signals to subpixels included in the display panel 150 through scan lines GL1 to GLm. The scan driver 130 may be formed in the form of an IC or directly on the display panel 150 using a Gate In Panel (GIP) method, but is not limited thereto.

The data driver 140 samples and latches the data signal (DATA) in response to the data timing control signal (DDC) supplied from the timing control unit 120 and converts the digital data signal into analog data based on the gamma reference voltage. Converts to voltage and outputs. The data driver 140 supplies data voltage to subpixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

The power supply unit 180 generates and outputs a common voltage (VCOM) based on an external input voltage supplied from the outside. The power supply unit 180 includes not only the common voltage (VCOM) but also the voltage required to drive the scan driver 130 (e.g., scan high voltage, scan low voltage) or the voltage required to drive the data driver 140 (drain voltage, half voltage). drain voltage), etc. can be generated and output.

The display panel 150 displays an image in response to a scan signal supplied from the scan driver 130, a data voltage supplied from the data driver 140, and a common voltage (VCOM) supplied from the power supply unit 180. Subpixels of the display panel 150 control light provided through the backlight unit 170.

For example, one subpixel (SP) includes a switching transistor (SW), a storage capacitor (Cst), and a liquid crystal layer (Clc). The gate electrode of the switching transistor (SW) is connected to the scan line (GL1) and the source electrode is connected to the data line (DL1). The storage capacitor (Cst) has one end connected to the drain electrode of the switching transistor (SW) and the other end connected to the common voltage line (Vcom). The liquid crystal layer Clc is formed between the pixel electrode 1 connected to the drain electrode of the switching transistor SW and the common electrode 2 connected to the common voltage line Vcom.

The display panel 150 operates in TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, and FFS (Fringe Field Switching) mode depending on the structure of the pixel electrode (1) and common electrode (2). Alternatively, it is implemented in ECB (Electrically Controlled Birefringence) mode.

The backlight unit 170 provides light to the display panel 150 using a light source that emits light. The backlight unit 170 includes a light emitting diode (hereinafter referred to as LED), an LED driver that drives the LED, an LED substrate on which the LED is mounted, a light guide plate that converts the light emitted from the LED into a surface light source, a reflector that reflects light from the bottom of the light guide plate, It may include, but is not limited to, optical sheets that collect and diffuse the light emitted from the light guide plate.

FIG. 3 is a block diagram schematically showing an organic light emitting display device according to an embodiment of the present invention, and FIG. 4 is a configuration diagram schematically showing the subpixel shown in FIG. 3.

As shown in FIGS. 3 and 4, the organic light emitting display device includes an image supply unit 110, a timing control unit 120, a scan driver 130, a data driver 140, a display panel 150, and a power supply unit ( 170), etc. are included.

Since the image supply unit 110, timing control unit 120, scan driver 130, data driver 140, etc. included in the organic electroluminescent display device have similar basic configuration and operation to the liquid crystal display device, detailed description will be omitted. .

The power supply unit 180 generates and outputs a high-potential first power source (EVDD) and a low-potential second power source (EVSS) based on an external input voltage. The power supply unit 180 provides not only the first and second power supplies (EVDD, EVSS) but also the voltage (e.g., scan high voltage, scan low voltage) required to drive the scan driver 130 or the data driver 140. Voltages (drain voltage, half-drain voltage), etc. can be generated and output.

The display panel 150 is configured to receive a driving signal including a scan signal and a data voltage output from a driving unit including the scan driving unit 130 and a data driving unit 140, and first and second power outputs from the power supply unit 170 ( Displays images in response to EVDD, EVSS). Subpixels of the display panel 150 directly emit light. The display panel 150 may be manufactured based on a rigid or flexible substrate such as glass, silicon, or polyimide. And the subpixels that emit light may be composed of pixels containing red, green, and blue, or pixels containing red, green, blue, and white.

For example, one subpixel (SP) includes a pixel circuit (PC) including a switching transistor (SW), a driving transistor, a storage capacitor, and an organic light emitting diode. The subpixel (SP) used in organic light emitting displays emits light directly, so the circuit configuration is more complicated than that of liquid crystal displays. In addition, compensation circuits that compensate for the deterioration of organic light-emitting diodes that emit light as well as driving transistors that supply driving current to the organic light-emitting diodes are complex and diverse. Therefore, please refer to the fact that the pixel circuit (PC) included in the subpixel (SP) is shown in block form.

Meanwhile, the timing control unit 120, scan driver 130, and data driver 140 described in FIGS. 1 and 3 may be defined as a panel driver for driving the display panel 150. The panel driver may be implemented in the form of an IC including a timing control unit 120, a scan driver 130, and a data driver 140. However, this only applies when the display device is implemented in a small or medium size. In contrast, when the display device is implemented in a large size, the timing control unit 120, scan driver 130, and data driver 140 are each implemented in IC form.

Figure 5 is a diagram showing the arrangement of a gate-in-panel scan driver according to an embodiment of the present invention, Figure 6 is a diagram showing the first configuration of a device related to the gate-in-panel scan driver, and Figure 7 is a gate-in-panel scan driver. This is a diagram showing the second configuration of a device related to the method scan driver.

As shown in FIG. 5, the gate-in-panel scan drivers 130a and 130b are disposed in the non-display area NA of the display panel 150. The scan drivers 130a and 130b may be disposed in the left and right non-display areas (NA) of the display panel 150, as shown in FIG. 5(a). Additionally, the scan drivers 130a and 130b may be disposed in the upper and lower non-display areas NA of the display panel 150, as shown in FIG. 5(b).

The scan drivers 130a and 130b are shown and explained as an example of being arranged in pairs in the non-display area (NA) located on the left and right or above and below the display area (AA), but only one is placed on the left, right, top or bottom. It may be, but is not limited to this.

As shown in FIG. 6, the gate-in-panel scan driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 generates and outputs a plurality of clock signals (CLK) and a start signal (VST) based on the signal output from the timing control unit 120. The clock signal (CLK) may be generated and output in the form of K (K is an integer greater than 2) with different phases, such as 2-phase, 4-phase, and 8-phase.

The shift register 131 operates based on signals (CLK, VST) output from the level shifter 135, and scan signals (turn-off) that can turn on or turn off the transistor formed in the display panel. Scan [1] ~ Scan [m]) is output. The shift register 131 is formed in the form of a thin film on the display panel using the gate-in-panel method. Accordingly, the part of the scan driver 130 formed on the display panel corresponds to the shift register 131 (parts 130a and 130b in FIG. 5 correspond to 131).

Unlike the shift register 131, the level shifter unit 135 is formed in the form of an IC. Accordingly, the level shifter unit 135 may be configured in the form of a separate IC as shown in FIG. 6, and may be included inside the power supply unit 180 or another device as shown in FIG. 7.

FIG. 8 is a diagram showing a first configuration of a device related to a data driver according to a first embodiment of the present invention, and FIG. 9 is a diagram showing a second configuration of a device related to a data driver according to the first embodiment of the present invention. am.

As shown in FIG. 8, the data driver 140 includes a drive control unit 141, a shift register unit 142, a first data latch unit 143, a second data latch unit 145, and a decoder unit 147. , includes an output buffer unit 148 and an output switch unit 149.

The driving control unit 141 includes a shift register unit 142, a first data latch unit 143, a second data latch unit 145, a decoder unit 147, an output buffer unit 148, and an output switch unit 149. Control at least one of the The drive control unit 141 generates and outputs signals for controlling devices included within the data drive unit 140.

The shift register unit 142 starts operation in response to a data timing control signal supplied from the timing control unit and applies a horizontal clock signal, etc. to at least one of the first data latch unit 143 and the second data latch unit 145. do.

The first data latch unit 143 receives data signals supplied from the timing control unit and sequentially stores the input data signals. The first data latch unit 143 can store one line worth of data signals. The second data latch unit 145 temporarily stores one line worth of data signals transmitted from the first data latch unit 143 and then simultaneously outputs them.

The decoder unit 147 receives one line worth of data signals from the second data latch unit 145 and converts the digital data signal into an analog data voltage based on a gamma reference voltage applied from the outside. The decoder unit 147 includes an analog-to-digital converter that can convert digital signals into analog signals.

The output buffer unit 148 buffers the data voltage transmitted from the decoder unit 147. The output buffer unit 148 may be comprised of an operational amplifier and may buffer a data voltage based on a bias voltage.

The output switch unit 149 outputs the data voltage present in the output buffer unit 148 to the display panel 150. The output switch unit 149 outputs a data voltage through the data line of the display panel 150. The output switch unit 149 is located between the output buffer unit 148 and the data line of the display panel 150. The output switch unit 149 is turned on or off in response to the logic state of the output activation signal output from the drive control unit 141.

As shown in FIG. 9, the data driver 140 includes a drive control unit 141, a shift register unit 142, a first data latch unit 143, a second data latch unit 145, and a level shifter unit 146. ), a decoder unit 147, an output buffer unit 148, and an output switch unit 149.

The driving control unit 141 includes a shift register unit 142, a first data latch unit 143, a second data latch unit 145, a decoder unit 147, an output buffer unit 148, and an output switch unit 149. Control at least one of the The drive control unit 141 generates and outputs signals for controlling devices included within the data drive unit 140.

The shift register unit 142 starts operation in response to a data timing control signal supplied from the timing control unit and applies a horizontal clock signal, etc. to at least one of the first data latch unit 143 and the second data latch unit 145. do.

The first data latch unit 143 receives data signals supplied from the timing control unit and sequentially stores the input data signals. The first data latch unit 143 can store one line worth of data signals. The second data latch unit 145 temporarily stores one line worth of data signals transmitted from the first data latch unit 143 and then simultaneously outputs them.

The level shifter unit 146 receives one line worth of data signals from the second data latch unit 145 and adjusts the level into a signal that the decoder unit 147 can recognize. The level shifter 146 may be provided only when the data signal output from the timing control unit is weakly transmitted.

The decoder unit 147 receives one line worth of data signals from the level shifter unit 146 and converts the digital data signal into an analog data voltage based on a gamma reference voltage applied from the outside. The decoder unit 147 includes an analog-to-digital converter that can convert digital signals into analog signals.

The output buffer unit 148 buffers the data voltage transmitted from the decoder unit 147. The output buffer unit 148 may be comprised of an operational amplifier and may buffer a data voltage based on a bias voltage.

The output switch unit 149 outputs the data voltage present in the output buffer unit 148 to the display panel 150. The output switch unit 149 outputs a data voltage through the data line of the display panel 150. The output switch unit 149 is turned on or off in response to the logic state of the output activation signal output from the drive control unit 141.

The data driver 140, which supplies data voltage to the display panel 150 in the display device, may be configured as shown in Figure 8 or Figure 9, but the present invention is not limited thereto.

Meanwhile, with the development of display devices, high resolution is required. The biggest issue in implementing high-resolution display devices is the reduction in data voltage writing time due to increased resolution. Since the data voltage writing time is inversely proportional to the amount of data voltage to be displayed, it decreases as the resolution increases. To overcome this, it is necessary to improve the slew-rate characteristics related to the data voltage output of the data driver.

The slew rate characteristic is expressed as the time until the output of the data driver changes from the previous value to the current value, and can be determined by the current supplied by the data driver and the output load value.

Accordingly, in order to improve slew rate characteristics, the present invention arranges the output switch unit 149 at the rear of the output buffer unit 148 between the data driver and the output load. Additionally, the slew rate characteristics are improved by controlling the activation time (driving time) of the output buffer unit 148 and the activation time (driving time) of the output switch unit 149.

FIGS. 10 and 11 are diagrams for explaining the device configuration and operation within the data driver according to the first embodiment of the present invention, and FIG. 12 is a waveform showing slew rate characteristics when outputting a data voltage according to the first embodiment. 13 is a waveform diagram for comparing and explaining the slew rate characteristics when outputting the data voltage of the experimental example and the first embodiment.

10 to 12, the data driver 140 according to the first embodiment of the present invention includes a drive control unit 141, a first data latch unit 143, a second data latch unit 145, It includes a level shifter unit 146, a decoder unit 147, an output buffer unit 148, and an output switch unit 149.

The data signal (DATA) input from the timing control unit is stored in the first data latch unit 143 in response to the first activation signal (EN1) and the second activation signal (EN2) output from the driving control unit 141. 2 is stored in the data latch unit 145. DATA_1 refers to the first data signal output from the first data latch unit 143, and DATA_2 refers to the second data signal output from the second data latch unit 145. The second data signal corresponds to a data signal applied before the first data signal.

The data signal output from the second data latch unit 145 passes through the level shifter unit 146 and the decoder unit 147 and is then converted into a data voltage. SD_IN shows the form in which the data voltage output from the decoder unit 147 is applied to the input terminal of the output buffer unit 148.

The output buffer unit 148 precharges the internal node from the point when the output activation signal (SD_OUT_EN) controlling the output switch unit 149 maintains logic low or the output switch unit 149 is turned off. -charging). The output activation signal (SD_OUT_EN) is output from the drive control unit 141.

When the output switch unit 149 is turned off, the output buffer unit 148 retains the previous data voltage value until the next data voltage is input. The output switch unit 149 is turned off when it outputs the current data voltage. Accordingly, the time when the output activation signal (SD_OUT_EN) maintains a logic low or the time when the output switch unit 149 is turned off can be defined as after outputting the previous data voltage.

The voltage required for pre-charging is based on the data voltage output from the decoder unit 147. That is, the output buffer unit 148 pre-charges the internal node with the data voltage to be currently supplied. Thereafter, when the output activation signal (SD_OUT_EN) changes to logic high, the output switch unit 149 outputs the data voltage through the output terminal (S_OUT) of the output switch unit 149. The output terminal (S_OUT) of the output switch unit 149 corresponds to the output channel of the data driver.

Refer to FIG. 10 for the turn-off state of the output switch unit 149, and refer to FIG. 11 for the turn-on state of the output switch unit 149. And within 1 horizontal time (1 Hsync Time), the state of the output activation signal (SD_OUT_EN) for pre-charging of the output buffer unit 148, and the change in the input terminal (SD_IN) of the output buffer unit 148. , Refer to the waveform in FIG. 12 for changes in the output terminal (A Node) of the output buffer unit 148 and changes in the data voltage and slew rate output through the output terminal (S_OUT) of the output switch unit 149. do.

As can be seen through changes in the data voltage applied to the input terminal (SD_IN) of the output buffer unit 148, the output terminal (A Node) of the output buffer unit 148, and the output terminal (S_OUT) of the output switch unit 149 in FIG. , The first embodiment of the present invention can improve slew-rate characteristics compared to the experimental example.

The first embodiment of the present invention adds the output switch unit 149, and output buffer unit 148 uses the current data voltage from the point in time when the output activation signal (SD_OUT_EN) is not applied (or when the output switch part is turned off). ) nodes are pre-charged and then output. That is, in the first embodiment, the output switch unit 149 is turned off and a small load is applied to the output terminal (A Node) of the output buffer unit 148, so the data voltage is output with a fast slew rate characteristic. You can prepare. The first embodiment precharges the node of the output buffer unit 148 and then turns on the output switch unit 149 to output the data voltage, thereby reducing the source delay time (SDT). You can control it.

On the other hand, in the experimental example, the output buffer unit 148 cannot be pre-charged because the output switch unit does not exist. In an experimental example in which the output switch unit 149 is not provided, when the node of the output buffer unit 148 is pre-charged, the data voltage may leak through the data line of the display panel or the current data voltage may be reduced. This may have an undesirable effect on previously written data voltages.

FIG. 14 is a device configuration diagram of a data driver according to a second embodiment of the present invention, and FIG. 15 is a device configuration diagram of a data driver according to a third embodiment of the present invention.

As shown in FIG. 14, the data driver 140 according to the second embodiment of the present invention includes a drive control unit 141, a first data latch unit 143, a second data latch unit 145, and a level shifter unit. 146, a decoder unit 147, an output buffer unit 148, and an output switch unit 149.

The data driver 140 according to the second embodiment is similar to the first embodiment, but has a separate pre-charging voltage (Vpre) between the output terminal (A Node) of the output buffer unit 148 and the input terminal of the output switch unit 149. ) is different in that it is approved. The precharging voltage Vpre may be set to the common voltage value (or intermediate gray level value) of the data voltage to be output through all output channels of the data driver 140.

Since the precharging voltage (Vpre) is set to the common voltage value (or intermediate gray level value) of the data voltage to be output through all output channels, it can be implemented to be output from the decoder unit 147 under the control of the drive control unit 141. It is not limited to this.

In this way, a separate pre-charging voltage (Vpre) is applied to the output terminal (A Node) of the output buffer unit 148 and the input terminal of the output switch unit 149 in the turn-on section of the output switch unit 149 where no data voltage is output. If applied in between, faster charging occurs. Therefore, the second embodiment can charge faster than the first embodiment, and thus the slew rate characteristics can be further improved. Additionally, the slew rate characteristics of all output channels of the data driver 140 can be averaged, thereby reducing the possibility of slew rate deviation between output channels.

As shown in FIG. 15, the data driver 140 according to the third embodiment of the present invention includes a drive control unit 141, a first data latch unit 143, a second data latch unit 145, and a level shifter unit. 146, a decoder unit 147, an output buffer unit 148, a precharge switch 144, and an output switch unit 149.

The data driver 140 according to the third embodiment is similar to the first embodiment, but a separate pre-charging voltage (Vpre) is provided between the output terminal (A Node) of the output buffer unit 148 and the input terminal of the output switch unit 149. ) is different in that it is approved. Another difference is that a pre-charge switch 144 is added to apply a separate pre-charging voltage (Vpre). The precharge switch 144 is located between the precharge voltage source having the precharge voltage Vpre and the output terminal (A Node) of the output buffer unit 148.

The precharging voltage Vpre may be set to the common voltage value (or intermediate gray level value) of the data voltage to be output through all output channels of the data driver 140. Since the precharging voltage (Vpre) is set to the common voltage value (or intermediate gray level value) of the data voltage to be output through all output channels, it can be implemented to be output from the decoder unit 147 under the control of the drive control unit 141. It is not limited to this.

The precharging voltage Vpre is applied between the output terminal (A Node) of the output buffer unit 148 and the input terminal of the output switch unit 149 only when the precharge switch 144 is activated (turned on). As a first example, if the display panel is not high resolution, there is no reason to precharge the output buffer unit 148 to improve slew rate characteristics. Accordingly, when the display panel is not high resolution, the driving control unit 141 may output a logic low precharge activation signal VPRE_EN to turn off the precharge switch 144. As a second example, when the display panel has a high resolution, it is necessary to precharge the output buffer unit 148 to improve slew rate characteristics. Accordingly, when the display panel is high resolution, the driving control unit 141 may output a logic high precharge activation signal VPRE_EN to turn on the precharge switch 144.

In this way, a separate pre-charging voltage (Vpre) is applied to the output terminal (A Node) of the output buffer unit 148 and the input terminal of the output switch unit 149 in the turn-on section of the output switch unit 149 where no data voltage is output. If applied in between, faster charging occurs. Therefore, the third embodiment can charge faster than the first embodiment, and thus the slew-rate characteristics can be further improved. Additionally, the slew rate characteristics of all output channels of the data driver 140 can be averaged, thereby reducing the possibility of slew rate deviation between output channels.

A display device according to an embodiment of the present invention includes a display panel that displays an image, and a data driver that supplies a data voltage through a data line connected to the display panel, and the data driver precharges an internal node based on the data voltage. After that, the data voltage is output through the data line connected to the display panel.

According to some embodiments of the present invention, the data driver may include an output buffer unit that precharges an internal node based on the current data voltage, and an output switch unit located between the output buffer unit and the data line.

According to some embodiments of the present invention, the output switch unit may be turned on after the node of the output buffer unit is precharged and buffered with a data voltage.

According to some embodiments of the present invention, the output buffer unit may be precharged based on the current data voltage from the time the previous data voltage is output and the output switch unit is turned off.

According to some embodiments of the present invention, the output switch unit may be turned on or off in response to the logic state of the output activation signal output from the drive control unit included within the data driver.

According to some embodiments of the present invention, the data driver may apply a precharging voltage to a node between the output buffer unit and the output switch unit.

According to some embodiments of the present invention, the precharging voltage may be set to a common voltage value or an intermediate gray level value of the data voltage to be output through all output channels of the data driver.

According to some embodiments of the present invention, the data driver includes a precharging voltage source that applies a precharging voltage to the node between the output buffer unit and the output switch unit, and a precharge switch located between the precharging voltage source and the output terminal of the output buffer unit. It may further include.

In addition, a display device according to an embodiment of the present invention has a display panel that displays an image, an output buffer unit that buffers the data voltage to be supplied to the display panel, and an output switch unit that controls the output of the data voltage transmitted from the output buffer unit. It includes a data driver, and the data voltage is precharged at the internal node by the output buffer and then output through the turned-on output switch.

According to some embodiments of the present invention, the output buffer unit may be precharged based on the current data voltage from the time the previous data voltage is output and the output switch unit is turned off.

In addition, the data driver according to an embodiment of the present invention includes a data latch unit that latches the data signal, a decoder unit that converts the data signal output from the data latch unit into a data voltage and outputs it, and a data voltage output from the decoder unit. It includes an output buffer unit that precharges and buffers the internal node, and an output switch unit that controls the output of the data voltage output from the output buffer unit.

According to some embodiments of the present invention, the output switch unit may be turned on after the node of the output buffer unit is precharged and buffered with a data voltage.

According to some embodiments of the present invention, the output buffer unit may be precharged based on the current data voltage from the time the previous data voltage is output and the output switch unit is turned off.

According to some embodiments of the present invention, the data voltage may be precharged at the internal node by the output buffer unit and then output through the turned-on output switch unit.

According to some embodiments of the present invention, it may further include a driving control unit that outputs an output activation signal to control turn-on or turn-off of the output switch unit.

The present invention has the effect of providing a display device suitable for high resolution by improving the slew rate characteristics when outputting a data voltage. Additionally, the present invention has the effect of improving display quality by improving slew rate characteristics. Additionally, the present invention has the effect of lowering the possibility of slew rate deviation between output channels.

Although embodiments of the present invention have been described with reference to the accompanying drawings, the technical configuration of the present invention described above can be modified by those skilled in the art in the technical field to which the present invention belongs in other specific forms without changing the technical idea or essential features of the present invention. You will understand that it can be done. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the claims described later rather than the detailed description above. In addition, the meaning and scope of the patent claims and all changes or modified forms derived from the equivalent concept should be construed as being included in the scope of the present invention.

110: video supply unit 120: timing control unit
130: scan driver 131: shift register
135: level shifter unit
140: data driver 150: display panel
141: driving control unit 142: shift register unit
143: first data latch unit 145: second data latch unit
147: decoder unit 148: output buffer unit
149: Output switch unit
170: backlight unit 180: power supply unit

Claims (15)

A display panel that displays images; and
A data driver that supplies a data voltage through a data line connected to the display panel,
The data driver unit connects the output terminal of the decoder unit to the input terminal of the switch unit,
When the output switch unit is turned off, the internal node is precharged with the output terminal voltage of the decoder unit,
When the output switch unit is turned on, the voltage precharged to the internal node has the same level as the output terminal voltage of the output buffer unit,
A display device that outputs the output terminal voltage of the output buffer unit to the data line. According to paragraph 1,
The data driver
The output buffer unit precharges the internal node based on the current data voltage,
A display device including the output switch unit located between the output buffer unit and the data line. According to paragraph 2,
The output switch unit
A display device that is turned on after the node of the output buffer unit is precharged and buffered with the data voltage. According to paragraph 2,
The output buffer unit
A display device that is precharged based on the current data voltage from the time the previous data voltage is output and the output switch unit is turned off. According to paragraph 2,
The output switch unit
A display device that is turned on or turned off in response to the logic state of an output activation signal output from a drive control unit included in the data driver. According to paragraph 2,
The data driver
A display device that applies a precharging voltage to a node between the output buffer unit and the output switch unit. According to clause 6,
The precharging voltage is
A display device set to the common voltage value or intermediate gray level value of the data voltage to be output through all output channels of the data driver. According to clause 6,
The data driver
A precharging voltage source that applies a precharging voltage to a node between the output buffer unit and the output switch unit,
A display device further comprising a pre-charging switch located between the pre-charging voltage source and the output terminal of the output buffer unit. A display panel that displays images; and
a data driver having an output buffer unit that buffers the data voltage to be supplied to the display panel, and an output switch unit that controls the output of the data voltage delivered from the output buffer unit;
The data driver unit connects the output terminal of the decoder unit to the input terminal of the output switch unit,
When the output switch unit is turned off, the internal node is precharged with the output terminal voltage of the decoder unit,
When the output switch unit is turned on, the voltage precharged to the internal node has the same level as the output terminal voltage of the output buffer unit,
A display device that outputs the output terminal voltage of the output buffer unit to a data line through the turned-on output switch unit. According to clause 9,
The output buffer unit
A display device that is precharged based on the current data voltage from the time the previous data voltage is output and the output switch unit is turned off. a data latch unit that latches a data signal;
a decoder unit that converts the data signal output from the data latch unit into a data voltage and outputs it;
an output buffer unit that precharges and buffers an internal node based on the data voltage output from the decoder unit; and
An output switch unit that controls the output of the data voltage output from the output buffer unit,
The output terminal of the decoder unit is connected to the input terminal of the output switch unit,
When the output switch unit is turned off, the internal node is precharged with the output terminal voltage of the decoder unit,
When the output switch unit is turned on, the voltage precharged to the internal node has the same level as the output terminal voltage of the output buffer unit,
A data driver that outputs the output terminal voltage of the output buffer unit to a data line through the turned-on output switch unit. According to clause 11,
The output switch unit
A data driver that turns on after the node of the output buffer unit is precharged and buffered with the data voltage. According to clause 11,
The output buffer unit
A data driver that precharges based on the current data voltage from the time the previous data voltage is output and the output switch unit is turned off. According to clause 11,
The data voltage is
A data driver that is precharged at an internal node by the output buffer unit and then output through the turned-on output switch unit. According to clause 11,
A data driver further comprising a drive control unit that outputs an output activation signal for controlling turn-on or turn-off of the output switch unit.

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