KR100436613B1 - High-speed data sampling system - Google Patents

Abstract

The present invention provides a system for sampling an analog or digital data signal at a relatively high rate using a relatively slow circuit. System 40 includes several sample and hold circuits 42-50 that each receive a data signal. The sample and hold circuit (42 to 50) are the same, but the frequency is clocked by the respective clock signals with each other and spaced in the same phase _{(φ 1, ... φ n)} . Thus, the sample and hold circuits take samples of the data signal at equal intervals of time. Each of the sample and hold circuits is connected to a series of shift registers 62-70 that are clocked at the same frequency as the clock used to clock the sample and hold circuit to which they are connected. Shift register are operable to store the samples _{(S 1, ..., S n} ) obtained by the respective sample and hold circuit sequentially. The outputs of the shift registers 82-90 may be applied to the column drivers of a conventional matrix display.

Description

High-speed data sampling system

Often, it is necessary to sample analog or digital data in various fields. In general, an analog or digital signal containing data is sampled at a periodic rate to obtain samples corresponding to the amplitude of the signal at points in time that are spaced apart at regular intervals. These samples are then subjected to processing such as storing the samples for future use. In some cases, the samples are processed sequentially after being stored, while in other situations the samples are stored and processed simultaneously.

One example of a conventional sampling system in which signals including analog or digital data are sampled and then processed at the same time are drive circuits for matrix displays, such as field emission displays. Typically, the matrix displays are arranged in an array of rows and columns perpendicular to each other on a display screen. Generally, each row is selected consecutively, and each column of the selected row is modulated to control the intensity of the corresponding pixel located at the intersection of the selected row and the corresponding column. Thus, for example, 500 samples of the same interval of a video signal may be obtained and used to modulate each of the 500 columns of the Nx500 matrix display. The first sample of the video signal is used to control the intensity of the leftmost pixel in the selected row and the last sample of the video signal is used to control the intensity of the rightmost pixel in the selected row.

One type of sampling system 10 that can be used to obtain samples of a video signal is shown in Fig. The system 10 of FIG. 1 includes a sample and hold circuit 12 having an input line 13, an output line 14, and a clock input line 16. An analog or digital data signal is applied to the input line 13. The sample and hold circuit 12 outputs on the output line 14 a sample of the data signal for each leading edge of the clock signal φ applied to the clock input line 16. The samples on the output line 14 are applied to a series of shift registers 20-28. Each of the shift registers 20-28 has a clock input line 30 that is simultaneously driven by the same clock signal φ that drives the sample and hold circuit 12 through the input line 16. Each of the shift registers has an input line 32 and an output line 34. The sampling circuit 10 outputs each of the samples S ₁ , S ₂ , S ₃ , S _N-1 , S _N of the data signal applied to the input line 13 of the sample and hold circuit 12, (34), as will be described later.

The operation of the sampling circuit shown in Fig. 1 will be described with reference to Fig. The upper part of Fig. 2 shows the analog data signal, and the lower part of Fig. 2 shows the clock signal [ phi ]. As shown in Fig. 2, the clock signal has a frequency of 100 MHz corresponding to a clock period of 10 nsec. As described above, the sample and hold circuit 12 takes a sample of the data signal at each leading edge of the clock signal [ phi ]. Therefore, the sample-and-hold circuit 12 samples the data input signal at time _{(t 1, t 2, t} 3, ..., t N-1, t N). The sample S ₁ taken at time t ₁ is first shifted to the first shift register 20. At time t ₂ , the first sample S ₁ is shifted to the second shift register 22 and the second sample S ₂ is shifted to the first shift register 20. The sampling circuit 10 continues to operate in this manner until the first sample S ₁ taken at time t ₁ is shifted to the final shift register 28. At this time, the sample S ₁ is outputted from the shift register 28, the second sample S ₂ is outputted from the N-1 shift register 26, the third sample S ₃ is outputted from the N- The second sample in the last sample is output from the second shift register 22 and the final sample S _N is output from the first shift register 20. The samples S ₁ to S _N can then be used to drive the columns of the matrix display so that the left pixel of the selected row of the display has an intensity corresponding to the amplitude of the data signal at time t ₁ will be. Likewise, the right pixel of the selected row of the display will have intensity corresponding to the amplitude of the data signal at time t _N. The intensity of the pixels between the end pixels of the selected row will have intensities corresponding to the amplitude of the data signal at the points corresponding to their location in the selected row. Of course, the sampling circuit 10 may be used to achieve various purposes besides driving the matrix displays.

The conventional method shown in Figs. 1 and 2 has generally been satisfactorily operated to date. However, data signals, such as the data signals shown at the top of FIG. 2, are displayed more frequently on matrix displays with high resolution. These high resolution displays have high resolution because there are many columns in the matrix array. As described above, a sample of the data signal must be obtained for each column of the matrix display. Thus, high resolution matrix displays require that data be sampled at a corresponding high rate. For example, a " refresh rate ", i.e., the rate at which all pixels of a display are modulated, is typically 60 Hz. A conventional VGA display has 480 lines and 640 columns. Thus, since 480 rows must be processed 60 times per second, the time required to process each row is 34.7 microseconds (i.e., the inverse of 60 * 480). 640 data signal samples should be taken for this 34.7 mu sec, which results in a sampling rate of about 54 nsec. The method shown in Figures 1 and 2 was generally able to provide samples at this sampling rate. However, high resolution XGA displays have 768 rows and 1024 columns. For a refresh rate of 60 Hz, each row should be processed within a time of 21.7 microseconds. For the 21.7 microseconds, 1024 samples should be taken, which results in a sampling rate of 21.2 nsec. The method shown in Figures 1 and 2 for sampling at such a high sampling rate can not currently be economically applied. Also, the resolution of the matrix displays will continue to increase, requiring higher sampling rates in the future. Thus, conventional methods of sampling data signals to drive matrix displays are inadequate in recent high resolution matrix displays.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for sampling analog or digital data, and more particularly to a system for sampling analog or digital data at high speed, storing samples and then simultaneously outputting a sample for use in a matrix display or other device will be.

1 is a block diagram illustrating a conventional system for obtaining and storing samples of a data signal;

Figure 2 is a waveform and timing diagram used to illustrate the operation of the system of Figure 1;

3 is a block diagram used for explaining the operation principle of the sampling system of the present invention;

4 is a waveform timing diagram used to illustrate the operation of the system of FIG. 3;

5 is a general block diagram of one embodiment of a sampling system of the present invention.

6 is a waveform timing diagram illustrating operation of the system of FIG. 5 with a 4 * M matrix display;

Figure 7 is a logic diagram of one embodiment of the inventive system shown in Figure 5;

8 is a schematic logic diagram of the sample and hold circuit and the shift register shown in the logic diagram of Fig.

Figure 9 is a detailed logic diagram of the shift register shown in the logic diagram of Figure 8;

FIG. 10 is a timing diagram illustrating the operation of some of the components used in the embodiments of FIGS. 7-9. FIG.

11 is a timing diagram illustrating the operation of almost all of the components used in the components.

Summary of the Invention

The system and method of the present invention samples analog or digital data signals at relatively high frequencies using components operating at relatively low frequencies. The system includes a clock circuit that generates a plurality of clock signals at respective outputs having different phases. Although these phase differences need not be uniform, it is desirable that the clock signals have phases at uniform intervals from one another. If there are uniformly spaced phases, the clock signals have phases of 360 / X degrees, where X = 1, 2, ..., N and N is the number of clock signals generated by the clock circuit. The sampling system also includes a plurality of sample circuits each having a data input for receiving a data signal and a clock input for receiving a respective one of the clock signals. Each sample circuit samples a data signal in response to a respective clock signal and applies a sample to the output. The sampling system also includes a set of a plurality of shift registers each having a data input, a data output and a clock input. The shift registers in each set are connected in series and each set of first shift registers has an input connected to the output of each sample circuit. The clock inputs of all the shift registers in each set are coupled to each other and to one of the clock signals, allowing the shift registers to operate in unison. When the data signal is an analog signal, the sample circuit and the shift registers are analog devices. When the data signal is a digital signal, digital sampling circuits and shift registers can be used. If the frequency of the clock signal f _O, the data signal is sampled at a relatively high frequency of Nf _O. Thus, at a given sampling frequency, the operating frequency of system components may be reduced as desired by increasing the number of N, i. E., The number of sample and hold circuits. Although the sampling system and method of the present invention may be used to achieve various purposes, it may be advantageously used to generate thermally modulated signals for conventional matrix displays having a plurality of row inputs and a plurality of column inputs.

details

The operating principle of the sampling system of the present invention is best described with reference to Figs. 3 and 4. Fig. 3, the sampling system 40 includes several sample and hold circuits 42 to 50 labeled S / H ₁ , S / H ₂ , ..., S / H _N . Each of the sample and hold circuits 42 to 50 is identical to each other, and they are circuits of the kind used as the sample and hold circuit of Fig. All sample and hold circuits 42-50 receive the data signals shown at the top of FIG. 3 on their respective data input lines 52. The sample and hold circuits 42 to 52 receive clock signals ( φ ₁ , φ ₂ ,..., Φ _N ) on their respective clock input lines 54 that are spaced in phase with each other. Therefore, the phase of the clock signal ? ₂ differs from the phase of the clock signal ? _{1 by} 360 ° / N. Each clock signal is shown in FIG. Samples and output from the hold circuit (42 to 50) are in each register for receiving from the output lines (56) each of the clock input line of the clock signal (φ ₁ to φ _N) corresponding through 72 0.0 > 62-70. ≪ / RTI > Each of the registers 62 to 70 outputs the samples S ₁ to S _N to the respective output lines 82 to 90.

As shown in FIG. 4, each of the sample and hold circuits 42 to 50 samples the data signal at the leading edge of each of the clock signals ? ₁ to ? _N. In addition, the clock signal latches the sample to the output of each register 62-70. Thus, causes the rising edge of a sample-and-hold circuit 42 samples, and to take a (S ₁₎ register 62 for causing the data signal of the first clock (φ ₁₎ at time (t _1), the output line ( 82 to output the sample. Similarly, the rising edge of the second clock phi ₂ at time t ₂ causes the sample and hold circuit 44 to take the second sample S ₂ of the data signal. The second clock signal ? ₂ also triggers the register 64 to provide the sample S ₂ to the output line 84. Operation continues as described above until the clock signal φ _N causes the sample and hold circuit (S / H _N ) 50 to take a sample at time t _N. The clock φ _N also triggers the register 70 to output the sample S _N on the output line 90. At this time, all the samples (S ₁ , S ₂ , ..., S _N ) are provided to the respective output lines 82 to 90.

3 is that all the registers 62 to 70 are sampled at intervals of 10 nsec, even though they operate at substantially lower frequencies than the 10 nsec sampling rate (i.e., 100 MHz). For a sampling system having N sample and hold circuits, the data can be sampled continuously at a frequency of f _O / N, where f _O is the sampling frequency (100 MHz in this example). Thus, for example, a sampling system with five sample and hold circuits can sample a data signal at a rate of 100 MHz, even though the components of the system operate only at a frequency of 20 MHz.

The importance of being able to sample at relatively high frequencies using a circuit that operates at a relatively low frequency is less than that in the generalized block diagram of one embodiment of the sampling system 108 of the present invention used to drive the columns of the matrix display Clearly. Referring to FIG. 5, the sampling system includes the same N sample and hold circuits as the sample and hold circuits 42 through 50 of FIG. Each of the sample and hold circuits 42 to 50 is triggered by each clock signal ? ₁ ,? ₂ , ..., ? _N. The clock signals ? ₁ to ? _N are generated by a conventional phase splitter 100 from the master clock signal generated by the conventional clock circuit 102. As is known in the art, phase splitter 100 may be implemented using various circuits including conventional counters and decoders. When the sampling system 108 is fabricated as a single integrated circuit, preferably the clock circuit 102 and / or phase splitter is not necessarily located outside the integrated circuit. The clock signals φ ₁ , φ ₂ , ..., φ _N preferably have the same frequency as the ratio of the frequency of the master clock signal to the number of clock signals N from the clock circuit 102. It is preferable that the phases of the clock signals ? ₁ ,? ₂ , ..., ? _N are equally spaced from each other.

A sample at the output of each sample and hold circuit 42-50 is applied to M serially connected shift registers 112-120. Each serial shift register 112, 114, 116, or 120 is clocked by the same clock signal, i.e., each clock signal from the phase splitter 100. Thus, for example, the shift registers 112a through 112m are all clocked by the ? ₁ clock signal. Likewise, the last set of shift registers 120a through 120m are all clocked by the φ _N clock.

As will be described in greater detail below, the outputs of all shift registers 112a through 120m are applied to respective inputs of a conventional column driver circuit 130. [ The column driver circuit 130 generates appropriate column driver signals applied to respective column inputs of the matrix display 132, such as a field emission display. As is known in the art, matrix display 132 also receives row input signals from conventional row driver circuitry 134. [

The operation of the sampling system 108 shown in Fig. 5 will be described with reference to Fig. The data signal is shown in FIG. 6 as an analog data signal, although it may be understood that the signal may be a digital data signal having any one of the two input levels. The operation of the sampling system shown in FIG. 5 is described with reference to FIG. 6, where "N" in the generalized block diagram of FIG. 5 is 4 (ie, there are four sample and hold circuits 42 to 50). At time t ₁ , the first clock signal ? ₁ triggers the sample and hold circuit 42 to take the first sample S ₁ . In addition, the first clock signal (φ ₁₎ shifts the sample to the output of the first shift register (112a). Hours at (t _2), the second clock signal (φ ₂₎ is the second sample and to cause the hold circuit 44 to sample the data signal, samples the first register (114a) of the second set of the (S ₂₎ As shown in FIG. The operation allows the last clock signal φ _N to sample the data signal at time t ₄ and the sample S ₄ to the fourth (N = 4) sample and hold circuit 50, And proceeds in this manner until it is shifted to the output of the shift register 120a. At time t _{5 the} clock φ ₁ causes the second sample and hold circuit 112b to switch from the output of the first shift register 112a to the output of the second shift register 112b to the first sample S ₁ ). Also, at time (t _5), the clock signal (φ ₁₎ is the sample and cause the hold circuits 42 and to once again sample the data signal in order to obtain a sample (S _5), the sample (S ₅₎ shift And shifts to the output of the register 112a. (In practice, data is shifted in and out of the shift registers 112 to 120 at different times, but for clarity, the shift registers 112 to 120 here simultaneously shift the new data to the shift register and the previous data Can be shifted out of the shift register). Hold circuit 44 at time t ₅ and the second sample-and-hold circuit 44 at time t ₆ until the fourth sample-and-hold circuit 50 samples the data signal again at time t ₇ . Additional samples are taken by the sample and hold circuit 48. The first sample and hold circuit 42 then takes a third sample S ₉ at time t ₈ . Simultaneously, the φ ₁ clock signal shifts the first sample S ₁ from the shift register 112b to the downstream shift register and shifts the sample S ₅ to the second shift register 112b, And the sample S ₉ is shifted to the shift register 112a. Operation proceeds in the same manner until the first sample S ₁ is shifted to the M shift register 112m and the fourth sample S ₄ is shifted to the shift register 120m. At this time, the fourth sample (S _{4 (M-1) +1} ) in the final sample is shifted to the shift register 112a and the third sample S ₄ Is shifted to the shift register 114a, and the final sample S _4M is shifted to the shift register 120a. At this time, all of these samples S ₁ through S _4M are processed by the column driver circuit 130, which applies appropriate signals to the column signals of the matrix display 132. At this time, the display 132 illuminates the pixels with intensity corresponding to the amplitude of each sample at a position corresponding to the overlap of the row and column selected by the row driver circuit 134. It should be noted that the first sample S ₁ is applied to the leftmost column input of the column driver circuit 130 and the final signal S _NM is applied to the rightmost column input of the column driver circuit 130 do. The samples are applied in this order to the column driver circuit 130 in such a manner that the matrix displays receiving the video signals customarily display the initial portion of the video signal to the left of the display screen and the video signal As shown in FIG. However, it can be appreciated that the order of displaying the samples can be reversed on demand.

It will be clear from FIG. 6 that the clock signals ? ₁ through ? ₄ have a frequency that is one quarter of the frequency at which the data signal is sampled, as described above. Thus, although the data signal is sampled at a relatively high rate, i.e., 100 MHz, the shift registers 112-120 can operate at relatively low frequencies, i.e., 25 MHz. By increasing the number of clock signals and the sets of sample and hold circuits and shift registers, the operating frequency of the shift registers 112-120 can be reduced without further decreasing the sampling frequency. For example, by using eight clock signals and eight sets of sample and hold circuits 42-50 and shift registers 112-120, the data signal is at 100 MHz, even though the shift registers operate at 12.5 MHz. Can be sampled.

One specific embodiment of the generalized sampling system 108 shown in FIG. 5 is shown in FIG. Although the sampling system shown in FIG. 7 may be implemented to sample either an analog signal or a digital signal, the embodiment shown in FIG. 7 is used to sample the digital signals. Similar to the system 108 shown in FIG. 5, the system 140 shown in FIG. 7 utilizes a phase splitter 100 to generate a series of clock signals from the master clock 102. These clock signals are phase 0 °, 45 °, 90 °, and 135 °, and the 45 ° incremented angles between 135 ° and 360 ° are reversed clock signals from the phase splitter 100 . The clock signals are applied to the respective sampling circuits and shift registers indicated by reference numeral 150 through a set of inverters, In particular, the 0 ° clock signal from phase splitter 100 is applied to sampling and shift register circuit 150h via a pair of inverters 180,182 such that the clock input of circuit 150h is at phase 0 . A 0 ° clock signal from phase splitter 100 is also applied to sample and shift register 150f via inverter 184 to cause circuit 150f to receive a clock signal that is phase aligned by 180 °. In a similar manner, a 45 [deg.] Clock signal from phase splitter 100 is applied to sampling and shift register circuit 150d via a pair of inverters 186 and 188, The clock input allows a 45 ° clock signal to be received. The 45 ° clock signal is also applied to the sampling and shift register circuit 150b via one inverter 190 so that the clock input of the sampling and shift register circuit 150b receives a clock signal that is phase- do. In a similar manner, a 90 [deg.] Clock signal from phase splitter 100 is applied to sampling and shift register circuit 150e via a pair of inverters 192 and 194, sampled and fed via one inverter 196 And is applied to the shift register circuit 150g. Thus, the sampling and shift register circuit 150e receives a clock signal that is 90 ° out of phase, and the sampling and shift register circuit 150g receives a signal that is 270 ° out of phase. Finally, a 135 [deg.] Clock signal from phase splitter 100 is applied to sampling and shift register circuit 150a via a pair of inverters 200 and 202 and sampled and shifted through one inverter 204 And is applied to the register circuit 150c. Thus, the sampling and shift register circuit 150a receives a clock signal that is phase shifted by 135, and the sampling and shift register circuit 150c receives a clock signal that is phase shifted by 315 degrees. In summary, the clock inputs of the sampling and shift register circuits 150a-150h receive eight separate clock signals that are 45 ° apart from each other. The outputs of the sampling and shift register circuits 150 drive each set of serially connected shift registers,

The sampling and shift register circuits 150a through 150h are shown in more detail in FIG. The sampling and shift register circuits 150 include a sampling circuit 210 and a shift register circuit 208. The sampling circuit includes a PMOS transistor 216 and an NMOS transistor 218 connected in parallel with each other so that the sources of the transistors 216 and 218 are all connected to the data signal input and the drain of the transistors 216 and 218 All connected to the common output. The gate of the PMOS transistor 216 is connected to the first enable input "enp" and the gate of the NMOS transistor 218 is connected to the second enable input "enn". The PMOS transistor 216 is switched to a conducting state by a logic " 0 " signal and the NMOS transistor is switched to a conducting state by a logic " 1 " When the transistors 216 and 218 are switched to the non-conducting state, the amplitude of the data signal at this time is stored in the capacitor 220. At this time, the sample on the capacitor 220 is applied to the data input of the shift register 208.

The shift registers 208 are shown in more detail in FIG. The data signal is applied directly to the first NAND gate 230 and to the second NAND gate 234 via the inverter 232. [ The clock signal is applied to the inputs of the two NAND gates 230, 234 via inverter 236. Thus, NAND gates 230 and 234 are enabled at the trailing edge of the clock input (i.e., transition from high to low). Logic " 0 " applied to the input of NAND gate 234 sets the flip-flop formed by NAND gates 240 and 242 so that if NAND gate 242 is logic "Quot; 1 " At the same time, NAND gate 240 outputs a logic " 0 " which holds the output of NAND gate 242 at logic " 1 ". The flip-flop formed by NAND gates 240 and 242 is reset so that NAND gate 240 outputs a logic " high " and NAND gate 242 is reset to logic < RTI ID = And outputs " 0 ". Thus, the data samples are clocked to the shift register 208 at the falling edge of the clock signal.

In addition, the clock signal is applied directly to a pair of NAND gates 260 and 262 having outputs coupled to a pair of NAND gates 270 and 272. NAND gates 260 and 262 function in the same manner as NAND gates 230 and 234 and NAND gates 270 and 272 function as flip-flops in the same manner as NAND gates 240 and 242 . Thus, NAND gates 260 and 262 are enabled at the rising edge (i.e., " low to high transition " of the clock signal) such that the inversion of the output from NAND gates 240 and 242 causes NAND gates 270, and 272, respectively. A logic " 0 " at the output of NAND gate 242 causes the output of NAND gate 262 to go high on the rising edge of the clock signal if the data signal was a logic " 1 " at the previous falling edge of the clock signal. Conversely, a logic " 1 " at the output of NAND gate 240 causes the NAND gate 260 to output a logic " 0 ", thereby resetting the flip-flop formed by NAND gates 270 and 272. NAND gate 270 outputs a logic " 1 " that is a logic " 1 " after being inverted twice by a pair of inverters 278,280. If the data signal was a logic " 0 " at the falling edge of the clock signal, a logic " 0 " is shifted through the inverter 280 at the next rising edge of the clock signal. In summary, the data is shifted to the shift register at the falling edge of the clock signal and the same data is shifted out of the register at the subsequent rising edge of the clock signal.

The operation of the sampling circuits 140 shown in Figs. 7 to 9 will be described with reference to Fig. 10 for the register 150h which receives the 0 [deg.] Clock signal. The enn enable input to circuit 150h receives a 90 ° clock signal and the enp enable input receives an inverted signal, that is, a 270 ° clock signal. Thus, at time t ₁ , a sample of the data signal is taken and stored in capacitor 220. Thereafter, at the trailing edge of 0 ° clock at time t ₂ , the sample stored in capacitor 220 is latched into shift register 208 of circuit 158h. At the next leading edge of the 0 ° clock at time t ₃ , the data is latched to the output of shift register 208 of circuit 150h. At time t4, another sample of the data signal is taken. At time t ₅ the second sample taken at time t ₄ is latched into shift register 208 of circuit 150h and the first sample taken at time t ₁ is latched into second shift register 208, . The operation of each set of shift registers 208 proceeds as described above until the data is serially shifted into the final shift register.

The operation of all the circuits shown in Fig. 7 is shown in the timing diagram of Fig. 11 shows the data output from the first shift register 208 of the circuits 150, as well as the digital data signal applied to the sampling and register circuits 150. The timing diagram of FIG. The signals output from the shift registers 208 are delayed from the rising edge of the clock signal due to the delay of the propagation signal through the shift registers 208. [

Thus, the sampling system of the present invention represents sampling circuits operating at relatively low frequencies, as well as being able to sample analog or digital data at a significantly higher rate using a relatively slow rate. Although specific embodiments of the invention have been described herein for purposes of illustration, it will be appreciated that various modifications may be made without departing from the spirit and scope of the invention. For example, although data signals are described as sampled by sample and hold circuits, other devices, such as multiple memory devices, enabled by respective clocks that are different in phase with each other may be used . In this case, instead of using shift registers to store multiple samples, each of the counters clocked by the different phase clock signals can be used to address the memory to store each of the samples in consecutive addresses. Accordingly, the invention is limited only by the appended claims.

Therefore, the sampling system of the present invention not only samples analog or digital data at a relatively high speed, but also samples a sampling circuit operating at a relatively low frequency. Although specific embodiments of the invention have been described for illustrative purposes, various modifications may be made without departing from the spirit and scope of the invention. For example, although data signals are shown sampled by sample and hold circuits, other devices such as multiple memory devices enabled by different clocks in phase with each other may be used It should be understood. In this case, instead of using a shift register to store multiple samples, each counter clocked by a different phase clock signal can be used to address a memory for storing each sample in a subsequent address. Accordingly, the invention is limited only by the appended claims.

Claims (20)

A system for sampling a data signal at a relatively high speed, comprising: A clock circuit for generating a master clock signal at an output; A clock divider having an input connected to an output of the clock circuit for receiving the master clock signal from the clock circuit, the clock divider comprising a plurality of clock signals having a frequency substantially lower than the frequency of the master clock signal, Wherein the clock signals are generated from the master clock signal at outputs of the clock divider, the clock signals having respective phases different from each other; A plurality of sample circuits each having a data input for receiving the data signal and a clock input for receiving one of the clock signals, each of the sample circuits sampling the data signal in response to its respective clock signal, A plurality of sample circuits for applying a sample to an output; And Each set of the shift registers being connected in series with one another, each set of first shift registers having a first input terminal, a second input terminal, and a second input terminal, each of the set of M shift registers having a data input, a data output, and a clock input, The set of M shift registers having an input connected to the output of the sample circuit, wherein the clock inputs of all the shift registers in each set are coupled to each other and to one of the clock signals. The method according to claim 1, The clock divider is f ₀ / a frequency of N and generate the N clock signals with each of the f ₀ is the frequency of the master clock signal and the clock signals are 360 / X also (X each is 1, 2, ..., N) so that the sampling system receives the N * M samples of the data signal at a frequency of f ₀ to obtain N * M samples every M / f ₀ seconds, / RTI > The method according to claim 1, Wherein the data signal is an analog signal, the sample circuit is an analog sample circuit, and the shift registers are analog shift registers. The method according to claim 1, Wherein the data signal is a digital signal that varies between two logic levels. The method according to claim 1, The sample circuit comprising: A PMOS transistor having a gate connected to a first trigger signal generated from one of the clock signals; An NMOS transistor having a source connected to the source of the PMOS transistor and a source connected to the data signal, a drain connected to the drain of the PMOS transistor, and a gate connected to a second trigger signal generated from the same clock signal from which the first trigger signal is generated, transistor; And And a capacitor coupled to a drain of the transistor and storing a sample of the data signal in response to the first and second trigger signals. A system for displaying an image corresponding to a data signal on a screen, comprising: A matrix display having a plurality of row inputs and a plurality of column inputs; A row processing and driving circuit connected to row inputs of the matrix display; A clock circuit for generating a plurality of clock signals at respective outputs having different phases from each other; A plurality of sample circuits each having a data input for receiving the data signal and a clock input for receiving one of the clock signals, each of the sample circuits sampling the data signal in response to its respective clock signal, A plurality of sample circuits for applying a sample to an output; Each set of the shift registers being connected in series with one another, each set of first shift registers having a first input terminal, a second input terminal, and a second input terminal, each of the set of M shift registers having a data input, a data output, and a clock input, Sets of the plurality of M shift registers having an input connected to the output of the sample circuit, the clock inputs of all the shift registers of each set being coupled to each other and to one of the clock signals; And A thermal processing and drive circuit having a plurality of column inputs for receiving respective column signals corresponding to the intensity at which the pixels of the column are to be displayed, Wherein the inputs to the thermal processing and drive circuit are connected to the outputs of the shift registers in the same order as the order in which the samples stored in the shift registers are obtained, Processing and drive circuitry. The method according to claim 6, The clock circuit generates N clock signals each having a frequency of f ₀ / N, and the clock signals are identical to each other to have phases of 360 / X degrees (X = 1, 2, ..., N) Wherein the display system samples the data signal at a frequency of f ₀ to obtain N * M samples of the data signal every M / f ₀ seconds. The method according to claim 6, Wherein the data signal is an analog signal, the sample circuit is an analog sample circuit, and the shift register is an analog shift register. The method according to claim 6, Wherein the data signal is a digital signal that varies between two logic levels. The method according to claim 6, The sample circuit comprising: A PMOS transistor having a gate connected to a first trigger signal generated from one of the clock signals; An NMOS transistor having a source connected to the source of the PMOS transistor and a source connected to the data signal, a drain connected to the drain of the PMOS transistor, and a gate connected to a second trigger signal generated from the same clock signal from which the first trigger signal is generated, transistor; And A capacitor connected to the drains of the transistors, the capacitor storing a sample of the data signal in response to the first and second trigger signals. The method according to claim 6, Wherein the matrix display is a field emission display. The method according to claim 6, Wherein the display comprises N * M columns. A system for sampling a data signal at a relatively high frequency using a clock having a relatively low frequency, the system comprising: An oscillator for generating a plurality of clock signals having a relatively low frequency, wherein the clock signals each have different phases from each other; And a sampling device for receiving the data signal to obtain each sample of the data signal in response to each of the clock signals at the relatively low frequency so that samples are obtained from all of the clock signals at the relatively high frequency, ; And A storage coupled to the sampling device, the storage device receiving and storing the data signal samples obtained in response to each clock signal of the corresponding sets, each set of samples being stored in the order in which the samples are obtained, And to cause a corresponding set of temporally ordered samples to be obtained. 14. The method of claim 13, Wherein the oscillator generates N clock signals having respective phases spaced apart from each other, the clock signals having phases of 360 / X degrees (X = 1, 2, ..., N) Thus, the sampling device has N * sampling the data signal at a frequency of f _O and f _O is the frequency of the sampling system of the relatively low frequency. 14. The method of claim 13, Wherein the storage device is N * M number of samples, the sampling system can be obtained per second M / f ₀ of the data signal to store the M samples in the respective set. 14. The method of claim 13, Wherein the storage device comprises a plurality of shift registers. 14. The method of claim 13, Wherein the sampling device is a sample and hold circuit. A method of sampling a data signal at a relatively high frequency using a clock having a relatively low frequency, the method comprising: Generating a plurality of clock signals having relatively low frequencies and having different phases from each other; Sampling the data signal in response to each of the clock signals to obtain each sample at the relatively low frequency from each of the clock signals such that samples are obtained from all of the clock signals at the relatively high frequency; And Storing the data signal samples obtained in response to each clock signal of the corresponding sets, wherein each sample of each set is stored in the order in which the samples were obtained so that a set of temporally ordered Wherein the stored samples are obtained. 19. The method of claim 18, N clock signals having respective phases spaced at equal intervals from each other, such that the clock signals have phases of 360 / X degrees (X = 1, 2, ..., N) Wherein the signal is sampled at a frequency of N * f ₀ , and wherein f ₀ is the frequency of the relatively low frequency. 19. The method of claim 18, The M samples are stored in the respective set, N * M samples of the data signals that can be obtained per second M / f _O, sampling method.