JPS63131614A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To confirm the potential of an internal bus to a low or a high level even when all tri-state gates driving the internal bus are brought into high impedance state at the same time by connecting an inverter latching a logic level of a potential of the internal bus to the internal bus. CONSTITUTION:A 1st inverter comprising a complementary MIS transistor (TR) whose input is connected to the internal bus 10 and a 2nd inverter 2 using the output of the 1st inverter as the input and whose output is connected to the internal bus 10 are provided. Thus, the logic level of the potential of the internal bus 10 is latched and even when all the tristate gates 3-6 driving the internal bus 10 go to a high impedance state at the same time, the floating state of the internal bus 10 is avoided. Thus, the logic level of the internal bus 10 is confirmed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device composed of complementary MIS transistors, and particularly to a semiconductor integrated circuit device in which the outputs of a plurality of 3-state gates are integrated within the semiconductor integrated circuit device. The present invention relates to a semiconductor integrated circuit device having an internal bus connected to a main communication line.

(Prior Art) Conventionally, the internal bus of this type of semiconductor integrated circuit device has been pulled up or down to the power supply potential or ground potential using a resistor element, or by using an MIS transistor, in order to avoid a floating state of the internal bus. By controlling the gate electrodes of the MIS transistors, when all three-state gates that drive the internal bus become high impedance at the same time, the power supply potential or ground potential is supplied to the internal bus, or 3- is in the output state under the condition that all logically active 3-state gates driving the internal bus are in high impedance.
The configuration included adding state gates, etc.

[Problem that the invention seeks to solve]

The conventional semiconductor integrated circuit device described above uses a resistance element to pull up the internal bus to the power supply potential or ground potential.
In the pull-down configuration, a steady current flows when the 3-state gate connected to the internal bus is in the output state, impairing the characteristics of the complementary MIS transistors, and in the other two configurations, the redundant A control signal is required, which not only complicates the logic design, but also requires that at least one output transistor connected to the internal bus be turned on, making it difficult to avoid bus collisions in terms of timing. It has the disadvantage of being.

[Means for solving problems]

The semiconductor integrated circuit device of the present invention is comprised of complementary MIS transistors, and has an input connected to an internal bus.
The second inverter is composed of an inverter and complementary MIS transistors, the output of the first inverter is used as an input, and the output is connected to an internal bus.

In this way, the first. By connecting a second inverter to the internal bus, the logic level of the potential on the internal bus can be latched, so that even if all three-state gates driving the internal bus are in a high-impedance state at the same time. , it is possible to avoid the internal bus from being in a floating state, and it is possible to determine the level of the potential of the internal bus.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of a semiconductor integrated circuit device of the present invention, FIG. 2 is a circuit diagram of a main part of the first embodiment, and FIG. 3 is an operation of the first embodiment. FIG.

An internal bus 10 of a semiconductor integrated circuit device to which four 3-state gates 3 to 6 are connected is connected to a first inverter 1, which is a feature of the present invention, in addition to a gate 7.8 that receives and receives bus signals. The output of the first inverter 1 is input to the second inverter 2, and the output of the second inverter 2 is output to the internal bus 10. 3-state-gate 3
-6 output circuits 3A to 6A (5A and 6A are not shown)
are each composed of complementary MIS transistors, and the sources of the P-type MIS transistor and the Nl'MIS transistor are connected to the positive and negative poles (ground) of the DC power supply, respectively.
The drains are connected to each other, and the connection point thereof is connected to the internal bus 10.

Now, the on-resistance of the P-type MIS transistor that makes up the second inverter is r, and the on-resistance of the N-type MIS transistor that makes up the second inverter is r, which makes up the output of the 3-state gate connected to the H1 bus. P-type MISt
- R is the on-resistance of the transistor, RP is the on-resistance of the N-type MISt that constitutes the output of the 3-state gate connected to the bus, and is the maximum voltage guaranteed for operation. D
HAX, when the threshold voltage of the P-type MIS transistor constituting the first inverter is V, and the threshold voltage of the PN-type MIS transistor is vllI, [R/(r +RN)]-V,, HAx <V□ ,
.

Nf'...(1) and [R/(r +R)] -V
＜IVTPIPNP
If the second inverter is configured to simultaneously satisfy the following two relationships: DDHAX (2), the level of the internal bus will change in accordance with the change in the logic level of the output of the 3-state gate.

In this embodiment, the complementary type M constituting the second inverter 2
The on-resistance of the IS transistor is Ω for the P-type MIS transistor and rN=25 for the N-type MIS transistor.
The on-resistance of the complementary MIS transistors constituting the outputs of the 3-state gates 3 to 6 is R, = 2.5Ω for the P-type MIS transistor, and RN for the N-type M S transistor. = 1 to Ω, maximum operation guaranteed power supply voltage V
=5.5V, PIM I S transistor 00H8χ threshold voltage VTP = -1,2V, N type M■
Threshold voltage of S transistor V = 1.
OV and [R/(r,+RN)]TlI
At N −V = 0.212V [R/(r, +−DDH
AX H R)] ・v <v, and [R1/N
DDHAX TH(r
+R)]-V = 1.1V and [R.

N P DDHAX/(rN
+R, )] "[1DHAX <IVTP' is satisfied. The first and second inverters 1.2 function as a kind of latch, and all outputs of 3-state gates 3 to 6 are high. When in impedance state, internal bus 10
can hold the potential at a low level or high level, thereby preventing the gates 7 to 8 from entering the input open state.

Now, at time t1, any one of the 3-state gates 3 to 6 enters the output state, and the first... Second inverter 1
．． When attempting to invert the potential of the internal bus 10 held by 2 from low level to high level, the potential of internal bus 10 first changes from O- level to VDor at time t2.
N/(RP+rN), and as a result, the gates that receive the internal bus 10 signal, including the first inverter 1,
The N-type MIS transistor is turned on, while the P-type M*S transistor is inverted as the threshold voltage *TP is no longer obtained and it is turned off. At time t3,
When the first inverter 1 is inverted, the second inverter 2 is inverted, and the internal bus 10 becomes high level. Then time t
4, the 3-state gate 4 in the output state changes from the output state to the high impedance state (marked H2 in the figure), and the potential of the b1 internal bus 10 changes to the 1st. Since it is latched by the second inverters 1 and 2, the previous state continues to be maintained.

Next, at time t5, one of the three-state gates 3 to 6 changes from the high-impedance state to the output state, and the first... When attempting to invert the potential of the internal bus 10 held by the second inverter 1゜2 from high level to low level, the potential of the internal bus 10 first changes from high level to V R/(R+r ,)become,
As a result, the gates that receive the signal from the DNM channel internal bus 10, including the first inverter 1, turn on the P-type MISt-transistor, while the N-type MIS transistor becomes unable to obtain the threshold voltage TN. It is reversed by turning it off. At time t7, when the first inverter 1 is inverted, the second inverter 2 is inverted, and the internal bus 10 becomes low level. Next, even if the 3-state gate 4 in the output state changes from the output state to the high impedance state at time t8, the potential of the internal bus 10 remains unchanged from the first. Second inverter 1.2
Since it is wrapped by , it continues to retain its previous state.

FIG. 4 is a circuit diagram of a main part of a second embodiment of the semiconductor integrated circuit according to the present invention.

In this embodiment, the MIS transistors of output circuits 3B and 4B forming a 3-state gate are connected in parallel in order to differentiate the driving abilities of the MIS transistors in the circuit shown in FIG.

FIG. 5 is a configuration diagram of a third embodiment of a semiconductor integrated circuit 5At of the present invention.

In this embodiment, the internal bus has four pits.

Each signal 1i120.30.40.50. Inverters 21, 22.31, 32.41, and 42. are arranged at the tips of the respective signal lines 20.30.40.50.
51 and 52. Each signal line 20.30.40.50
3-state gates 23 and 24.3 connected to
3 and 34.43 and 44.53 and 54. The gates 25, 35, 45, and 55 connected to the respective signal lines constitute a 4-bit semiconductor integrated circuit device in which the semiconductor integrated circuit device of the first embodiment has 1 bit.

FIG. 6 is a block diagram of a fourth embodiment of the present invention.

In this embodiment, the initialization circuit 1 is connected to the internal bus 10 of the first embodiment.
1 is connected.

7 and 8, P-type and N-type MIS transistors 11A and IIB are used in the initialization circuit 11 of FIG. 6, respectively.
The source of B is connected to the positive or negative electrode (ground) of the power supply, and the drain is connected to the internal bus 10, respectively.

In the case of FIG. 7, the potential of the internal bus 10 is set to a high level by setting the gate of the initialization circuit 11A to a low level. In the case of FIG. 8, the potential of the internal bus 10 is set to a low level by setting the gate of the initialization circuit 11B to a high level.

FIG. 9 is a configuration diagram of a fifth embodiment of the present invention.

In this embodiment, the initialization circuit 12 is connected to the connection point between the first inverter and the second inverter in the first embodiment.

FIG. 10 shows an embodiment in which an initialization circuit is added by the method shown in FIG. 9, and the initialization circuit 12 includes a transfer gate T,
Once G becomes conductive, the internal bus 10 can be arbitrarily set to a low level or a high level depending on the input signal level of the initialization circuit 12.

〔Effect of the invention〕

As explained above, in the present invention, by connecting an inverter to the internal bus that latches the logic level of the potential of the internal bus, the internal The potential of the bus can be determined to a low level or a high level, which has the effect of overcoming the drawbacks of the prior art for avoiding the 70-ting state of the internal bus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of a semiconductor integrated circuit device of the present invention, FIG. 2 is a circuit diagram of a main part of the first embodiment, and FIG. 3 shows the operation of the first embodiment. Timing chart, 4th
FIG. 5 is a circuit diagram of a second embodiment of the semiconductor integrated circuit device of the present invention, FIG. 5 is a block diagram of a third embodiment of the semiconductor integrated circuit device of the present invention, and FIG. 6 is a semiconductor integrated circuit of the present invention. A configuration diagram of the fourth embodiment of the device, FIG. 7 is a circuit diagram of the main part when a P-type MIS transistor is used in the initialization circuit 11 of the fourth embodiment, and FIG. 8 is a diagram of the fourth embodiment. A circuit diagram of a main part when an N-type MIS transistor is used in the initialization circuit 11 of the example, FIG. 9 is a configuration diagram of a fifth embodiment of a semiconductor integrated circuit device of the present invention, and FIG. Initialization circuit 11 of the embodiment of
FIG. 2 is a configuration diagram when a transfer gate is provided. 1.2.21.22.31, 32.41, 42°51.
52...Inverter, 3-6, 23, 24.33, 34, 43.44°53.
54...3-state gate, 3A, 3B, 4A,
4B...3-state gate output circuit, 7.8.25.35.45.55...gate, 10.
20, 30, 40.50...internal bus, 11.12.
IIA, 11B...Initialization circuit. Patent applicant: NEC Corporation Figure 1 Figure 3 Figure 5 Figure 6 Figure 9 Figure 7 Figure 8 Figure 10

Claims (1)

[Claims] 1. A semiconductor integrated circuit device having an internal bus in which the outputs of a plurality of 3-state gates are connected to one signal line, and comprising complementary MIS transistors, comprising: A first inverter is made up of MIS transistors and has an input connected to the internal bus, and a second inverter is made up of complementary MIS transistors, takes the output of the first inverter as input, and has an output connected to the internal bus. A semiconductor integrated circuit device comprising an inverter. 2, 3 - The on-resistance of the P-type MIS transistor of the complementary MIS transistors constituting the output circuit of the state gate is R_P, and the on-resistance of the N-type MIS transistor is R_
N, and the maximum power supply voltage for guaranteed operation is V_D_O_M_A_
X, P-type MIS transistor constituting the first inverter;
When the threshold voltages of the N-type MIS transistors are respectively V_T_P and V_T_N, the on-resistance of the P-type MIS transistor of the complementary MIS transistors forming the second inverter is r_P, and the on-resistance of the N-type MIS transistor is r_N, The second inverter is [R_N/(r_P+R_N)]・V_D_D_M_A
_X<V_T_H...(1) and [R_P/(r_N+R_P)]・V_D_D_M_A
_X<|V_T_P|...(2) The semiconductor integrated circuit device according to claim 1 is constituted by a P-type MIS transistor and an N-type MIS transistor having on-resistances r_P and r_N that satisfy _X<|V_T_P|...(2) .