JP2858503B2 - MOS type semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS semiconductor integrated circuit, and more particularly to a MOS semiconductor integrated circuit that controls a normal, reverse, or stop mode of a motor or the like by using an output buffer H-bridge circuit.

[0002]

2. Description of the Related Art Conventionally, this type of MOS semiconductor integrated circuit has an output buffer H-bridge circuit 14a composed of four MOS transistors 5 to 8, as shown in FIG. That is, the mode control circuit 11 controls the internal input nodes Na,
The gate control signals VNa and VNb are supplied to Nb.

The output buffer H-bridge circuit 14a includes a first MOS transistor 5 having a source connected to the power supply terminal 3, a source connected to the first output terminal 9, a gate connected to the input node Na, and a drain connected to the output terminal 9. , A source connected to the ground terminal 4 and a gate connected to the input node Nb, a drain connected to the power supply terminal 3, a source connected to the second output terminal 10, and a gate connected to the input terminal Nb. A third MOS transistor 7 connected to the node Nb; and a fourth MOS transistor 8 having a drain connected to the output terminal 10, a source connected to the ground terminal 4, and a gate connected to the internal input terminal Na. doing. A load is connected between the output terminals 9 and 10 using an external motor M as a load. Mode control circuit 11
Is composed of a control logic circuit 15 and level shift circuits 16a and 16b shown in FIG. Since the output buffer H-bridge circuit 14a of the level shift circuit is composed of only N-channel type field effect transistors 5 to 8, the gate control signals VNa and VNb are higher than the motor power supply voltage VM applied to the power supply terminal 3. Since it is necessary to convert the logic voltage to the level, the power supply terminal 2b of the control circuit 11 is separated from the power supply terminal 2a for the control logic circuit 15.

The mode control circuit 11 has an input terminal 1
The signals S1a and S1b are input to the buffer H
Gate control signals VNa and VNb are supplied to the input nodes Na and Nb of the bridge circuit 14a, and the current IL and the current IL are supplied to the double diffusion type N-channel MOS transistors 5a to 8a as shown in FIGS. Control is performed in three modes: forward rotation, reverse rotation, and stop, in which IR and the through current I at the time of switching flow.

FIG. 6 is a voltage / current characteristic diagram at the time of mode switching for explaining the operation of the circuit of FIG. When the level of the gate control signal VNa of the internal input node Na is at "H" level, the transistors 5 and 8 are conducting, so that the potential V9 of the output terminal 9 is substantially VM, and the potential V10 of the output terminal 10 is substantially 0V. become.

Conversely, the gate control signal V of the internal input node Nb
Conversely, when the level of Nb is "H", the transistors 6 and 7 are turned on, so that the potential V9 of the output terminal 9 becomes almost 0 V and the potential V10 of the output terminal 10 becomes almost VM. Here, the two gate control signals VNa and VNb are controlled by the control circuit 11 so as not to be at the "H" level at the same time.

However, as described above, the N-channel type MO
When the output buffer H-bridge circuit 14a is composed of only the S transistors 5 to 8, the switching speed of the transistor 5 on the power supply side is slower than that of the transistor 6 on the ground side. At time TL, the conduction state is simultaneously established, a through current I flows from the power supply terminal 3 through the upper and lower transistors 5 and 6 to the ground terminal 4 as shown by a dotted line in FIG. 5C, and the motor power supply voltage VM is divided. A large amount of power is consumed by the two transistors 5 and 6, respectively, and the output buffer H-bridge circuit 14 is destroyed.

Next, the difference between the current switching speeds of the transistors 5 and 6 will be described using the waveforms of the internal gate control signals VNa and VNb. Here, the VG which becomes “H” level is the mode control circuit 11.
The power supply voltage is supplied from the power supply terminal 2b of the H-bridge circuit 14a, and is usually about 8 V higher than the motor power supply voltage VM of the H-bridge circuit 14a. FIG. 6 shows a waveform in which the gate control signal VNb switches from "L" to "H" level while the gate control signal VNa switches from "H" to "L" level.

The control signal VNb, which is the voltage VG6 applied to the gate electrode of the transistor 6 that is turned off, becomes conductive from time t1 when it becomes higher than the threshold voltage Vth of the transistor 6, but it is conductive. Transistor 5 does not enter a non-conductive state until time t2 when control signal VNa falls to threshold voltage Vth.

As shown in FIG. 6, a gate control signal VNa,
If the waveform of VNb is symmetrical up / down with respect to the intermediate voltage (VG / 2), there will be a difference in current switching speed,
A simultaneous conduction state of the transistors 5 and 6 during the period T occurs, and a through current I between the power supply and the ground is generated. Its peak current IP
At this time, half of the motor power supply voltage VM is applied to the drain-source voltages of the transistors 5 and 6, and the respective peak powers of (IP · VM) · (１ ／) are consumed.

[0011]

SUMMARY OF THE INVENTION The conventional MOS described above
When an output buffer H-bridge circuit is composed of N-channel MOS transistors, a power-supply-side transistor and a ground-side transistor are simultaneously turned on, so that a power supply / ground through current flows and power consumption increases. Had the disadvantage of destroying it.

Further, there is a disadvantage that a large spike noise is generated in the motor power supply terminal 3 and the ground terminal 4 due to the through current, thereby causing a malfunction of the integrated circuit and a destruction therefor.

An object of the present invention is to reduce the through current and spark noise so that an MO that does not malfunction or break down during switching is provided.
An object of the present invention is to provide an S-type semiconductor integrated circuit.

[0014]

According to the MOS type semiconductor integrated circuit of the present invention, first and second input signals are inputted to a control logic circuit, and the first and second input signals are passed through a level shift circuit connected to a high power supply terminal. A mode control circuit for supplying a gate control signal to a second internal input node; a first terminal having a drain connected to the power supply terminal, a source connected to the first output terminal, and a gate receiving the first gate control signal; A MOS transistor having a drain connected to the first output terminal, a source connected to the ground terminal, a gate connected to the second gate control signal, and a drain connected to the power supply terminal; Are connected to a second output terminal, the gate is a third MOS transistor for inputting the second gate control signal, and the drain is the second output terminal. Output buffer H to gate source is connected to the terminal connected to the ground terminal has a fourth MOS transistor for inputting the first gate control signal
A MOS type semiconductor integrated circuit including a bridge circuit for controlling forward, reverse and stop of a load current flowing between the first and second output terminals by the first and second input signals. A first feedback positive MOS transistor having a drain connected to the first internal input node, a source connected to the ground terminal, and a gate connected to the second output terminal; A second MOS transistor for positive feedback, which is connected to the second internal input node, has a source connected to the ground terminal, and has a gate connected to the first output terminal, is provided.

The threshold voltages of the first and second MOS transistors for positive feedback of the present invention are configured to be lower than the threshold voltages of the first to fourth MOS transistors of the output buffer H-bridge circuit. ing.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of one embodiment of the present invention. The difference between this embodiment and the conventional MOS semiconductor integrated circuit shown in FIG. 3 is that the output terminals 10 and 10 on the opposite side are located between the input nodes Na and Nb of the output buffer H bridge circuit 14a and the ground terminal. MOS for positive feedback connecting gate to 9
This is because the transistors 12 and 13 are added, and the others are the same.

In order to enhance the effect of reducing the through current between the power supply and the ground, the two N-channel MOS
It is desirable that the threshold voltages of transistors 12 and 13 be lower than the threshold voltages of transistors 5 to 8 constituting the output buffer H-bridge circuit.

The positive feedback MOS transistor 12 has a drain connected to the internal input node Na, a source connected to the ground terminal 4, and a gate connected to the output terminal 10.

The opposing MOS transistor 13 is
The drain is connected to the internal input node Nb, the source is connected to the ground terminal 4, and the gate is connected to the output terminal 9.

FIG. 2 is a voltage / current characteristic diagram at the time of mode switching for explaining the operation of the circuit of FIG. Now, when the gate control signal VNa is at the "H" level and the signal VNb is at the "L" level, the MOS transistor 5 and the opposing transistor 8 are conducting,
The potential V9 of the output terminal 9 is substantially the motor power supply voltage VM, and the potential V10 of the output terminal 10 is substantially 0V.

When the signal VNa changes from "H" to "L" and the signal VNb changes from "L" to "H", the MOS transistors 5 and 8 become non-conductive, and conversely, the MOS transistors 6 and 7 become conductive. become.

In the transient state of the current switching change, FIG.
As shown in FIG. 7, a time τ at which the transistor 6 on the ground side becomes conductive from the time t1 before the time t2 at which the transistor 5 on the power supply side becomes non-conductive occurs, during which a through current flows from the power supply terminal 3 to the ground terminal 4. Occurs. In order to reduce or prevent this, the charge / discharge switching time of the transistors 5 and 7 on the power supply side is shortened.

Generally, the speed at the time of interruption is important for preventing a through current, and it is necessary to shorten the gate discharge time. Therefore, N-channel MOS transistors 12 and 13 for positive feedback are added.

As a result, when MOS transistor 7 is turned on and output terminal potential V10, that is, the gate potential of MOS transistor 12, becomes higher than its threshold voltage, MOS transistor 12 is turned on and control signal VNa is turned to ground potential. To discharge the gate faster. The MOS transistor 13 works similarly.

As a result, as shown in FIG. 2, the switching time of the signal VNa, VNb from "H" to "L" is shorter than the rising time from "L" to "H". Since the time τ is significantly reduced as compared with the conventional time T, the peak current value IP of the through current I can also be significantly reduced.

Specifically, the conventional circuit shown in FIG.
The circuit according to the present embodiment generates a through current with a peak of 0.1.
1A or less could be achieved. Note that the lower the threshold voltage of the MOS transistors 12 and 13 for positive feedback, the lower the threshold voltage of the MOS transistors 5 and 8 constituting the output buffer H bridge circuit, the shorter the simultaneous ON time τ.

As another embodiment, when the MOS transistors 5 to 8 of the output buffer H-bridge circuit 14 are constituted by double diffusion type MOS transistors, the MOS transistor for positive feedback
The difference between the threshold voltages of the transistors 12 and 13 increases, and the through current can be further reduced.

[0028]

As described above, according to the present invention, the output buffer H-bridge circuit is provided with a MOS transistor for which positive feedback is applied from the output terminal to the input node of the control signal, so that the current of the output buffer H-bridge circuit is reduced. Since the time of the through current flowing through the transistors on the side and ground can be shortened, it is possible to prevent destruction due to an increase in the power consumption of the transistors constituting the bridge even for an input signal having a large rise and fall time, This has the effect of reducing spike noise generated at the ground terminal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a voltage / current characteristic diagram at the time of mode switching for explaining the operation of the circuit of FIG. 1;

FIG. 3 is a circuit diagram of an example of a conventional MOS semiconductor integrated circuit.

FIG. 4 is a circuit diagram of the mode control circuit of FIG. 3;

FIGS. 5A to 5C are circuit diagrams illustrating forward, reverse, and stop modes of an output buffer H-bridge circuit, respectively.

FIG. 6 is a voltage-current characteristic diagram at the time of mode switching for explaining the operation of the circuit of FIG. 3;

[Explanation of symbols]

 1a, 1b Input terminal 2a, 2b, 3 Power supply terminal 4 Ground terminal 5-8 MOS transistor 9, 10 Output terminal 11 Mode control circuit 12, 13 Positive feedback MOS transistor 14, 14a Output buffer H bridge circuit 15 Control logic circuit 16a , 16b Level shift circuit M Motor Na, Nb Input node VM Motor power supply voltage VNa, VNb Gate control signal V1a, V1b I Through current Ip Through current peak value T Through current time

Claims (2)

(57) [Claims] 1. A mode in which first and second input signals are input to a control logic circuit and a gate control signal is supplied to first and second internal input nodes via a level shift circuit connected to a high power supply terminal. A control circuit, a first MOS transistor having a drain connected to the power supply terminal, a source connected to the first output terminal, a gate connected to the first gate control signal, and a drain connected to the first output terminal A second MOS transistor having a source connected to the ground terminal and a gate inputting the second gate control signal, a drain connected to the power supply terminal, a source connected to the second output terminal, and a gate connected to the second output terminal. A third MOS transistor for inputting the gate control signal of the third gate, a drain connected to the second output terminal, a source connected to the ground terminal, and a gate. And an output buffer H-bridge circuit having a fourth MOS transistor for inputting the first gate control signal, wherein the first and second input signals allow the output buffer H-bridge circuit to be connected between the first and second output terminals. In a MOS type semiconductor integrated circuit which controls forward, reverse and stop of a flowing load current, the output buffer H bridge circuit comprises:
A first positive feedback MOS transistor having a drain connected to the first internal input node, a source connected to the ground terminal, and a gate connected to the second output terminal, and a drain connected to the second internal input node; A MOS-type semiconductor integrated circuit, further comprising a positive feedback second MOS transistor connected to an input node, a source connected to the ground terminal, and a gate connected to the first output terminal. 2. The threshold voltage of the first and second MOS transistors for positive feedback is lower than the threshold voltages of the first to fourth MOS transistors of the output buffer H-bridge circuit. The MOS type semiconductor integrated circuit according to claim 1.