JPS594890B2 - digital circuit - Google Patents

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a heterogeneous channel type insulated gate field effect transistor.
Effect transistor is hereinafter referred to as IGFET.

) is related to a voltage level shift circuit using.

[Technical background of the invention and its problems]

In general, in digital logic systems, the need to perform logic amplitude conversion often arises.

For example, when the output of a logic circuit operating at a low logic level is input to a logic circuit operating at a high logic level, overflow occurs.

In this case, a voltage level shift circuit is used as an intermediary.

Voltage level shift circuits such as those shown generally in FIGS. 1, 2, and 3 are well known.

All of these voltage level shift circuits have a load resistor and a driver transistor connected in series between a power supply terminal and a reference (earth) terminal.

A logic circuit (not shown) that operates at a voltage level lower than the power supply voltage level.

) is applied to the input terminal of the level shift circuit, the inverter function of this level shift circuit will output a level-shifted voltage according to the power supply level that drives this level shift circuit to the output of this level shift circuit. can do.

However, in the conventional voltage level shift circuits shown in Figures 1, 2, and 3, when the driver transistor is turned on, more current flows into the reference terminal than the power supply terminal, reducing power consumption. It has the disadvantage that it becomes

[Purpose of the invention]

An object of the present invention is to provide a voltage level shift circuit that eliminates the drawbacks of the conventional level shift circuits as described above and can reduce power consumption.

[Summary of the invention]

This invention provides a first power supply terminal to which a first voltage VDDt is supplied, and a second voltage vDD2 different from the first voltage VDD.
a second power supply terminal to which a reference potential is supplied, a reference voltage terminal to which a reference potential is supplied, a first output terminal, a second output terminal, a first
an input terminal, a second input terminal, a first inverter driven using the first voltage VDDt, a second inverter driven using the first voltage VDDt, and a second power supply terminal. (c) an eleventh GFET of a first conductivity type connected in series between the first output terminal and the second output terminal; an IGFET, a first logic circuit formed between the first output terminal and the reference voltage terminal and having a multi-input terminal, and a first logic circuit formed between the second output terminal and the reference voltage terminal and having a multi-input terminal. a second logic circuit having a terminal, means for connecting the gate of the eleventh GFET and the second output terminal, and a means for connecting the gate of the second IGFET and the first output terminal;
means for connecting the first input terminal to the input terminal of the first inverter; and means for connecting the first input terminal to the input terminal of the first inverter;
means for connecting an input terminal to an input terminal of the second inverter; and each input/output A, A, of the first and second inverters;
B, B to the multi-input terminal of the first logic circuit; and means for supplying inputs and outputs A, λ, and B of the first and second inverters;
, B to the multi-input terminal of the second logic circuit.

This is a voltage level shift circuit characterized by the following.

That is, in this invention, the connection configuration as described above,
Since it includes a first inverter, a second inverter, an eleventh GFET, a second IGFET, a multi-input first logic circuit, and a multi-input second logic circuit, the second voltage can be input from the first output terminal or the second output terminal. It is possible to obtain a target voltage level shift circuit that can extract a shift voltage according to the level and consumes little power.

[Embodiments of the invention]

A representative embodiment according to the invention is shown in FIG.

Now, in order to better understand the voltage level shift circuit of the present invention shown in FIG. 6, the basic idea of the invention will be explained using the voltage level shift circuit shown in FIGS. I will explain using

First, to explain the voltage level shift circuit shown in FIG. 4, 14 and 15 are enhancement type P-channel insulated gate field effect transistors, and 16 and 17 are enhancement type P-channel insulated gate field effect transistors having a different conductivity type from the above. It is an N-channel insulated gate field effect transistor.

One of the signal input terminals 11 is grounded, and the other is connected to the gate of the transistor 16 and the connection point 12 which is the input side of the inverter 130.

The output side of the inverter 13 is connected to the gate of the transistor 17.

Note that the inverter 13 is connected to the power supply vDD1 and ground.

The sources of transistors 16 and 17 are grounded, and the sources of transistors 14 and 15 are connected to power supply VDD2.

Connection point (first output terminal) 18 is transistor 14.1
6 and the gate of the transistor 15, and further connected to one of the output terminals 19.

The other output terminal 19 is grounded.

The connection point (second output terminal) 20 is the transistor 15.1
7 and the gate of the transistor 14, and further connected to one of the output terminals 21.

The other output terminal 21 is grounded.

The operation of the circuit shown in FIG. 4 above is as follows.

When an input signal is applied to the input terminal 11, an output signal whose amplitude is converted and whose polarity is opposite to that of the input signal is obtained from the output terminal 19.

Further, from the output terminal 21, an amplitude-converted output signal having the same polarity as the input signal is obtained.

Here we set the initial state of this circuit.

It is assumed that transistors 15 and 16 are in the OFF state and transistors 14 and 17 are in the ON state.

This state corresponds to a state in which the input signal is at a low level, the output signal at the output terminal 19 is at a high level, and the output signal at the output terminal 21 is at a low level.

Next, considering a transient state in which the input signal changes from a low level to a high level, first the transistor 16 is turned on.
state, the transistor 17 is inverted to the "OFF" state, respectively.

Therefore, at this moment transistors 14 and 16 are simultaneously turned on.
It becomes N” state.

If the voltage at the connection point 18 satisfies the following equation (1) at this moment, the transistor 15 is immediately inverted to the "ON" state.

Therefore, since the transistor 11 has already been inverted to the "OFF" state, the transistor 14 is inverted to the "OFF" state and becomes a steady state.

In particular, Ronl 6 : Saturation resistance Ron of transistor 16
14: Saturation resistance RGs15 of transistor 14:)
When the gate-source voltage of the transistor 15 necessary to saturate the transistor 15, that is, the transistor 14.17 is in the "OFF" state,
The transistors 15 and 16 are turned on, and a low level output signal is obtained at the output terminal 19 and a high level output signal is obtained at the output terminal 21.

Next, when the input signal changes from high level to low level, if the following equation (2) is satisfied, the transistor 1
4 can be reversed from the OFF" state to the ON" state.

Therefore, in steady state, transistor 14.17 is
When the transistors 15 and 16 are in the "OFF" state, a high level output signal is obtained at the output terminal 19 and a low level output signal is obtained at the output terminal 21.

Here, Ronl 7: Saturation resistance Ron of transistor 17
15: ) Saturation resistance vGs of transistor 15 14:
The gate-source voltage of transistor 14 required to bring transistor 14 into saturation results in transistors 16, 17 and inverter 13.
If we use field effect transistors 14 and 15 whose absolute values of threshold voltages are higher than the absolute values of threshold voltages of the field effect transistors constituting the field effect transistors and set vDDl<vDD2,
It becomes possible to take out a logic amplitude larger than the logic amplitude applied to the input terminal 11 from the output terminal 19.21.

It is clear that the reverse is also possible.

That is, if formulas (1) and (2) are satisfied, VDDl and v
By setting with DD2, logical amplitude conversion can be performed.

Further, the current consumed is only the current that flows during an extremely short period of time within the switching time of the transistors 14 and 15, so by shortening the switching time, the average power consumption can be extremely reduced.

Next, the voltage level shift circuit shown in FIG. 5 will be explained.

As shown in FIG. 5, the series circuit 5, form 6, (1)
The values of Ronl4 and Ronl5 in equation (2) can be increased with equality constraints.

This means that the operating conditions expressed by equations (1) and (2) can be adjusted by the resistor.

Therefore, according to FIG. 5, the resistance is 22'.

By choosing the value of 23, transistor 14.1
5, 16, 17 dimension settings are more flexible,
This has the effect that circuit design can be easily performed in pattern arrangement and pattern design.

Furthermore, in FIGS. 4 and 5, transistors 16 and 17
By using N-channel insulated gate field effect transistors instead, it is possible to configure various digital circuits and perform logic amplitude conversion at the same time.

Through these steps, the present invention as shown in FIG. 6 was born.

As is clear from the figure, the voltage level shift circuit shown in FIG. 6, which is a typical embodiment of the present invention, consists of a first power supply terminal 1 to which a first voltage vDD1 is supplied, A second power supply terminal 3 to which a second voltage VDD2 different from the voltage VDDI is supplied, a reference voltage terminal 2 to which a reference potential (earth) is supplied, a first output Vout terminal 18, a second output terminal 20, 1 human power Vin terminal and 2nd human power Vin terminal
a first inverter 13a driven using the first voltage VDI)+, a second inverter 13b driven using the first voltage VDD+, and a first inverter 13b driven using the first voltage VDD+;
an eleventh GFET (for example, a P-channel insulated gate field effect transistor) 14 of a first conductivity type connected in series between the power supply terminal 3 and the first output terminal 18; and the second power supply terminal 3 and the second output terminal. 20, a first conductivity type IGFET (for example, a P-channel insulated gate field effect transistor) 15 connected in series between the first output terminal 18 and the reference voltage terminal 2, and a multi-input A first logic circuit (e.g., consisting of four n-channel insulated gate field effect transistors, as shown in FIG. 6) having terminals for A, B, PER, and B.

) is formed between the second output terminal 20 and the reference voltage terminal 2, and has a large power A5.

A second logic circuit (e.g., consisting of four n-channel insulated gate field effect transistors, as shown in FIG. 6) having terminals for B and B;

), the gate of the first IGFETl 4 and the second
means for connecting the output terminal 20 and the second IGFET;
15 and the first output terminal 18; means for connecting the first input terminal to the input terminal of the first inverter; and connecting the second input terminal to the input terminal of the second inverter. means for connecting and each input/output A of the first and second inverters.

means for supplying A, B, and B to the gates (multi-input terminals) of each IGFET of the first logic circuit, as shown in FIG. ,
B, B to the gates (multi-input terminals) of the respective IGFETs of the second logic circuit as shown in FIG.

As is clear from the figure, the voltage level shift circuit shown in FIG. 6 has approximately the same basic configuration as the circuits shown in FIGS. As is clear from the description of each circuit in FIG. 5, logical amplitude conversion can be performed by setting the first voltage vDD1 and the second voltage VDD2.

Further, the current consumed in the voltage level shift circuit shown in FIG. 6 can be reduced for substantially the same reason as in the case of the circuits shown in FIGS. 4 and 5.

Although not shown in FIG. 6, as in the circuit of FIG. 5, a resistor or equivalent resistance (indicated by numbers 22, 23 in FIG. 5) is connected to the IGFET 14. By using it in series connection with 15, Ronl 4 and Ro of the above equations (1) and (2) in the explanation of the circuit of FIG.
It is possible to obtain the same effect as when the value of nl 5 can be increased with equal constraints.

In other words, the operating conditions expressed by the above equations (1) and (2) can be adjusted by using the resistor.

Furthermore, in FIG. 6, as is clear from the figure, the first logic circuit forms an exclusive NOR circuit,
The second logic circuit forms an exclusive OR circuit, and these logic circuits are also used together with the voltage level shift circuit. This has the effect that the number of elements can be reduced compared to a circuit in which the husband is provided independently.

〔Effect of the invention〕

Therefore, as is clear from the above description, according to the present invention, it is possible to provide a voltage level shift circuit that can reduce power consumption.

[Brief explanation of the drawing]

Figures 1, 2, and 3 are wiring diagrams of conventional voltage level shift circuits; Figure 4 is a wiring diagram of a voltage level shift circuit for explanation to help understand the basic idea of the present invention; FIG. 5 is a wiring diagram of a voltage level shift circuit for explaining the basic idea of the present invention, and FIG. 6 is a wiring diagram of a voltage level shift circuit showing a typical embodiment of the present invention. It is.

Claims (1)

[Claims] 1. A first power supply terminal 1 to which a first voltage vDD1 is supplied;
A second power supply terminal 3 to which a second voltage VDD2 different from the first voltage VDDt is supplied, a reference voltage terminal 2 to which a reference potential is supplied, a first output terminal 18, a second output terminal 20, a first an input terminal, a second input terminal, and the first voltage VD
A first inverter 13a driven using Dt;
A second inverter 13b driven using the first voltage VDDt, and a first IG of a first conductivity type connected in series between the second power supply terminal 3 and the first output terminal 18.
FET 14 and a second IGFE of a first conductivity type connected in series between the second power supply terminal 3 and the second output terminal 20.
T15, the first output terminal 18 and the reference voltage terminal 2
a first logic circuit formed between the second output terminal 20 and the reference voltage terminal 2 and having a multi-input terminal; a second logic circuit formed between the second output terminal 20 and the reference voltage terminal 2 and having a multi-input terminal; 11 The gate of GFET 14 and the second output terminal 20
means for connecting the gate of the second I GFET 15 and the first output terminal 18; means for connecting the first input terminal to the input terminal of the first inverter; means for connecting an input terminal to an input terminal of the second inverter, and each input/output A, A, B of the first and second inverters. means for supplying B to a multi-input terminal of the first logic circuit;
Each input/output A of the first and second inverters. and means for supplying λ, B, and B to multiple input terminals of the second logic circuit. 2. The voltage level shift circuit according to claim 1, wherein the first and second logic circuits are an exclusive NOR circuit or an exclusive OR circuit.