JPH06224703A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain the semiconductor integrated circuit whose circuit operation is quickened without increasing the drive capability of a drive circuit of a pre-stage, whose power consumption is low and in which no inverted clock signal is required. CONSTITUTION:The integrated circuit is provided with a couple of MOS transistor groups 1a, 1b whose gate receives a couple of complementary input signal groups set between two different reference potential points, a 1st switching TR Q1 turned on/off by a clock signal, and a couple of 2nd switching TRs Q21, Q22 in cross connection to the said couple of MOS transistor groups 1a, 1b.

Description

Detailed Description of the Invention

The present invention relates to a semiconductor integrated circuit, and more particularly to a CM
The present invention relates to an OS dynamic semiconductor integrated circuit.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit, a source electrode is connected to a first reference potential point (ground potential point) and a clock signal CK is input to a gate electrode to turn it on, as shown in FIG.
Between an N-type transistor Q6 which is turned off and a plurality of N-type second transistors which are turned on and off by correspondingly inputting input signals IN1 to INn to the gate electrodes, respectively, between the drain electrode of the transistor Q6 and the output terminal. Connected to the first input signal INl to INn according to a predetermined logic to turn on / off between the drain electrode and the output terminal of the transistor Q6, and the source electrode to a second reference potential point. The P-type first transistor Q7 which is connected to the (power supply potential point) and inputs the inverted signal CLKb of the clock signal CLK to the gate electrode to turn on and off, and the input signals INl to INn corresponding to the gate electrodes, respectively. A plurality of P-type second transistors for turning on and off are provided, and the first logic is connected between the drain electrode of the transistor Q7 and the output terminal. On between the drain electrode and the output terminal of the transistor Q7 have a complementary relationship to each other and the road section 1k, it has been a configuration and a second logic circuit portion 1m for off (IEEE J.Solid-Sta
te Circuits, 1973, 462-46.
Page 9, "Clocked CMOS Calculator Circuitry"
ulator Circuit)).

This semiconductor integrated circuit has a clock signal CK.
Is high level, the transistors Q6 and Q7 are turned on. At this time, depending on the levels of the input signals INl to INn, the logic circuit units 1m and N of the P-type transistor group are formed.
Type logic group logic circuit section 1k is turned on in one side and turned off in the other side, and output signal OUT is high.
Level or low level. Normal CM at this time
The operation is similar to that of the OS circuit. Output signal OUT is High
When changing from the h level to the low level, a conduction path by an N-type transistor is formed in the logic circuit section 1k between the output terminal and the ground potential point, and the logic circuit is provided between the output terminal and the power supply potential point. It is electrically isolated by the P-type transistor in the portion 1m. Low level to H
When changing to the high level, the reverse operation is performed.
The speed of change depends on the capability of each transistor (channel width of the transistor).

When the clock signal CLK goes low, the transistors Q6 and Q7 are turned off, so that the output terminal is electrically disconnected from the power supply potential point and the ground potential point. At this time, the output signal OUT is the input signals INl to IN.
Regardless of the level of n, the level immediately before the clock signal CK changes to the Low level is dynamically held by the capacitance connected to the output terminal.

[0005]

In order to speed up the circuit operation in this semiconductor integrated circuit, the logic circuit section 1k,
It is necessary to widen the channel width of the 1 m transistor, which increases the input capacitance.

In this conventional semiconductor integrated circuit, the two transistors of the logic circuit portions 1k and 1m are driven by one input signal, and if the channel width of these transistors is widened to increase the speed, the input is performed. Since the capacity increases, it is necessary to increase the drive capability of the drive circuit at the previous stage that drives the logic circuit units 1k and 1m, and there is a problem that the power consumption increases. Therefore, high-speed circuit operation cannot be realized. In addition to the clock signal CLK, the inverted signal CLKb thereof is required.

FIG. 16 shows another conventional example of this type of semiconductor integrated circuit. The clock signal CLK,
The first transistor Q6 which is turned on / off by CLKb
The configuration is exactly the same as that of FIG. 1 except that Q7 is arranged between the logic circuit portions 1m and 1k formed of the second transistor with the output terminal OUT interposed therebetween. The operation is also exactly the same as the conventional example of FIG. That is, when the clock signal CLK is at high level, the N-channel type MOS transistor Q6 and the P-channel type MOS transistor Q7 are turned on. At this time, the input signal groups INl to I
Depending on each signal level of Nn, the respective MOS transistors of the logic circuit section 1m composed of the P-channel type MOS transistor group and the logic circuit section 1k composed of the N-channel type MOS transistor group are turned on or off, and the circuit is at the high level or It outputs a low level signal. At this time, normal CMOS circuit operation is performed. When the output changes from the High level to the Low level, a conduction path by an N-channel MOS transistor is formed between the output terminal OUT and the GND electrode, and the P-channel MO transistor is provided between the output terminal OUT and the VDD electrode.
The S-transistor is electrically disconnected. When changing from the Low level to the High level, the opposite is true. The speed at which each MO changes
It depends on the capability of the S transistor (channel width of the MOS transistor).

When the clock signal CLK becomes low level, the N-channel type MOS transistor Q6 and the P-channel type MOS transistor Q7 are turned off, so that the circuit is electrically disconnected from the VDD electrode and the GND electrode. At this time, the output is dynamically held at the level immediately before the clock signal CLK is changed to the Low level regardless of the signal levels of the input signal groups INl to INn by the capacitance of the output terminal.

Also in this conventional semiconductor integrated circuit, just as in the above-mentioned conventional example, in order to speed up the circuit operation, it is necessary to widen the channel width of the MOS transistor, and the input capacitance increases. As the input capacitance increases, signals input to this circuit (input signal group IN
The delay values of 1 to INn, the clock signal CLK, and the inverted signal CLKb) of the clock signal increase. In order to reduce the delay value, it is necessary to increase the driving capability of the circuit that generates these signals. In addition, the increased input capacitance increases the power consumption of the circuit that generates these signals. The input signal groups INl to INn have a logic circuit unit 1m.
And the logic circuit section 1k are both input, the widening of the channel width of these MOS transistors has a large effect.

Further, not only the clock signal CLK but also the inverted signal CLKb is necessary for controlling the operating state.

Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art, to speed up the circuit operation without increasing the driving capability of the driving circuit in the preceding stage, and thus to reduce the power consumption, Another object is to provide a semiconductor integrated circuit that does not require an inverted signal of a clock signal.

[0012]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention includes a complementary pair arranged in parallel between a first reference potential point and a second reference potential point. A pair of transistors, each transistor pair being a MOS transistor group, and receiving a pair of complementary input signal groups corresponding to the respective transistor pairs at the gates of the respective constituent transistors. Are connected in series between the pair of MOS transistor groups that are turned on and off in accordance with the above, the pair of parallel MOS transistor groups between the first and second reference potential points, or each of these transistor group pairs. It is arranged between one or two first switching transistors that are turned on and off by a clock signal of a kind and the first and second reference potential points. Parallel M each of said pair with
A pair of second switching transistors connected in series to each transistor pair of the OS transistor group, wherein a pair of electrode terminals on the side of the pair of MOS transistor groups of the second switching transistors are connected to each other. The output terminal of the device, and the gate of each of these second switching transistors is the pair of MOS transistors.
The complementary MOS transistor groups on the opposite side of the transistor group are directly or directly connected via the one or two switching transistors, and the electrode terminals on the opposite side of the output side terminals of these switching transistors are connected to the output side terminals. It is provided with a pair of second switching transistors connected to either the first or second reference potential point.

[0013]

In the present invention, when the clock signal is at the high level, the first switching transistor is turned on, and when the complementary input signal group is input to the gate of the MOS transistor group forming a complementary pair, these inputs are input. Depending on the level of the signal, for example, the second reference potential point is brought into conduction, one of the pair of MOS transistor groups is brought into conduction, and the other is brought out of conduction, so that it is separated from the second reference potential point, for example. As a result, for example, the M of one of the pair of output terminals of the device is
One output terminal connected to the OS transistor group is Lo
w level. Further, among the second switching transistors, the transistor on the side of the other pair of MOS transistors is turned on because its gate is connected to the output terminal. Therefore, the other output terminal is Hi
It becomes gh level.

Therefore, the other transistor of the second switching transistors is turned off. As described above, between the first and second reference potential points, the second switching transistor and the one MOS transistor group are electrically connected to each other, and the second switching transistor and the other MOS transistor group which are complementary thereto are electrically connected to each other. Paths are formed, but neither of them is connected to the reference potential point on either side, and a steady current does not flow through these paths.

When the clock signal is at the low level, the first switching transistor is in the off state. Therefore, each output terminal is electrically disconnected from the second reference potential point regardless of the level of the input signal group.
Therefore, the output terminal cannot be changed to the Low level. Further, the second switching transistor cannot change its conduction state by the input signal. Therefore, each output terminal dynamically holds the level immediately before the clock signal changes from the high level to the low level by the capacitance of these output terminals.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a circuit configuration diagram showing an embodiment of a semiconductor integrated circuit according to the present invention. In this embodiment, a source electrode is connected to a first reference potential point (ground potential point), an N-type first transistor Q1 that turns on and off by inputting a clock signal CLK to the gate electrode, and a gate electrode, respectively. The first transistor Q is provided with a plurality of N-type second transistors that turn on and off by inputting corresponding first input signals INl to INn.
The drain electrode of the first transistor Q1 and the first output terminal (OUT1) according to a predetermined logic for the first input signals IN1 to INn, which are connected between the first drain electrode and the first output terminal (OUT1). The first logic circuit section 1a for turning on and off the input terminals and the second input signals INlb-INnb having logic levels complementary to the first input signals INl-INn corresponding to the gate electrodes are input. The first logic circuit unit 1 includes a plurality of N-type third transistors that are turned on and off, and is connected between the drain electrode of the first transistor Q1 and the second output terminal (OUT2).
The second logic circuit portion lb for turning on and off between the drain electrode of the first transistor Q1 and the second output terminal (OUT2) so as to have a complementary relationship with a and the source electrode for the second logic circuit portion lb. A P-type first transistor Q21 and a source electrode connected to a reference potential point (power supply potential point), a drain electrode connected to a first output terminal (OUT1), and a gate electrode connected to a second output terminal (OUT2) Is connected to a second reference potential point (power supply potential point), the drain electrode is connected to the second output terminal (OUT2), and the gate electrode is connected to the first output terminal (O2).
The unit integrated circuit 10 includes a load circuit 2 including a P-type second transistor Q22 connected to the UT 1).

Next, the operation of this embodiment will be described.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of this embodiment.

When the clock signal CLK is at the high level, the transistor Q1 is on. At this time, depending on the level of the input signals INl to INn and INlb to INnb, a conduction path is formed between one of the logic circuit sections 1a and 1b between the output terminal and the ground potential point, and the other is electrically disconnected. . Here, for example, it is assumed that the logic circuit unit 1a is in a conductive state and the logic circuit unit 1b is in a disconnected state. Since the output terminal (OUT1) is electrically connected to the ground potential point, it becomes Low level. Further, the transistor Q22 is turned on because its gate electrode is connected to the output terminal (OUT1). Therefore, the output terminal (OUT2) is connected to the logic circuit section 1b.
Since it is electrically separated from the ground potential point by
It becomes the high level. Therefore, the transistor Q21 is turned off. As described above, the path between the power supply potential point and the ground potential point includes the path formed by the transistor Q21 and the logic circuit section 1a and the path formed by the transistor Q22 and the logic circuit section 1b, both of which are electrically separated. It is in a broken state. Therefore, a steady current does not flow.

When the clock signal CLK is at low level,
The transistor Q1 is off. Therefore, the output terminals (OUT1, OUT2) are connected to the input signals IN1 to IN1.
It is electrically disconnected from the ground potential point regardless of the levels of n and INlb to INnb. Therefore, the output terminals (OUT1, OUT2) cannot be changed to the Low level. Also, the transistors Q21 and Q22 are
The conduction state cannot be changed by the input signals INl to INn and INlb to INnb. Therefore, each output terminal (OUT1, OUT2) dynamically holds the level immediately before the clock signal CLK changes from the High level to the Low level by the capacitance connected to each output terminal (OUT1, OUT2).

In this embodiment, the drive circuit in the preceding stage is one of the logic circuit sections 1a and 1b for each input signal.
Since only one transistor needs to be driven, compared with the conventional example, it is only necessary to drive about 1/2 the input capacitance, and high speed operation and low power consumption can be achieved. Also, the output terminal OUT1,
When the level of the output signal appearing at OUT2 changes to the High level, it is performed by one transistor (Q21 or Q22) of the load circuit 2 instead of being performed by the plurality of transistors by the logic circuit unit 1m as in the conventional example.
Higher speed can be achieved. Further, the clock signal CLK does not need its inverted signal.

FIG. 3 is a circuit diagram showing a modification of the first embodiment.

In this modification, the first reference potential point is the power supply potential point, the second reference potential point is the ground potential point, one conductivity type is P type, and the opposite conductivity type is N type. The basic operation and effect are similar to those of the first embodiment. However,
Those corresponding to the logic circuit units 1a and 1b in FIG. 1 are shown as logic circuit units 1c and 1d.

FIG. 4 is a circuit diagram of a D flip-flop constructed by using the first embodiment of the present invention shown in FIG.

This flip-flop has transistors Q11, Q12, Q1 each having one logic circuit section.
3, Q14 and logic circuit sections 1e, 1f, 1g, 1
and the unit integrated circuit including the logic circuit units 1e and 1f is set to 1
0b, the unit integrated circuit including the logic circuit portions 1g and 1h is 10c, and the output terminal OUT1 of the unit integrated circuit 10b is
The output signal appearing at OUT2 is used as the input signal of the unit integrated circuit 10c, and the clock signals input to the gate electrodes of the transistors Q3 and Q4 are inverted signals so that the clock signals have opposite phases.

Next, the operation of this flip-flop will be described.

When the clock signal CLK is at low level,
The unit integrated circuit 10b is activated, and output signals are obtained at its output terminals OUT1 and OUT2 according to the input signals D and Db. At this time, the unit integrated circuit 10c includes the transistor Q
Since 4 is off, the level of the output signal of the output terminals OUT3 and OUT4 in the previous cycle is held regardless of the level of the output signal. When the clock signal CLK changes to the high level, the unit integrated circuit 10c outputs the output signal to the output terminals OUT3 and OUT4 according to the level of the output signal of the output terminals OUT1 and OUT2 at that time. At this time, even if the levels of the input signals D and Db change, the unit integrated circuit 10b outputs the output signals of the output terminals OUT1 and OUT2 according to the levels of the input signals D and Db before the clock signal CLK changes to the High level. Holds the level.
Therefore, when the clock signal CK is at the high level, even if the levels of the input signals D and Db change, the output terminal OUT
The output signal levels of 3 and OUT4 do not change.

As described above, by connecting two unit integrated circuits of the first embodiment in cascade, a D flip-flop can be constructed.

FIG. 5 is a circuit diagram of a D flip-flop constructed by combining the first embodiment of the present invention shown in FIG. 1 and its modification shown in FIG.

In this flip-flop, in the unit integrated circuit 10b of the flip-flop shown in FIG. 4, the logic circuit portion of the modification shown in FIG. 3 is configured by one transistor Q15 and Q16, respectively. It is replaced by the unit integrated circuit 10d which is 1i and 1j.

In this flip-flop, the transistors Q4, which control activation of the unit integrated circuits 10c, 10d.
Since the conductivity type of Q5 is different, common clock signal CLK
There is an advantage that it can be controlled by the above, and its inverted signal becomes unnecessary.

FIG. 6 is a block diagram of a pipeline semiconductor integrated circuit which performs a pipeline operation by connecting a plurality of the D flip-flops shown in FIG. 4 in cascade. In FIG. 6, (N) in the unit integrated circuits 10b and 10c indicates that the logic circuit portion and the like are formed by N-type transistors.

FIG. 7 is a block diagram of a pipeline semiconductor integrated circuit that performs a pipeline operation by connecting a plurality of the D flip-flops shown in FIG. 5 in cascade. In FIG. 7, (N) and (P) of the unit integrated circuits 10c and 10d indicate that the logic circuit portion and the like are formed by N-type transistors and P-type transistors, respectively. The operation of the semiconductor integrated circuit shown in FIGS.
Since it is basically the same as the D flip-flop shown in FIGS. 4 and 5, it is omitted.

In the first embodiment described above, the one-conductivity-type first transistor in which the source electrode is connected to the first reference potential point and the clock signal is input to the gate electrode,
A first logic circuit unit formed of a second transistor of the same conductivity type that inputs a first input signal corresponding to a gate electrode and connected between a drain electrode of the first transistor and a first output terminal And a first logic transistor formed of a third transistor of one conductivity type for inputting a second input signal corresponding to the gate electrode, connected between the drain electrode of the first transistor and the second output terminal. Higher speed and lower power consumption by having a configuration including a second logic circuit portion that takes a complementary logic to the circuit portion and a load circuit including two transistors of reverse conductivity type in which gate electrodes and drain electrodes are cross-connected It is possible to realize the same, and there is an effect that the inverted signal of the clock signal becomes unnecessary.

Next, a second embodiment according to the present invention will be described with reference to FIG.

The difference between the second embodiment and the first embodiment is that two switching transistors for receiving a clock signal are provided and the arrangement thereof is changed.

FIG. 8 is a circuit configuration diagram showing a second embodiment according to the present invention, and FIG. 9 is a timing diagram thereof.

Referring to FIGS. 8 and 9, INl to I
Nn is an input signal group, and INlb to INnb are input signal groups 1
Input signal group which is logically opposite to a, Q31 and Q32 are P channel type MOS transistors, 3a and 3b are logic circuit sections which are composed of N channel type MOS transistor group, and Q41 and Q42 are N channel type. The MOS transistors OUT1 and OUT2 are output terminals for outputting signal levels whose logics are opposite to each other, C
LK and CLKb represent clock signals for controlling the operating state, respectively.

P-channel type MOS transistor Q31
Has a source electrode connected to the VDD electrode (second reference potential point), a gate electrode connected to the output terminal OUT2, and a drain electrode connected to the source electrode of the N-channel MOS transistor Q41 and the output terminal OUT4. The source electrode of the P-channel MOS transistor Q32 is VD
The gate electrode is connected to the output terminal OUT1 and the drain electrode is connected to the source electrode of the N-channel MOS transistor Q42 and the output terminal OUT2, respectively, to the D electrode (second reference potential point). The drain electrode of the N-channel transistor Q41 is the drain electrode of the P-channel MOS transistor Q31 and the output terminal OUT1.
The gate electrode is connected to the clock signal CLK, and the source electrode is connected to the MOS transistor group 3a.
The drain electrode of the N-channel transistor Q42 is the drain electrode of the P-channel MOS transistor Q32 and the output terminal OUT2, the gate electrode is the clock signal CLKb, and the source electrode is the MOS transistor group 3b.
Respectively connected to. MOS transistor group 3a
The gate electrode of the N-channel type MOS transistor which constitutes this is connected to the input signal group IN, and the source electrode and the drain electrode are connected in series and parallel to each other.
It is connected between the source electrode and the GND electrode of the OS transistor Q41. In the logic circuit portion 3b, the gate electrode of the N-channel type MOS transistor constituting the logic circuit portion 3b is connected to the input signal group INb, the source electrode and the drain electrode are connected in series and parallel to each other, and the source electrode and the GND electrode of the N-channel type MOS transistor Q42 ( (A first reference potential point).

Clock signals CLK and CLKb are High
At level, N-channel type MOS transistor Q4
1, Q42 is in the ON state. At this time, the input signal group I
Depending on the respective signal levels of N and INb, one of the logic circuit portions 3a and 3b brings the output terminal and the GND electrode into a conductive state, and the other is brought into an electrically disconnected state. Here, for example, the logic circuit unit 3a is in a conductive state, and the logic circuit unit 3b is
Makes the GND electrode and the output terminal OUT2 electrically disconnected. Since the output terminal OUT1 is electrically connected to the GND electrode, it becomes a low level. Since the gate electrode of the P-channel type MOS transistor Q32 is connected to the output terminal OUT1, it is turned on. The output terminal OUT2 becomes High level because it is electrically separated from the GND electrode by the logic circuit unit 3b. Therefore, the P-channel type MOS transistor Q31 is turned off. In this way, the VDD electrode (second reference potential point) and the GND
The path to the electrode (first reference potential point) is a P channel type M
There is a path formed by the OS transistor Q31 and the logic circuit section 3a, and a path formed by the P-channel type MOS transistor Q32 and the logic circuit section 3b.
It is electrically isolated by the OS transistor. Therefore, a steady current does not flow. The same applies when the states of the logic circuit portions 3a and 3b are opposite.

When the clock signals CLK and CLKb are at low level, the N-channel type MOS transistor Q41,
Q42 is in the OFF state. For this purpose, each output terminal OU
T1 and OUT2 are electrically disconnected from the GND electrode regardless of the signal levels of the input signal groups IN and INb. Therefore, the output terminals OUT1 and OUT2 are set to Low.
It cannot be changed to a level. Further, the conduction states of the P-channel type MOS transistors Q31 and Q32 cannot be changed by the input signal groups IN and INb. Therefore, the output terminals OUT1 and OUT2 have the levels immediately before the clock signals CLK and CLKb change from the high level to the low level.
Dynamically held by the capacity of UT2.

FIG. 10 is a circuit diagram showing a modified example of the second embodiment. The difference between this modification and the second embodiment is that the logic circuit portions 3c and 3d are arranged on the second reference potential point side and the conductivity type of the element is reversed, but the operation thereof is different. Since it is the same as that of the second embodiment, its explanation is omitted.

FIG. 11 is a circuit diagram in the case where a D flip-flop is constructed by cascading the circuits 20b and 20c of the second embodiment.

Referring to FIG. 11, D and Db are data inputs of a D flip-flop, Q35 to Q38 are P-channel MOS transistors, and 3e to 3h are N-channel MOS transistor groups (here, they are MOS transistor groups). (Only one transistor is shown), Q65 to Q68 are N-channel MOS transistors, OUT1 to OUT4 are output terminals, CLK, CLK.
Symbols b respectively indicate clock signals for controlling the operating state. OUT3 (Q) and OUT4 (Qb) are output terminals of the D flip-flop. Clock signal CLKb
Is an inverted signal of the clock signal CLK. The output signals appearing at the output terminals OUT1 and OUT2 of the circuit 20b become the input signals of the circuit 20c. Clock signal CLK is Lo
At the w level, the circuit 20b outputs its output to the output terminals OUT1 and OUT2 according to the input signals D and Db. At this time, the circuit 20c outputs the output terminals OUT1 and OU.
Output terminals OUT3 (Q), OU regardless of the level of T2
The output level is held at T4 (Qb). When the clock signal CLK changes to the high level, the circuit 20c causes the output terminals OUT1 and OUT of the circuit 20ba at that time.
2 according to the output level of the output terminal OUT3
(Q) and OUT4 (Qb). At this time, even if the levels of the input signals D and Db change, the circuit 20b holds the output level according to the levels of the input signals D and Db before the clock signal CLK changes to the High level. Therefore, when the clock signal CLK is at the high level, the output levels of the output terminals OUT3 (Q) and OUT4 (Qb) do not change even if the levels of the input signals D and Db change. Thus, as in the case of the first embodiment,
A D flip-flop can be constructed by cascade-connecting two circuits of the second embodiment.

FIG. 12 shows two circuits 20d and 20e of the present invention.
FIG. 6 is a circuit diagram in the case where a D flip-flop is configured by connecting them in cascade.

D and Db are data inputs of a D flip-flop, Q39 and Q40 are N-channel type MOS transistors, Q37 and Q38 are P-channel type MOS transistors, 3i and 3j are P-channel type MOS transistors. (Only one transistor is shown here) 3g, 3h are MOS transistor groups composed of N-channel MOS transistors, and Q69 and Q70 are P-channel MOS transistors.
Transistors, Q67 and Q68 are N-channel type MOS
Transistors, OUT1 to OUT4 (Qb) are output terminals, and CLK is a clock signal for controlling the operating state.
OUT3 (Q) and OUT4 (Qb) are output terminals of the D flip-flop. The output terminal OUT1 of the circuit 20d,
The output signal appearing at OUT2 becomes the input signal of the circuit 20e. In this way, the D flip-flop can be configured as in the case of FIG. However, the inverted signal of the clock signal CLK is not necessary.

FIGS. 13 and 14 are block diagrams of a pipeline circuit constructed by connecting a plurality of circuits of the present invention in cascade. Reference numerals 20b and 20c are circuits of the present invention when N channel type MOS transistors are used for the MOS transistor group, and 28a and 28b are circuits of the present invention when P channel type MOS transistors are used for the MOS transistor group. The operation is similar to that of the D flip-flop described with reference to FIGS.

[0048]

As described above, according to the present invention,
Since each input signal is input to only one MOS transistor group, it is necessary to drive only about 1/2 the input capacitance as compared with the conventional example, and high speed and low power consumption can be achieved. Further, when the MOS transistor group is composed of N-channel type MOS transistors, when the output level changes to the High level, it is not performed by a plurality of P-channel type MOS transistors connected in series and parallel as in the conventional example. Since each P-channel MOS transistor is used, the circuit operation can be speeded up. Further, the inverted signal is not required as the clock signal for controlling the operating state.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a timing chart showing an operation of the first embodiment shown in FIG.

FIG. 3 is a circuit configuration diagram of a modified example of the first embodiment.

FIG. 4 is a circuit configuration diagram of a D flip-flop obtained by cascade-connecting two of the first embodiments shown in FIG.

5 is a circuit configuration diagram of a D flip-flop obtained by combining the first embodiment shown in FIG. 2 and its modification shown in FIG.

6 is a circuit configuration diagram of a pipeline configuration obtained by cascading the D flip-flops shown in FIG.

7 is a circuit configuration diagram of a pipeline configuration obtained by cascading the D flip-flops shown in FIG.

FIG. 8 is a circuit configuration diagram of a second embodiment of a semiconductor integrated circuit according to the present invention.

9 is a timing chart showing an operation of the second embodiment shown in FIG.

10 is a circuit configuration diagram of a modified example of the second embodiment shown in FIG.

11 is a circuit configuration diagram of a D flip-flop obtained by cascading two of the second embodiments shown in FIG.

FIG. 12 is a circuit configuration diagram of a D flip-flop obtained by combining the second embodiment shown in FIG. 8 and its modification shown in FIG.

13 is a circuit configuration diagram of a pipeline configuration obtained by cascading the D flip-flops shown in FIG.

14 is a circuit configuration diagram of a pipeline configuration obtained by cascading the D flip-flops shown in FIG.

FIG. 15 is a circuit configuration diagram of an example of a conventional semiconductor integrated circuit.

FIG. 16 is a circuit configuration diagram of another example of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 Q1 1st transistor 1a, 1b Logic circuit part 2, 2a Load circuit 10, 10a, 10b, 10c, 10d Unit integrated circuit OUT1, OUT2, OUT3, OUT4 Output terminal CLK Clock signal CLKb Inverted clock signal

Claims (13)

[Claims] 1. A pair of complementary transistor groups arranged in parallel between a first reference potential point and a second reference potential point, each transistor pair comprising a MOS transistor group. , A pair of MOS transistor groups which are turned on / off according to a predetermined logic when a pair of complementary input signal groups corresponding to the respective transistor pairs are received by the gates of the respective constituent transistors, and the first and second pairs. A pair of parallel MOS transistor groups between the reference potential points and one or two first switching transistors connected in series with each of these transistor group pairs and turned on / off by one kind of clock signal; , Each of which is arranged between the first and second reference potential points, and which is provided to each transistor pair of the pair of parallel MOS transistor groups. A pair of seconds connected in series to each other
Switching transistors of the second switching transistors, the pair of electrode terminals on the side of the pair of MOS transistor groups serving as the output terminals of the device, and the gates of the second switching transistors respectively. A complementary MOS transistor group on the opposite side of the pair of MOS transistor groups is directly or directly connected through the one or two switching transistors, and is further connected to the output side terminal of these switching transistors. A semiconductor integrated circuit comprising: a pair of second switching transistors each having an electrode terminal connected to one of the first and second reference potential points. 2. The first switching transistor is 1
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is arranged between the pair of parallel-connected MOS transistor groups and the second reference potential point. 3. The first switching transistor is 2
And a plurality of MOS transistors connected in parallel to each other and arranged between the output terminal of the device and the pair of MOS transistors connected in parallel.
The semiconductor integrated circuit according to 1. 4. The first switching transistor is a MOS transistor connected in parallel with the first reference potential point.
Is disposed between the transistor group and the pair of second
The semiconductor integrated circuit according to claim 1, wherein the switching transistor is arranged between the pair of parallel-connected MOS transistor groups and the first reference potential point. 5. The pair of first switching transistors and the pair of second switching transistors are arranged in this order between the pair of parallel-connected MOS transistor groups and the first reference potential point. The semiconductor integrated circuit according to claim 1. 6. A D flip-flop configured by cascade-connecting two sets of the semiconductor integrated circuits according to claim 2. 7. A D flip-flop configured by cascade-connecting the semiconductor integrated circuit according to claim 2 and the semiconductor integrated circuit according to claim 4. 8. A pipeline circuit in which the D flip-flop according to claim 6 is used as a unit integrated circuit and the unit integrated circuits are cascade-connected. 9. A pipeline circuit in which the flip-flop according to claim 7 is used as a unit integrated circuit, and the unit integrated circuits are cascade-connected. 10. The semiconductor integrated circuit according to claim 3,
A D flip-flop configured by connecting in series. 11. A D flip-flop configured by cascade-connecting the semiconductor integrated circuit according to claim 3 and the semiconductor integrated circuit according to claim 5. 12. A pipeline circuit in which the flip-flops according to claim 10 are used as a unit integrated circuit and the unit integrated circuits are cascade-connected. 13. A pipeline circuit in which the flip-flop according to claim 11 is used as a unit integrated circuit, and the unit integrated circuits are cascade-connected.