JPH09232931A - Differential switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential switching circuit capable of reducing the noise of a current switch, the area of a control part and also power consumption. SOLUTION: This circuit has a constant current source circuit 1 provided with a PMOS P1 for which a fixed voltage V is supplied to the gate, a current switch 2 composed of a pair of PMOS P2 and P3, and a switch control part 3 for controlling an output resistor R1 and the PMOS P2 and P3. The control part 3 is provided with a PMOS P4, NMOS N1 with which a CMOS inverter function is provided by supplying the signal of DI terminal to the gate and connecting it between a VDD and a GND, a PMOS P5, a similar PMOS P6, an NMOS N2, and a PMOS P7 for providing a delay circuit function while being connected between these PMOS P4 and NMOS N1, and the PMOS P2 and P3 are prevented from being simultaneously turned off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential switching circuit, and more particularly to a differential switching circuit used in a current output type D / A converter or the like.

[0002]

2. Description of the Related Art A conventional differential switching circuit of this type is
For example, it is used by being incorporated in a current source cell of a D / A converter.

FIG. 5 is a differential switching circuit diagram showing a conventional example. As shown in FIG. 5, this differential switching circuit includes a constant current P-channel MOS transistor P1, a constant current source circuit 1 whose gate is supplied with a bias voltage V, and a constant current source circuit 1 connected to this constant current source circuit 1. A pair of P
Channel MOS transistor (hereinafter referred to as PMOS)
It has a current switch 2 composed of P2 and P3, and an output resistor R1. The gates of these PMOS P2 and P3 are directly controlled from the input terminal DI through the inverter I1 and directly controlled to output high and low voltages from the output terminal DO. Is a structure for taking out. Note that points A to D represent each node.

The PMOSP forming the current switch 2
2 and P3 control the voltage of the output terminal DO by supplying complementary digital signals and turning them on / off. Therefore, a circuit in which a current flows through either PMOS P2 or P3 is configured.

This differential switching circuit is provided corresponding to each current cell. As a D / A converter, a desired analog output can be obtained by controlling each of a plurality of constant current sources arranged. Can be controlled.

FIG. 6 shows a node B of the current switch shown in FIG.
FIG. 6 is a timing diagram illustrating a voltage change in the circuit. FIG.
As shown in (3), when the PMOS P2 and P3 of the current switch 2 are switched, there is a timing at which both transistors tend to be off. That is, when an input signal is supplied from the input terminal DI, the voltages at the nodes C and D change like VC and VD, respectively, but near the time 4 ns, the voltage VB at the node B changes to another switching time (0
ns, 8 ns) may be about 0.8V higher than the VB voltage. This is the timing when both the PMOS P2 and P3 are turned off, and this voltage change is superimposed on the constant bias voltage VA of the node A as noise via the parasitic capacitance of the PMOS P1.

When noise is superimposed on the constant bias voltage VA, it affects all of the plurality of constant current source transistors to which the bias voltage is applied, and D
Noise is also output to the / A conversion output. Such a situation occurs due to the system in which the control of the current switch 2 is performed in the order of the PMOS P3 and the PMOS P2 by the delay time of the inverter I1, that is, the switching sequence fixed system.

FIG. 7 is a differential switching circuit diagram showing another conventional example. As shown in FIG. 7, this differential switching circuit is an improvement of the circuit of FIG. 5 in order to reduce the above-mentioned output noise.
It is disclosed in the digital / analog converter of Japanese Patent No. 8288. This circuit is provided with a switch control unit 3a in addition to the constant current source circuit 1 and the current switch 2 described above, and the configuration thereof is PMOS P5 and P7 and NMOSN.
1 and N2.

The switch controller 3a is provided as follows.
Inverter I1 for forming the inverted signal in the circuit of FIG.
In order to eliminate the noise generated by the operation time lag of the PMOSP3 and PMOSP2 due to the gate delay, the time lag of the normal signal (DI) and the inverted signal (DI inversion) is eliminated. To do so. By eliminating such a time lag, the switching time becomes short and noise can be reduced.

FIGS. 8A and 8B are a timing diagram and a voltage characteristic diagram of the node A for explaining the voltage change at the node B of the current switch shown in FIG. 7, respectively. FIG.
As shown in FIG. 7A, in the differential switching circuit of FIG. 7, both the PMOS P3 and P2 of the current switch 2 are not completely turned off, but the voltage VB of the node B is the maximum due to the off state. About 0.6V can be lifted. Therefore, as shown in FIG. 8B, the voltage VA of the node A is raised by about 0.36 mV. This change in voltage is due to the fact that it is difficult to control the rising delay for both of the transistors P5 and P7 in controlling the operation of the PMOS P5 and P7 in the switch control unit 3a in FIG.

[0011]

The above-mentioned conventional differential switching circuit, particularly the former differential switching circuit shown in FIG. 5, has a drawback that noise is generated when the switching transistors are switched.

In the latter differential switching circuit shown in FIG. 7, the transistor (P
By controlling the timing so that both P2 and P3 are not turned off, noise can be reduced to some extent. However, in order to improve the switching timing of both transistors, the size balance between the NMOS and the PMOS must be NMOS-dominant. Therefore, there is a drawback that the area of the switch control section becomes large, which in turn increases the power consumption.

It is an object of the present invention to provide a differential switching circuit capable of reducing the noise injection into the constant current source, reducing the area of the switch control section and reducing the power consumption.

[0014]

A differential switching circuit of the present invention is a constant current MOS whose gate is supplied with a constant voltage.
A constant current source circuit including a transistor, a pair of MOS transistors, a current switch connected to the constant current source circuit, an output resistor connected to an output terminal, and an input terminal connected to the current switch. The pair of MOS
In a differential switching circuit including a switch control unit for controlling a transistor, the switch control unit supplies a signal from the input terminal to each gate, and a first PMOS transistor connected between a power supply and GND. And a first NMOS transistor, a second PMOS transistor connected between the first PMOS transistor and the first NMOS transistor, and a signal from the input terminal supplied to a gate via an inverter, respectively. The third connected between the power supply and the GND
And a second NMOS transistor, and a fourth PMOS connected between the third PMOS transistor and the second NMOS transistor.
A transistor, connecting a connection point of the second PMOS transistor and the first NMOS transistor to respective gates of the fourth PMOS transistor and one MOS transistor of the current switch, and PMOS transistor and the second
The connection point of the NMOS transistor of the second PMOS
It is configured by connecting to the gates of the transistor and the other MOS transistor of the current switch.

Further, the differential switching circuit of the present invention is
The connection positions of the first and second PMOS transistors connected between the power supply and the GND may be exchanged and the connection positions of the third and fourth PMOS transistors may be exchanged.

Further, the differential switching circuit of the present invention comprises a constant current source circuit having a constant current MOS transistor whose gate is supplied with a constant voltage, and a pair of MOS transistors, and is connected to the constant current source circuit. A differential switching circuit comprising: a current switch, an output resistance connected to an output terminal, and a switch controller connected to an input terminal for controlling the pair of MOS transistors of the current switch, The control unit supplies signals from the input terminals to the gates thereof, respectively, and a first PMOS transistor and a first NMOS transistor connected between a power supply and GND, and the first PMOS transistor.
A second NMOS transistor connected between the transistor and the first NMOS transistor, and a second PMO connected between the power supply and the GND by supplying a signal from the input terminal to the gate through an inverter.
An S transistor and a third NMOS transistor,
The second PMOS transistor and the third NM
A fourth NMOS transistor connected between the OS transistors, and connecting points of the first PMOS transistor and the second NMOS transistor to the fourth NMOS transistor and one MOS transistor of the current switch, respectively. Connected to the gate of the second PMOS transistor and the fourth NMO
The connection point of the S transistor is connected to the respective gates of the second NMOS transistor and the other MOS transistor of the current switch.

Further, in the differential switching circuit of the present invention, the connection positions of the first and second NMOS transistors connected between the power supply and the GND are exchanged, and the third and fourth NMOS transistors are switched. It is also possible to replace the connection positions.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a differential switching circuit diagram showing one embodiment of the present invention. As shown in FIG. 1, the differential switching circuit of the present embodiment is applied to a current source cell of a current cell matrix type D / A converter, and its configuration has a constant voltage V
Constant current source circuit 1 having a constant current PMOSP1 supplied with a current, a current switch 2 including a pair of PMOSP2 and P3, an output resistor R1 and a PMOSP of the current switch 2.
2, and a switch control unit 3 for controlling P3.

Constant current PMOS P1 in the present embodiment
Is a constant current source that constantly supplies a predetermined current by connecting the source to the power supply VDD, the drain to the sources of the current switches PMOSP2 and P3, and the gate to the bias terminal V. The PMOSs P2 and P3 forming the current switch 2 are turned on / off by a control signal applied to their gates, and the constant current source PMO is supplied.
Supply current from SP1 to output terminal DO, GND
To flush.

Further, the switch control section 3 has an input terminal D
The signal from I is supplied to each gate and the power source VD
PMOSP4 and NMOSN1 which are connected between D and GND and perform a CMOS inverter function, and these PMOSs
A PMOS P5 connected between P4 and NMOS N1 and serving as a delay circuit, and similarly a signal from an input terminal DI is supplied to the gate via an inverter I1 and connected between a power supply VDD and GND to perform a CMOS inverter function. It has PMOSP6 and NMOSN2, and PMOSP7 connected between these PMOSP6 and NMOSN2 and performing a delay circuit function.

That is, the switch control section 3 has an input terminal DI and an inverter I1 for inverting the input signal, and the input terminal DI is connected to the gate of the PMOS P4 and the NMO.
Connect to the gate of SN1. The output of the inverter I1 is connected to the gate of the PMOS P6 and the gate of the NMOS N2, the source of the PMOS P5 is connected to the drain of the PMOS P4, and the drain of the PMOS P5 is connected to the drain of the NMOS N1. Similarly, the source of the PMOS P7 is connected to the drain of the PMOS P6, and the drain of the PMOS P7 is connected to the drain of the NMOS N2. Moreover, of the pair of PMOS P2 and P3 of the current switch 2,
The gate of P2 is connected to the drain of N1 and the gate of P7, and the gate of P3 is connected to the drain of N2 and the gate of P5.

In the differential switching circuit having such a configuration, when a signal from the input terminal DI is input, the PMOSP2,
The voltages VC and VD of the nodes C and D that are the gates of P3 are
NMOSN1 and NMOSN2 respond immediately and PM
OSP4 and PMOSP6 also try to respond immediately. However, the PMOSP4 and P6 are responsive to the voltages VC and VD of the nodes C and D, and the PMOSP5 and PMO are responsive.
Since the SP7 is connected, the output nodes C and D of the switch control section 3 are
High "level responses do not arrive immediately. Therefore,
The output nodes C and D are relatively low immediately, but in order to become high, it is difficult to become high unless the other is low. In short, unless the other is always low, the PMOSs P5 and P7 as delay elements do not turn on, so that it is difficult to make them high, so that both the PMOSs P2 and P3 as current switches are not turned off at the same time. This is because. In addition, PMOSP4, P6
Also functions as a resistor and delays the rising timing of the voltage at the nodes C and D.

In order to make such a switching timing with a slow rise and a fast fall, the PMOS P4 to P7 and the NMOSs N1 and N2 of the switch controller 3 are provided.
As for the size ratio of the PMOS and the NMOS, the size of the NMOS has to be made larger to some extent than the PMOS. However, according to the present embodiment, since the PMOSes are vertically stacked, each inverter has a general inverter size. It can be realized as it is.

2 (a) and 2 (b) are a timing diagram and a voltage characteristic diagram of node A for explaining the voltage change at node B of the current switch shown in FIG. 1, respectively. FIG.
As shown in (a) and (b), the voltage characteristics of this voltage switch correspond to the characteristics of the conventional example shown in FIGS. 8 (a) and 8 (b). Since the falling characteristics of the control voltages VC and VD applied to the gates of the PMOSs P2 and P3 forming the switch 2 can be made agile, that is, the operation speed of the PMOS can be slowed down, so that the voltage VB at the node B can be made more stable. And consequently the PMOSP that constitutes the constant current source circuit 1
It is possible to significantly reduce the influence of noise on the bias voltage VA supplied to the 1 gate.

FIG. 3 is a differential switching circuit diagram showing another embodiment of the present invention. As shown in FIG. 3, the differential switching circuit according to the present embodiment is the same as that shown in FIG.
The PMOS forming each circuit of
The S is replaced by a PMOS.

That is, in such a differential switching circuit, the drain of the NMOS N3 forming the constant current source circuit 1 has the drains of the NMOS N4 and N5 forming the current switch 2.
, The source of the NMOS N3 is connected to the GND, and the gate is supplied with the bias voltage V, whereby the NMOS N3 serves as a constant current source. The NMOSs N4 and N5 of the current switch 2 are turned on and off by the signals applied to their gates, respectively, to supply or stop the current of the constant current source NMOSN3 to the output terminal DO.

Moreover, when the signal from the input terminal DI is supplied, the PMOSs P8 and P9 of the switch controller 3 immediately respond, so that the potentials VC and VD of the nodes C and D, which are the gates of the NMOSs N4 and N5, are high ( VDD).
However, in order for the potential VC or VD to go low,
The other needs to be high. That is, unless the other is high, the NMOSs N6 and N8 do not turn on, so that it is difficult for the NMOSN6 and N8 to go low.
We are trying not to turn off both 4 and N5 (at the same time). Further, the NMOS N7 in the switch control unit 3,
Since N9 also plays the role of a resistor, it is possible to delay the falling timing of the potentials VC and VD of the nodes C and D.

Using the switching circuit described above, N
The same effect can be obtained by a current cell matrix type D / A converter in which a constant current cell is formed by MOS.

In the circuit of FIG. 3, the NMOSN6 and N7 and the NMOSN which form the switch control section 3 are included.
Even if the positions of 8 and N9 are interchanged, the same function can be achieved.

FIG. 4 is a differential switching circuit diagram showing another embodiment of the present invention. As shown in FIG. 4, the differential switching circuit according to the present embodiment includes the PMOS P4 and the PMOS P4 in the switch control unit 3 of FIG.
5 and the connection positions of PMOS P6 and P7 are exchanged. That is, the PMOSP5,
This is a circuit in which P7 is connected and PMOSs P4 and P6 are connected to the nodes C and D sides. In addition, other constant current source circuits 1,
Since the current switch 2 and the output resistance R1 do not need to be changed, the description thereof will be omitted.

[0031]

As described above, the differential switching circuit of the present invention includes a constant current source circuit and a pair of PMOSs for supplying the current from the constant current source circuit to the output terminal or GND.
Alternatively, a current changeover switch composed of an NMOS and a switch control section for controlling the current changeover switch are provided, and further, a PMOS or an NMOS which operates with an input forward rotation signal and an input inversion signal is vertically connected to the switch control section. The pair of PMOS or NMO
Since it is possible to prevent simultaneous switching off of the switching timing of S, the size ratio of P to N of the inverter can be made equal, noise can be reduced, and the area of the switch control unit can be reduced and power consumption can be reduced. There is. Further, according to the present invention, the circuit design can be facilitated,
Even when used in a current cell type D / A converter, there is an effect that a stable converter can be obtained with less noise.

[Brief description of drawings]

FIG. 1 is a differential switching circuit diagram showing an embodiment of the present invention.

FIG. 2 is a voltage characteristic diagram at each node of the current switch shown in FIG.

FIG. 3 is a differential switching circuit diagram showing another embodiment of the present invention.

FIG. 4 is a differential switching circuit diagram showing still another embodiment of the present invention.

FIG. 5 is a differential switching circuit diagram showing a conventional example.

6 is a voltage characteristic diagram at each node of the current switch shown in FIG.

FIG. 7 is a differential switching circuit diagram showing another conventional example.

8 is a voltage characteristic diagram at each node of the current switch shown in FIG. 7.

[Explanation of symbols]

 1 Constant Current Source Circuit 2 Current Switch 3 Switch Control Unit I1 Inverter P1 to P9 P Channel MOS Transistor N1 to N9 N Channel MOS Transistor DI Input Terminal DO Output Terminal V Bias Voltage Terminal

Claims (4)

[Claims] 1. A constant current M whose gate is supplied with a constant voltage.
A constant current source circuit having an OS transistor and a pair of MOs
A current switch composed of an S transistor and connected to the constant current source circuit; and an output resistance connected to an output terminal,
The pair of M of the current switches are connected to the input terminals.
In a differential switching circuit including a switch control unit for controlling an OS transistor, the switch control unit supplies signals from the input terminals to respective gates, and a first PMOS connected between a power supply and GND. A transistor and a first NMOS transistor, and the first
A second PMOS transistor connected between the first PMOS transistor and the first NMOS transistor;
A signal from the input terminal is supplied to the gates via an inverter, and a third PMOS transistor and a second NMOS transistor connected between the power supply and the GND, a third PMOS transistor and the second PMOS transistor are connected. Fourth PMO connected between NMOS transistors
An S-transistor, connecting a connection point of the second PMOS transistor and the first NMOS transistor to respective gates of the fourth PMOS transistor and one MOS transistor of the current switch, and Of the PMOS transistor and the second NMOS transistor are connected to the second PMO.
S transistor and the other MOS of the current switch
A differential switching circuit characterized by being connected to each gate of a transistor. 2. The connection positions of the first and second PMOS transistors connected between the power supply and the GND are exchanged, and the third and fourth PMOS transistors are exchanged.
The differential switching circuit according to claim 1, wherein the connection positions of the transistors are exchanged. 3. A constant current M whose gate is supplied with a constant voltage.
A constant current source circuit having an OS transistor and a pair of MOs
A current switch composed of an S transistor and connected to the constant current source circuit; and an output resistance connected to an output terminal,
The pair of M of the current switches are connected to the input terminals.
In a differential switching circuit including a switch control unit for controlling an OS transistor, the switch control unit supplies signals from the input terminals to respective gates, and a first PMOS connected between a power supply and GND. A transistor and a first NMOS transistor, and the first
A second NMOS transistor connected between the PMOS transistor and the first NMOS transistor of
A second PMOS transistor and a third NMOS transistor connected to the power supply and the GND by supplying a signal from the input terminal to the gate through an inverter, respectively, and the second PMOS transistor and the third PMOS transistor. Fourth NMO connected between NMOS transistors
An S-transistor, connecting a connection point of the first PMOS transistor and the second NMOS transistor to respective gates of the fourth NMOS transistor and one MOS transistor of the current switch, and Of the PMOS transistor and the fourth NMOS transistor are connected to the second NMO.
S transistor and the other MOS of the current switch
A differential switching circuit characterized by being connected to each gate of a transistor. 4. The connection positions of the first and second NMOS transistors connected between the power supply and the GND are exchanged, and the third and fourth NMOS transistors are exchanged.
The differential switching circuit according to claim 3, wherein the connection positions of the transistors are exchanged.