JPH10290154A - Output circuit - Google Patents

Output circuit

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Publication number
JPH10290154A
JPH10290154A JP9095724A JP9572497A JPH10290154A JP H10290154 A JPH10290154 A JP H10290154A JP 9095724 A JP9095724 A JP 9095724A JP 9572497 A JP9572497 A JP 9572497A JP H10290154 A JPH10290154 A JP H10290154A
Authority
JP
Japan
Prior art keywords
pmos
nmos
output load
circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9095724A
Other languages
Japanese (ja)
Other versions
JP3516569B2 (en
Inventor
Harumi Kono
治美 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Oki Micro Design Miyazaki Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Oki Micro Design Miyazaki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd, Oki Micro Design Miyazaki Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP09572497A priority Critical patent/JP3516569B2/en
Publication of JPH10290154A publication Critical patent/JPH10290154A/en
Application granted granted Critical
Publication of JP3516569B2 publication Critical patent/JP3516569B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To prevent delay time from being extremely extended when an output load is increased by providing the control signal of control circuit from 3rd and 4th transistors connecting their respective control electrodes with the control electrodes of 1st and 2nd transistors while being parallelly connected with the serially connected 1st and 2nd transistors for driving the output load. SOLUTION: A circuit A is provided while being composed of PMOS 105 and NMOS 106, which are operated similarly to PMOS 107 and NMOS 108 for driving the output load, and an output SOUT of circuit A is connected to a control circuit B. The ON/OFF of PMOS 102 and NMOS 103 inside the control circuit B is performed by SOUT. Thus, a transient current to pass through PMOS 107 and NMOS 108 for driving the output load in case of change from ON to OFF can be suppressed and controlled in spite of the output load even when the output load is increased so that acceleration in the case of output load increase can be attained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、出力負荷を駆動する出
力回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit for driving an output load.

【０００２】[0002]

【従来の技術】従来、出力回路において、出力負荷を駆
動する際に発生するスイッチングノイズを抑制するもの
としては、図３（従来回路Ａ）、図５（従来回路Ｂ）に
示すような回路があった。2. Description of the Related Art Conventionally, in an output circuit, a circuit as shown in FIG. 3 (conventional circuit A) and FIG. 5 (conventional circuit B) has been known as a device for suppressing switching noise generated when driving an output load. there were.

【０００３】従来回路Ａの動作を図４のタイミング図を
用いて説明すると、出力OUTがLからHへ動作する場合、S
502のH→Lへの動作において、まずS501=Hの時、NMOS503
=OFF、PMOS504=ONであり、この状態からS502のH→Lへと
動作を開始する。The operation of the conventional circuit A will be described with reference to the timing chart of FIG. 4. When the output OUT operates from L to H, S
In the operation of 502 from H to L, when S501 = H, NMOS 503
= OFF and PMOS 504 = ON, and the operation starts from H → L in S502 from this state.

【０００４】しかしながら、NMOS503=OFFのためS501は
瞬時にLレベルとはならず出力OUTがHレベルへ近づくに
つれNMOS503=ONとなるため、S501はLレベルとなる。S50
1を瞬時にH→LにしないことでPMOS505を通る電源から出
力負荷への充電時の過渡電流を抑制することで、スイッ
チングノイズを抑制している。出力OUTのH→L動作は、P
MOS504の効果によりS502が瞬時にL→Hとならないため、
NMOS506を通る出力負荷からグランドへの放電時の過渡
電流を抑制することで、スイッチングノイズを抑制して
いる。However, since NMOS 503 is OFF, S501 does not immediately go to the L level, and NMOS 503 becomes ON as the output OUT approaches the H level, so that S501 goes to the L level. S50
Switching noise is suppressed by suppressing the transient current at the time of charging from the power supply through the PMOS 505 to the output load by not instantaneously changing 1 from H to L. H → L operation of output OUT is P
Because S502 does not go from L to H instantly due to the effect of MOS504,
Switching noise is suppressed by suppressing the transient current when discharging from the output load passing through the NMOS 506 to the ground.

【０００５】次に、従来回路Ｂの回路は出力OUTとつな
がるPMOS及びNMOSを各々PMOS601、607とNMOS602、608に
分割している。この回路の動作を図６のタイミング図を
用いて説明すると、まず出力OUTがL→Hへ動作する場
合、PMOS601はON状態となり、PMOS607はNMOS603の効果
（OUT=HとなればS605=Lとなる）により瞬時にはON状態
とならないため、PMOS601、PMOS607を通る電源から出力
負荷への充電時の過渡電流は抑制され、スイッチングノ
イズを抑制できる。次に出力OUTがH→Lへ動作する場
合、NMOS602はON状態となり、NMOS608はPMOS604の効果
（OUT=LとなればS604=Hとなる）により瞬時にはON状態
とならないため、NMOS602、NMOS608を通る出力負荷から
グランドへの放電時の過渡電流は抑制され、スイッチン
グノイズを抑制できる。Next, in the circuit of the conventional circuit B, the PMOS and the NMOS connected to the output OUT are divided into PMOS 601 and 607 and NMOS 602 and 608, respectively. The operation of this circuit will be described with reference to the timing chart of FIG. 6. First, when the output OUT operates from L to H, the PMOS 601 is turned on, and the PMOS 607 has the effect of the NMOS 603 (if OUT = H, S605 = L Therefore, a transient current during charging from the power supply passing through the PMOS 601 and the PMOS 607 to the output load is suppressed, and switching noise can be suppressed. Next, when the output OUT operates from H → L, the NMOS 602 is turned on, and the NMOS 608 is not instantly turned on by the effect of the PMOS 604 (S604 = H when OUT = L). The transient current at the time of discharging from the output load to the ground to the ground is suppressed, and switching noise can be suppressed.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、従来回
路Ａにおいては図４のタイミング図中の(c)、(g)のよう
に出力OUTを、制御回路の制御信号として使っているた
め出力負荷が増大した場合、図７に示すグラフのように
遅延時間が極端に大きくなるという問題があった。However, in the conventional circuit A, the output OUT is used as the control signal of the control circuit as shown in (c) and (g) in the timing chart of FIG. When it increases, there is a problem that the delay time becomes extremely long as shown in the graph of FIG.

【０００７】従来回路Ｂにおいても図６のタイミング図
中の(k)、(o)のように出力OUTを、制御回路の制御信号と
して使っているため出力負荷が増大した場合、図７に示
すグラフのように遅延時間が極端に大きくなるという問
題があった。The conventional circuit B also uses the output OUT as the control signal of the control circuit as shown in (k) and (o) in the timing chart of FIG. There is a problem that the delay time becomes extremely large as shown in the graph.

【０００８】[0008]

【課題を解決するための手段】本発明は、上述した問題
点を解決するためになされた半導体集積回路であり、そ
の代表的なものは、出力端子を介して電源電位と接地電
位との間に直列に接続された第１及び第２のトランジス
タを有する出力回路において、前記電源電位と接地電位
との間に直列に接続され、各々の制御電極が各々前記第
１及び第２のトランジスタの制御電極に接続された第３
及び第４のトランジスタとを有することを特徴とする出
力回路である。SUMMARY OF THE INVENTION The present invention is directed to a semiconductor integrated circuit for solving the above-mentioned problems. A typical example of the semiconductor integrated circuit is a circuit between an electric power supply potential and a ground potential via an output terminal. An output circuit having first and second transistors connected in series to the power supply potential and the ground potential, each control electrode being connected to the control of the first and second transistors, respectively. Third connected to the electrode
And a fourth transistor.

【０００９】[0009]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

（第１の実施の形態） （構成）の説明 第１の実施の形態を図１を用いて説明すると、出力負荷
を駆動するPMOS107とNMOS108と同じように動作するPMOS
105とNMOS106（回路A）を設けている。そして、その出
力SOUTを制御回路Bへ接続している。(First Embodiment) (Description of Configuration) A first embodiment will be described with reference to FIG. 1. A PMOS 107 and an NMOS 108 which operate in the same manner as a PMOS 107 and an NMOS 108 which drive an output load.
105 and an NMOS 106 (circuit A) are provided. Then, the output SOUT is connected to the control circuit B.

【００１０】（動作）の説明 第１の実施例の動作を図２のタイミング図をもちいて説
明すると、制御回路B内のPMOS102、NMOS103のON/OFFはS
OUTによって行われる。図２のタイミング図中(c)、(g)を
参照。Description of (Operation) The operation of the first embodiment will be described with reference to the timing chart of FIG. 2. The ON / OFF of the PMOS 102 and the NMOS 103 in the control circuit B is S
Done by OUT. See (c) and (g) in the timing chart of FIG.

【００１１】（効果）の説明 以上説明したように、本発明の第１の実施の形態によれ
ば、制御回路Bの制御信号（SOUT）を出力負荷を駆動す
るトランジスタと同じように動作するPMOS105、NMOS106
より得たため、OFFからON状態に変化（出力負荷を駆
動）するトランジスタを通る過渡電流を抑制できるため
スイッチングノイズを抑制できるようになり、また出力
負荷が増大しても出力負荷と無関係に制御されるため、
図７に示すように遅延時間の容量依存は直線近似できる
ようになり、出力負荷の増えた場合の高速化がはかれ
る。Description of (Effect) As described above, according to the first embodiment of the present invention, the control signal (SOUT) of the control circuit B is controlled by the PMOS 105 operating in the same manner as the transistor driving the output load. , NMOS106
As a result, the switching current can be suppressed because the transient current passing through the transistor that changes from OFF to ON (drives the output load) can be suppressed, and even if the output load increases, it is controlled independently of the output load. Because
As shown in FIG. 7, the capacity dependence of the delay time can be approximated by a straight line, and the speed can be increased when the output load increases.

【００１２】（第２の実施の形態） （構成）の説明 本提案の第２の実施の形態を図８を用いて説明すると、
第２の実施の形態は第１の実施の形態の回路Aにこの回
路を設けたものとする。PMOS105とNMOS106の間に、常時
ON状態のPMOS81、NMOS82を直列に設けその接続点をSOUT
としている。Second Embodiment Description of (Structure) A second embodiment of the present invention will be described with reference to FIG.
In the second embodiment, this circuit is provided in the circuit A of the first embodiment. Always between PMOS 105 and NMOS 106
PMOS81 and NMOS82 in the ON state are connected in series and the connection point is connected to SOUT
And

【００１３】（動作）の説明 第２の実施の形態の動作を説明すると、基本的な動作は
図２のタイミング図と同じであるが、常時ON状態のPMOS
81とNMOS82の効果によりS101の立ち下がり動作はより緩
やかになり、S104の立ち上がり動作もより緩やかににな
る。Description of (Operation) The operation of the second embodiment will be described. The basic operation is the same as that of the timing chart of FIG.
Due to the effects of 81 and the NMOS 82, the falling operation of S101 becomes more gentle, and the rising operation of S104 becomes more gentle.

【００１４】（効果）の説明 以上述べたように、本発明の第２の実施の形態によれ
ば、制御回路Bの制御信号（SOUT）を出力負荷を駆動す
るトランジスタと同じように動作するPMOS105、NMOS10
6、常時ON状態のPMOS81、NMOS82より得たため、OFFから
ON状態に変化（出力負荷を駆動）するトランジスタを通
る過渡電流を抑制できるためスイッチングノイズを抑制
できるようになり、また出力負荷が増大しても出力負荷
と無関係に制御されるため、図７に示すように遅延時間
の容量依存は直線近似できるようになり、出力負荷の増
えた場合の高速化がはかれる。Description of (Effect) As described above, according to the second embodiment of the present invention, the control signal (SOUT) of the control circuit B is supplied to the PMOS 105 operating in the same manner as the transistor driving the output load. , NMOS10
6.Because it is obtained from PMOS81 and NMOS82 which are always ON, from OFF
Transient current passing through the transistor that changes to the ON state (drives the output load) can be suppressed, so that switching noise can be suppressed. Even if the output load increases, control is performed independently of the output load. As shown, the capacity dependence of the delay time can be approximated by a straight line, and the speed can be increased when the output load increases.

【００１５】（第３の実施の形態） （構成）の説明 本提案の第３の実施の形態を図９図を用いて説明する
と、第３の実施の形態は第１の実施の形態の回路Aにこ
の回路を設けたものとする。PMOS105とNMOS106の間（そ
の接続点をSOUT）に、コンデンサ91を故意に設けてい
る。(Third Embodiment) (Description of Configuration) A third embodiment of the present invention will be described with reference to FIG. 9. The third embodiment is a circuit of the first embodiment. Assume that this circuit is provided in A. A capacitor 91 is intentionally provided between the PMOS 105 and the NMOS 106 (the connection point is SOUT).

【００１６】（動作）の説明 第３の実施の形態の動作を説明すると、基本的な動作は
図２のタイミング図と同じであるが、故意に設けたコン
デンサ91の効果によりS101の立ち下がり動作はより緩や
かになり、S104の立ち上がり動作もより緩やかににな
る。Description of (Operation) The operation of the third embodiment will be described. The basic operation is the same as the timing chart of FIG. 2, but the falling operation of S101 is performed by the effect of the capacitor 91 provided intentionally. Becomes more gradual, and the rising operation of S104 becomes more gradual.

【００１７】（効果）の説明 以上述べたように、本発明の第３の実施の形態によれ
ば、制御回路Bの制御信号（SOUT）を出力負荷を駆動す
るトランジスタと同じように動作するPMOS105、NMOS10
6、故意に設けたコンデンサ91より得たため、OFFからON
状態に変化（出力負荷を駆動）するトランジスタを通る
過渡電流を抑制できるためスイッチングノイズを抑制で
きるようになり、また出力負荷が増大しても出力負荷と
無関係に制御されるため、図７に示すように遅延時間の
容量依存は直線近似できるようになり、出力負荷の増え
た場合の高速化がはかれる。Description of (Effect) As described above, according to the third embodiment of the present invention, the control signal (SOUT) of the control circuit B is controlled by the PMOS 105 operating in the same manner as the transistor driving the output load. , NMOS10
6.Because it was obtained from the capacitor 91 which was provided intentionally, it is turned on from OFF.
Transient current passing through a transistor that changes to a state (drives an output load) can be suppressed, so that switching noise can be suppressed. Further, even if the output load increases, control is performed independently of the output load. As described above, the capacity dependence of the delay time can be approximated by a straight line, and the speed can be increased when the output load increases.

【００１８】（第４の実施の形態） （構成）の説明 本提案の第４の実施の形態を図１０を用いて説明する
と、第４の実施の形態は第１の実施の形態の回路Aにこ
の回路を設けたものとする。PMOS105とNMOS106の間に、
常時ON状態のPMOS81、NMOS82を直列に設けその接続点を
SOUTとし、コンデンサ９１を故意に設けている。(Fourth Embodiment) Description of (Configuration) A fourth embodiment of the present proposal will be described with reference to FIG. 10. The fourth embodiment is a circuit A according to the first embodiment. It is assumed that this circuit is provided. Between PMOS 105 and NMOS 106,
PMOS81 and NMOS82 which are always ON are connected in series and the connection point is
SOUT, and a capacitor 91 is provided intentionally.

【００１９】（動作）の説明 第４の実施の形態の動作を説明すると、基本的な動作は
図２のタイミング図と同じであるが、常時ON状態のPMOS
81とNMOS82と故意に設けたコンデンサ91の効果によりS1
01の立ち下がり動作はより緩やかになり、S104の立ち上
がり動作もより緩やかにになる。Description of (Operation) The operation of the fourth embodiment will be described. The basic operation is the same as the timing chart of FIG.
S1 due to the effect of 81, NMOS 82 and capacitor 91 provided intentionally
The falling operation of 01 becomes gentler, and the rising operation of S104 becomes more gentle.

【００２０】（効果）の説明 以上述べたように、本発明の第４の実施の形態によれ
ば、制御回路Bの制御信号（SOUT）を出力負荷を駆動す
るトランジスタと同じように動作するPMOS105、NMOS10
6、常時ON状態のPMOS81、NMOS82と故意に設けたコンデ
ンサ91より得たため、OFFからON状態に変化（出力負荷
を駆動）するトランジスタを通る過渡電流を抑制できる
ためスイッチングノイズを抑制できるようになり、また
出力負荷が増大しても出力負荷と無関係に制御されるた
め、図７に示すように遅延時間の容量依存は直線近似で
きるようになり、出力負荷の増えた場合の高速化がはか
れる。Description of (Effect) As described above, according to the fourth embodiment of the present invention, the control signal (SOUT) of the control circuit B is controlled by the PMOS 105 operating in the same manner as the transistor driving the output load. , NMOS10
6. Transient current passing through the transistor that changes from OFF to ON (drives the output load) can be suppressed because it is obtained from the PMOS 81 and NMOS 82 that are always in the ON state and the capacitor 91 that is intentionally provided, so that switching noise can be suppressed. Further, even if the output load increases, the delay time is controlled independently of the output load. Therefore, as shown in FIG. 7, the capacity dependence of the delay time can be approximated by a straight line, and the speed when the output load increases can be increased.

【００２１】（第５の実施の形態）の説明 （構成）の説明 本提案の第５の実施の形態を図１１図を用いて説明する
と、第５の実施の形態は第１の実施の形態の回路Aにこ
の回路を設けたものとする。S101とSOUT、S104とSOUTの
間にコンデンサ111、112を各々設けている。Description of (Fifth Embodiment) Description of (Configuration) A fifth embodiment of the present proposal will be described with reference to FIG. 11, and the fifth embodiment will be described with reference to the first embodiment. It is assumed that the circuit A is provided with this circuit. Capacitors 111 and 112 are provided between S101 and SOUT and between S104 and SOUT, respectively.

【００２２】（動作）の説明 第５の実施の形態の動作を説明すると、基本的な動作は
図２のタイミング図と同じであるが、コンデンサ111、1
12の効果によりS101の立ち下がり動作はより緩やかにな
り、S104の立ち上がり動作もより緩やかにになる。S101
の立ち下がり動作を例にすると、S101がH→Lに変化する
と、SOUTはL→Hへ変化しはじめる（S101とSOUTは変化が
逆向き）。そうすると、コンデンサ111の効果（S101とS
OUTの電位差を保持しようとする働き）により、S101の
立ち下がり動作はより緩やかになる。(Description of Operation) The operation of the fifth embodiment will be described. The basic operation is the same as that of the timing chart of FIG.
Due to the effect of 12, the falling operation of S101 becomes more gentle, and the rising operation of S104 becomes more gentle. S101
As an example, when S101 changes from H to L, SOUT starts to change from L to H (changes in S101 and SOUT are reversed). Then the effect of capacitor 111 (S101 and S
The action of maintaining the potential difference of OUT) makes the falling operation of S101 gentler.

【００２３】（効果）の説明 以上述べたように、本発明の第５の実施の形態によれ
ば、制御回路Bの制御信号（SOUT）を出力負荷を駆動す
るトランジスタと同じように動作するPMOS105、NMOS106
より得て、OFFからON状態に変化（出力負荷を駆動）す
るトランジスタのゲート信号（S101,S104）もコンデン
サ111、112によって制御するようにしたためそのトラン
ジスタを通る過渡電流を抑制できるためスイッチングノ
イズを抑制できるようになり、また出力負荷が増大して
も出力負荷と無関係に制御されるため、第７図に示すよ
うに遅延時間の容量依存は直線近似できるようになり、
出力負荷の増えた場合の高速化がはかれる。Description of (Effect) As described above, according to the fifth embodiment of the present invention, the control signal (SOUT) of the control circuit B is controlled by the PMOS 105 operating in the same manner as the transistor driving the output load. , NMOS106
In addition, the gate signals (S101, S104) of the transistor that changes from OFF to ON (drives the output load) are also controlled by the capacitors 111 and 112, so that the transient current passing through the transistor can be suppressed. It is possible to control the delay time independently of the output load even if the output load increases. Therefore, as shown in FIG. 7, the capacity dependence of the delay time can be approximated by a straight line.
The speed can be increased when the output load increases.

【００２４】（第６の実施の形態） （構成）の説明 第６の実施の形態を図１２を用いて説明すると、出力負
荷を駆動するPMOS607とNMOS608と同じように動作するPM
OS605とNMOS606を設け、常時ON状態のトランジスタPMOS
609、NMOS610（回路C）を設けている。そして、PMOS605
とPMOS609の接続点をSOUTPとしNMOS610とNMOS606の接続
点をSOUTNとして制御回路Bへ接続している。(Sixth Embodiment) Description of (Structure) A sixth embodiment will be described with reference to FIG. 12. PM which operates in the same manner as the PMOS 607 and the NMOS 608 for driving the output load.
OS605 and NMOS 606 are provided, and the transistor PMOS is always ON.
609 and NMOS 610 (circuit C) are provided. And PMOS605
The connection point of the NMOS 610 and the PMOS 609 is connected to the control circuit B as SOUTP, and the connection point of the NMOS 610 and the NMOS 606 is connected as SOUTN.

【００２５】（動作）の説明 第６の実施の形態の動作を図１３のタイミング図をもち
いて説明すると、制御回路B内のPMOS602、NMOS603のON/
OFFはSOUTPとSOUTNによって行われる。図１３のタイミ
ング図中(c)、(g)参照。Description of (Operation) The operation of the sixth embodiment will be described with reference to the timing chart of FIG.
OFF is performed by SOUTP and SOUTN. See (c) and (g) in the timing chart of FIG.

【００２６】そして、PMOS602のゲート信号となるSOUTP
のLレベルはPMOS609の効果により、GND＋Vtp（PMOSの閾
値電圧）となる。また、NMOS603のゲート信号となるSOU
TNのHレベルはNMOS610の効果により、VDDーVtn（NMOSの
閾値電圧）となる。Then, SOUTP serving as a gate signal of the PMOS 602
L level becomes GND + Vtp (PMOS threshold voltage) due to the effect of the PMOS 609. In addition, SOU which becomes the gate signal of NMOS603
The H level of TN becomes VDD-Vtn (the threshold voltage of the NMOS) due to the effect of the NMOS 610.

【００２７】（効果）の説明 以上述べたように、本発明の第６の実施の形態によれ
ば、制御回路Bの制御信号（SOUTP、SOUTN）を出力負荷
を駆動するトランジスタと同じように動作するPMOS60
5、NMOS606と常時ON状態のトランジスタPMOS609、NMOS6
10より得て、そしてPMOS602のゲート信号LレベルをGND
よりも高く、NMOS603ののゲート信号HレベルをVDDより
も低くすることで、ON抵抗を高く設定できるようになり
OFFからON状態に変化（出力負荷を駆動）するトランジ
スタを通る過渡電流を抑制できるためスイッチングノイ
ズを抑制できるようになり、また出力負荷が増大しても
出力負荷と無関係に制御されるため、第７図に示すよう
に遅延時間の容量依存は直線近似できるようになり、出
力負荷の増えた場合の高速化がはかれる。Description of (Effect) As described above, according to the sixth embodiment of the present invention, the control signals (SOUTP, SOUTN) of the control circuit B operate in the same manner as the transistor driving the output load. PMOS60 to do
5.NMOS 606 and always-on transistors PMOS 609, NMOS 6
10 and the gate signal L level of PMOS 602 to GND
By setting the NMOS 603 gate signal H level lower than VDD, the ON resistance can be set higher.
Transient current passing through the transistor that changes from OFF to ON (drives the output load) can be suppressed, so that switching noise can be suppressed. In addition, even if the output load increases, control is performed independently of the output load. As shown in FIG. 7, the capacity dependence of the delay time can be approximated by a straight line, so that the speed can be increased when the output load increases.

【００２８】（第７の実施の形態） （構成）の説明 第７の実施の形態を図１４を用いて説明すると、第７の
実施の形態は第６の実施の形態の回路Cにこの回路を設
けたものとする。PMOS609とNMOS610の間にコンデンサ70
3を故意に設けている。(Seventh Embodiment) Description of (Structure) The seventh embodiment will be described with reference to FIG. 14. In the seventh embodiment, the circuit C is replaced with the circuit C of the sixth embodiment. Shall be provided. Capacitor 70 between PMOS 609 and NMOS 610
3 is intentionally provided.

【００２９】（動作）の説明 第７の実施の形態の動作を説明すると、基本的な動作は
図１３のタイミング図と同じであるが、故意に設けたコ
ンデンサ703の効果により、SOUTPとSOUTNの動作が緩や
かになり、S101の立ち下がり動作はより緩やかになり、
S104の立ち上がり動作もより緩やかにになる。Description of (Operation) The operation of the seventh embodiment will be described. The basic operation is the same as that shown in the timing chart of FIG. 13, but due to the effect of the capacitor 703 provided intentionally, SOUTP and SOUTN The operation becomes gradual, the falling operation of S101 becomes more gradual,
The rising operation of S104 also becomes gentler.

【００３０】（効果）の説明 以上述べたように、本発明の第７の実施の形態によれ
ば、制御回路Bの制御信号（SOUTP、SOUTN）を出力負荷
を駆動するトランジスタと同じように動作するPMOS60
5、NMOS606と常時ON状態のトランジスタPMOS609、NMOS6
10より得て、そしてPMOS602のゲート信号をGNDレベルよ
りも高く、NMOS603ののゲート信号をVDDよりも低くする
ことで、ON抵抗を高く設定できるようになり、コンデン
サ703の効果により、SOUTPとSOUTNの動作を緩やかにで
きるため、OFFからON状態に変化（出力負荷を駆動）す
るトランジスタを通る過渡電流を抑制できるためスイッ
チングノイズを抑制できるようになり、また出力負荷が
増大しても出力負荷と無関係に制御されるため、図７図
に示すように遅延時間の容量依存は直線近似できるよう
になり、出力負荷の増えた場合の高速化がはかれる。Description of (Effect) As described above, according to the seventh embodiment of the present invention, the control signals (SOUTP, SOUTN) of the control circuit B operate in the same manner as the transistor driving the output load. PMOS60 to do
5.NMOS 606 and always-on transistors PMOS 609, NMOS 6
10 and the gate signal of the PMOS 602 is higher than the GND level and the gate signal of the NMOS 603 is lower than VDD, so that the ON resistance can be set higher.By the effect of the capacitor 703, SOUTP and SOUTN Operation can be moderated, so that transient current passing through the transistor that changes from OFF to ON (drives the output load) can be suppressed, so that switching noise can be suppressed. Since the control is performed independently, the capacity dependence of the delay time can be approximated by a straight line as shown in FIG. 7, and the speed can be increased when the output load increases.

【００３１】（第８の実施の形態）の説明 （構成）の説明 本提案の第８の実施の形態を図１５を用いて説明する
と、第８の実施の形態は第１の実施の形態の回路Bにこ
の回路を設けたものとする。制御される（ON/OFFの切り
換えが行われる）トランジスタPMOS803、NMOS804がS101
とS104の間に直列に接続され、常時ON状態のNMOS801とP
MOS802がS101とS104の間に直列に接続され、PMOS803とN
MOS804の接続点とNMOS801とPMOS802の接続点は接続され
ている。Description of (Eighth Embodiment) Description of (Structure) An eighth embodiment of the present proposal will be described with reference to FIG. 15. The eighth embodiment is different from the first embodiment. It is assumed that the circuit B is provided with this circuit. The transistors PMOS 803 and NMOS 804 to be controlled (ON / OFF switching is performed)
NMOS801 and P, which are connected in series between
MOS802 is connected in series between S101 and S104, and PMOS803 and N
The connection point of the MOS 804 and the connection point of the NMOS 801 and the PMOS 802 are connected.

【００３２】（動作）の説明 第８の実施の形態の動作を説明すると、基本的な動作は
図２のタイミング図と同じであるが、S101立ち下がり時
の動作は、まずSOUT=LであるためPMOS803=ON、NMOS804=O
FFである。この状態から、S101がH→Lへ変化するが、NM
OS804がOFF状態であるためS101は瞬時に完全なLレベル
にならず（経路１）、その後SOUTがHレベルに近づくこ
とでNMOS804がON状態となり（経路２）S101はグランド
レベルとなる。次にS104立ち上がり時の動作は、まずSO
UT=HであるためPMOS803=OFF、NMOS804=ONである。この状
態から、S104がL→Hへ変化するが、PMOS803がOFF状態で
あるためS104は瞬時に完全なHレベルにならず（経路
２）、その後SOUTがLレベルに近づくことでPMOS803がON
状態となり（経路１）S104は電源レベルとなる。この動
作によりS101の立ち下がり動作はより緩やかになり、S1
04の立ち上がり動作もより緩やかにになる。Description of (Operation) The operation of the eighth embodiment will be described. The basic operation is the same as the timing chart of FIG. 2, but the operation at the falling of S101 is SOUT = L. PMOS803 = ON, NMOS804 = O
FF. From this state, S101 changes from H to L, but NM
Since OS 804 is in the OFF state, S101 does not instantaneously go to the complete L level (path 1), and then SOUT approaches the H level to turn on the NMOS 804 (path 2), and S101 goes to the ground level. Next, the operation at the rise of S104 is
Since UT = H, PMOS 803 = OFF and NMOS 804 = ON. From this state, S104 changes from L to H, but since the PMOS 803 is in the OFF state, S104 does not instantaneously go to the full H level (path 2), and then the PMOS 803 turns on when SOUT approaches the L level.
The state becomes (path 1), and S104 becomes the power supply level. With this operation, the falling operation of S101 becomes gentler and S1
The rising operation of 04 becomes slower.

【００３３】（効果）の説明 以上述べたように、本発明の第８の実施の形態によれ
ば、制御回路Bの制御信号（SOUT）を出力負荷を駆動す
るトランジスタと同じように動作するPMOS105、NMOS106
より得て、制御回路Bにおいても常時ON状態のNMOS801、P
MOS802のON抵抗値を自由に設定できるため、OFFからON
状態に変化（出力負荷を駆動）するトランジスタのを通
る過渡電流を抑制できるためスイッチングノイズを抑制
できるようになり、また出力負荷が増大しても出力負荷
と無関係に制御されるため、図７に示すように遅延時間
の容量依存は直線近似できるようになり、出力負荷の増
えた場合の高速化がはかれる。Description of (Effect) As described above, according to the eighth embodiment of the present invention, the control signal (SOUT) of the control circuit B is controlled by the PMOS 105 operating in the same manner as the transistor driving the output load. , NMOS106
In addition, in the control circuit B, the NMOS 801 and P
Since the ON resistance value of MOS802 can be set freely,
The switching current can be suppressed because the transient current passing through the transistor that changes to the state (drives the output load) can be suppressed, and even if the output load increases, the switching noise is controlled independently of the output load. As shown, the capacity dependence of the delay time can be approximated by a straight line, and the speed can be increased when the output load increases.

【００３４】（第９の実施の形態）の説明 （構成）の説明 本提案の第９の実施の形態を図１６を用いて説明する
と、第９の実施の実施の形態は第６の実施の形態の回路
Bにこの回路を設けたものとする。制御される（ON/OFF
の切り換えが行われる）トランジスタPMOS803、NMOS804
がS101とS104の間に直列に接続され、常時ON状態のNMOS
801とPMOS802がS101とS104の間に直列に接続され、PMOS
803とNMOS804の接続点とNMOS801とPMOS802の接続点は接
続されている。なお、PMOS803のゲートにはSOUTPが接続
されNMOS804にはSOUTNが接続されている。Description of (Ninth Embodiment) Description of (Configuration) The ninth embodiment of the present proposal will be described with reference to FIG. 16. The ninth embodiment is the same as the sixth embodiment. Form circuit
Assume that this circuit is provided in B. Controlled (ON / OFF
Switching is performed) transistors PMOS803, NMOS804
Is connected in series between S101 and S104, and the NMOS is always on.
801 and PMOS 802 are connected in series between S101 and S104, and PMOS
The connection point between 803 and NMOS 804 and the connection point between NMOS 801 and PMOS 802 are connected. The gate of the PMOS 803 is connected to SOUTP, and the NMOS 804 is connected to SOUTN.

【００３５】（動作）の説明 第９の実施の形態の動作を説明すると、基本的な動作は
図１３のタイミング図と同じであるが（PMOS803のゲー
ト信号となるSOUTPのLレベルはPMOS609の効果により、G
ND＋Vtp（PMOSの閾値電圧）となる。また、NMOS804のゲ
ート信号となるSOUTNのHレベルはNMOS610の効果によ
り、VDDーVtn（NMOSの閾値電圧）となる）、S101立ち下
がり時の動作は、まずSOUTN=L、SOUTP=GND＋Vtp（PMOS
の閾値電圧）であるためPMOS803=ON、NMOS804=OFFであ
る。この状態から、S101がH→Lへ変化するが、NMOS804
がOFF状態であるためS101は瞬時に完全なLレベルになら
ず（経路１）、その後SOUTNがHレベル（VDDーVtn（NMOS
の閾値電圧））に近づくことでNMOS804がON状態、SOUTP
=Hに近づくためPMOS803がOFF状態となり（経路２）S101
はグランドレベルとなる。次にS104立ち上がり時の動作
は、まずSOUTP=H、SOUTN=VDDーVtn（NMOSの閾値電圧）
であるためPMOS803=OFF、NMOS804=ONである。この状態か
ら、S104がL→Hへ変化するが、PMOS803がOFF状態である
ためS104は瞬時に完全なHレベルにならず（経路２）、
その後SOUTPがLレベル（GND＋Vtp（PMOSの閾値電圧））
に近づくことでPMOS803がON状態となり（経路１）S104
は電源レベルとなる。この動作によりS101の立ち下がり
動作はより緩やかになり、S104の立ち上がり動作もより
緩やかにになる。(Operation) The operation of the ninth embodiment will be described. The basic operation is the same as that shown in the timing chart of FIG. 13, except that the L level of SOUTP serving as the gate signal of the PMOS 803 is equal to the effect of the PMOS 609. By G
ND + Vtp (PMOS threshold voltage). In addition, the H level of SOUTN, which is the gate signal of the NMOS 804, becomes VDD-Vtn (the threshold voltage of the NMOS) due to the effect of the NMOS 610. At the time of the falling of S101, first, SOUTN = L, SOUTP = GND + Vtp (PMOS
PMOS803 = ON and NMOS804 = OFF. From this state, S101 changes from H to L.
Is in the OFF state, S101 does not instantly go to a complete L level (path 1), and then SOUTN goes to an H level (VDD-Vtn (NMOS
NMOS 804 turns on when the threshold voltage approaches
= H, the PMOS 803 is turned off (path 2) S101
Is at the ground level. Next, the operation at the rise of S104 is as follows: SOUTP = H, SOUTN = VDD−Vtn (NMOS threshold voltage)
Therefore, PMOS 803 = OFF and NMOS 804 = ON. From this state, S104 changes from L to H, but since the PMOS 803 is in the OFF state, S104 does not instantaneously go to the full H level (path 2).
Then SOUTP goes low (GND + Vtp (PMOS threshold voltage))
Approaching to turn on the PMOS 803 (path 1) S104
Is the power supply level. By this operation, the falling operation of S101 becomes more gentle, and the rising operation of S104 becomes more gentle.

【００３６】（効果）の説明 以上述べたように、本発明の第９の実施の形態によれ
ば、制御回路Bの制御信号（SOUT）を出力負荷を駆動す
るトランジスタと同じように動作するPMOS605、NMOS606
より得て、制御回路Bにおいても常時ON状態のNMOS801、P
MOS802のON抵抗値を自由に設定でき、そしてPMOS803の
ゲート信号LレベルをGNDよりも高く、NMOS804ののゲー
ト信号HレベルをVDDよりも低くすることで、ON抵抗を高
く設定できるようになるため、OFFからON状態に変化
（出力負荷を駆動）するトランジスタのを通る過渡電流
を抑制できるためスイッチングノイズを抑制できるよう
になり、また出力負荷が増大しても出力負荷と無関係に
制御されるため、図７に示すように遅延時間の容量依存
は直線近似できるようになり、出力負荷の増えた場合の
高速化がはかれる。Description of (Effect) As described above, according to the ninth embodiment of the present invention, the control signal (SOUT) of the control circuit B is controlled by the PMOS 605 operating in the same manner as the transistor driving the output load. , NMOS606
In addition, in the control circuit B, the NMOS 801 and P
The ON resistance of MOS802 can be freely set, and the ON resistance can be set higher by setting the gate signal L level of PMOS 803 higher than GND and the gate signal H level of NMOS 804 lower than VDD. Since the transient current passing through the transistor that changes from OFF to ON (drives the output load) can be suppressed, switching noise can be suppressed, and even if the output load increases, it is controlled independently of the output load. As shown in FIG. 7, the capacity dependence of the delay time can be approximated by a straight line, so that the speed can be increased when the output load increases.

【００３７】（第１０の実施の形態）の説明 （構成）の説明 第１０の実施の形態を図１７を用いて説明すると、出力
負荷を駆動するPMOS607とNMOS608と同じように動作する
回路Aを図のように設けている。そして、その出力SOUT
をPMOS604、NMOS603のゲートに接続している。Description of (Tenth Embodiment) Description of (Structure) The tenth embodiment will be described with reference to FIG. 17. A circuit A which operates in the same manner as a PMOS 607 and an NMOS 608 for driving an output load is provided. It is provided as shown in the figure. And its output SOUT
Are connected to the gates of the PMOS 604 and the NMOS 603.

【００３８】（動作）の説明 第１０の実施の形態の動作を図１８のタイミング図をも
ちいて説明すると、PMOS604、NMOS603のON/OFFはSOUTに
よって行われる。図１８のタイミング図中(k)、(o)を参
照。Description of (Operation) The operation of the tenth embodiment will be described with reference to the timing chart of FIG. 18. ON / OFF of the PMOS 604 and the NMOS 603 is performed by SOUT. See (k) and (o) in the timing diagram of FIG.

【００３９】（効果）の説明 以上説明したように、本発明の第１０の実施の形態によ
れば、PMOS604とNMOS603の制御信号（SOUT）を出力負荷
を駆動するトランジスタと同じように動作する回路Aよ
り得たため、出力負荷を駆動するトランジスタを分割し
た構成のものでも、OFFからON状態に変化（出力負荷を
駆動）するトランジスタを通る過渡電流を抑制できるた
めスイッチングノイズを抑制できるようになり、また出
力負荷が増大しても出力負荷と無関係に制御されるた
め、第７図に示すように遅延時間の容量依存は直線近似
できるようになり、出力負荷の増えた場合の高速化がは
かれる。Description of (Effect) As described above, according to the tenth embodiment of the present invention, the control signal (SOUT) of the PMOS 604 and the NMOS 603 operates in the same manner as the transistor driving the output load. Since it is obtained from A, even with a configuration in which the transistor driving the output load is divided, the switching current can be suppressed because the transient current passing through the transistor that changes from OFF to ON (drives the output load) can be suppressed, Even if the output load increases, the delay time is controlled irrespective of the output load. Therefore, as shown in FIG. 7, the capacity dependence of the delay time can be approximated by a straight line, and the speed when the output load increases can be increased.

【００４０】（第１１の実施の形態） （構成）の説明 第１１の実施の形態を図１９を用いて説明すると、出力
負荷を駆動するPMOS607とNMOS608と同じように動作する
回路Cを図のように設けている。そして、その出力SOUTP
をPMOS604、SOUTNをNMOS603のゲートに各々接続してい
る。(Eleventh Embodiment) Description of (Structure) Referring to FIG. 19, an eleventh embodiment will be described. A circuit C which operates in the same manner as a PMOS 607 and an NMOS 608 for driving an output load is shown in FIG. It is provided as follows. And its output SOUTP
Are connected to the gate of the PMOS 604 and SOUTN to the gate of the NMOS 603, respectively.

【００４１】（動作）の説明 第１１の実施の形態の動作を図１９のタイミング図をも
ちいて説明すると、PMOS602、NMOS603のON/OFFはSOUTP
とSOUTNによって行われる。図１９のタイミング図中
(k)、(o)を参照。(Description of Operation) The operation of the eleventh embodiment will be described with reference to the timing chart of FIG. 19. The ON / OFF of the PMOS 602 and the NMOS 603 is SOUTP
And done by SOUTN. In the timing chart of FIG.
See (k) and (o).

【００４２】そして、PMOS604のゲート信号となるSOUTP
のLレベルはPMOS609の効果により、GND＋Vtp（PMOSの閾
値電圧）となる。また、NMOS603のゲート信号となるSOU
TNのHレベルはNMOS610の効果により、VDDーVtn（NMOSの
閾値電圧）となる。Then, SOUTP which becomes a gate signal of the PMOS 604
L level becomes GND + Vtp (PMOS threshold voltage) due to the effect of the PMOS 609. In addition, SOU which becomes the gate signal of NMOS603
The H level of TN becomes VDD-Vtn (the threshold voltage of the NMOS) due to the effect of the NMOS 610.

【００４３】（効果）の説明 以上説明したように、本発明の第１１の実施例によれ
ば、PMOS604の制御信号（SOUTP）とNMOS603の制御信号
（SOUTN）を出力負荷を駆動するトランジスタと同じよ
うに動作する回路Cより得たため、出力負荷を駆動する
トランジスタを分割した構成のものでも、PMOS602のゲ
ート信号LレベルをGNDよりも高く、NMOS603ののゲート
信号HレベルをVDDよりも低くすることで、ON抵抗を高く
設定できるようになりOFFからON状態に変化（出力負荷
を駆動）するトランジスタを通る過渡電流を抑制できる
ためスイッチングノイズを抑制できるようになり、また
出力負荷が増大しても出力負荷と無関係に制御されるた
め、第７図に示すように遅延時間の容量依存は直線近似
できるようになり、出力負荷の増えた場合の高速化がは
かれる。Description of (Effect) As described above, according to the eleventh embodiment of the present invention, the control signal (SOUTP) of the PMOS 604 and the control signal (SOUTN) of the NMOS 603 are the same as the transistors driving the output load. The gate signal L level of the PMOS 602 should be higher than GND, and the gate signal H level of the NMOS 603 should be lower than VDD, even if the transistor driving the output load is divided, because it is obtained from the circuit C that operates as follows. Therefore, the ON resistance can be set higher and the transient current passing through the transistor that changes from OFF to ON (drives the output load) can be suppressed, so that switching noise can be suppressed, and even if the output load increases, Since the control is performed irrespective of the output load, the capacity dependence of the delay time can be approximated by a straight line as shown in FIG. 7, and the speed can be increased when the output load increases.

【００４４】（利用形態）の説明 （変形例） （１）第２の実施の形態のPMOS81とNMOS82は抵抗素子で
もよい。 （２）第１の実施例のPMOS107、NMOS108を駆動する回路
部（PMOS101、102、105、NMOS103、104、106）は１つと
しているが、PMOS107用とNMOS108用に２つ設けてもよ
い。なお、他の実施例についても同じ構成でかまわな
い。Description of (Usage) (Modification) (1) The PMOS 81 and the NMOS 82 of the second embodiment may be resistance elements. (2) Although the number of the circuit sections (PMOSs 101, 102, 105, NMOSs 103, 104, 106) for driving the PMOS 107 and the NMOS 108 of the first embodiment is one, two circuits may be provided for the PMOS 107 and the NMOS 108. The same configuration may be applied to other embodiments.

【００４５】[0045]

【発明の効果】以上詳細に説明したように、本発明の代
表的なものによれば、次のような効果を奏することがで
きる。As described above in detail, according to the representative embodiment of the present invention, the following effects can be obtained.

【００４６】すなわち、本発明によれば、制御回路の制
御信号を、出力負荷を駆動する出力トランジスタと同じ
ように動作するトランジスタより得るようにしたため、
出力負荷を駆動するトランジスタを流れる過渡電流を抑
制できるためスイッチングノイズを抑制できるようにな
り、また出力負荷が増大しても出力負荷と無関係に制御
されるため、遅延時間の容量依存は直線近似できるよう
になり、出力負荷の増えた場合の高速化がはかれる。That is, according to the present invention, the control signal of the control circuit is obtained from the transistor which operates in the same manner as the output transistor for driving the output load.
The switching current can be suppressed because the transient current flowing through the transistor driving the output load can be suppressed, and even if the output load increases, the delay time can be controlled independently of the output load. As a result, the speed can be increased when the output load increases.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第１の実施の形態を示す回路図FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

【図２】本発明の第１の実施の形態の動作を示すタイミ
ング図FIG. 2 is a timing chart showing the operation of the first embodiment of the present invention.

【図３】従来の技術を示す回路図FIG. 3 is a circuit diagram showing a conventional technique.

【図４】従来の回路の動作を示すタイミング図FIG. 4 is a timing chart showing the operation of a conventional circuit.

【図５】従来の技術を示す回路図FIG. 5 is a circuit diagram showing a conventional technique.

【図６】従来の回路の動作を示すタイミング図FIG. 6 is a timing chart showing the operation of a conventional circuit.

【図７】遅延時間の容量依存特性を示すグラフFIG. 7 is a graph showing a capacity dependence characteristic of a delay time.

【図８】本発明の第２の実施の形態を示す回路図FIG. 8 is a circuit diagram showing a second embodiment of the present invention.

【図９】本発明の第３の実施の形態を示す回路図FIG. 9 is a circuit diagram showing a third embodiment of the present invention.

【図１０】本発明の第４の実施の形態を示す回路図FIG. 10 is a circuit diagram showing a fourth embodiment of the present invention.

【図１１】本発明の第５の実施の形態を示す回路図FIG. 11 is a circuit diagram showing a fifth embodiment of the present invention.

【図１２】本発明の第６の実施の形態を示す回路図FIG. 12 is a circuit diagram showing a sixth embodiment of the present invention.

【図１３】本発明の第６の実施の形態の動作を示すタイ
ミング図FIG. 13 is a timing chart showing the operation of the sixth embodiment of the present invention.

【図１４】本発明の第７の実施の形態を示す回路図FIG. 14 is a circuit diagram showing a seventh embodiment of the present invention.

【図１５】本発明の第８の実施の形態を示す回路図FIG. 15 is a circuit diagram showing an eighth embodiment of the present invention.

【図１６】本発明の第９の実施の形態を示す回路図FIG. 16 is a circuit diagram showing a ninth embodiment of the present invention.

【図１７】本発明の第１０の実施の形態を示す回路図FIG. 17 is a circuit diagram showing a tenth embodiment of the present invention.

【図１８】本発明の第１０の実施の形態の動作を示すタ
イミング図FIG. 18 is a timing chart showing the operation of the tenth embodiment of the present invention.

【図１９】本発明の第１１の実施の形態を示す回路図FIG. 19 is a circuit diagram showing an eleventh embodiment of the present invention.

【図２０】本発明の第１０の実施の形態の動作を示すタ
イミング図FIG. 20 is a timing chart showing the operation of the tenth embodiment of the present invention;

【符号の説明】[Explanation of symbols]

１０５・・・ＰＭＯＳ １０６・・・ＮＭＯＳ １０７・・・ＰＭＯＳ １０８・・・ＮＭＯＳ ＯＵＴ・・・出力端子 ＩＮ・・・入力端子 105 ... PMOS 106 ... NMOS 107 ... PMOS 108 ... NMOS OUT ... output terminal IN ... input terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 出力端子を介して電源電位と接地電位と
の間に直列に接続された第１及び第２のトランジスタを
有する出力回路において、前記電源電位と接地電位との
間に直列に接続され、各々の制御電極が各々前記第１及
び第２のトランジスタの制御電極に接続された第３及び
第４のトランジスタとを有することを特徴とする出力回
路。1. An output circuit having first and second transistors connected in series between a power supply potential and a ground potential via an output terminal, wherein the output circuit is connected in series between the power supply potential and the ground potential. An output circuit, wherein each control electrode has a third transistor and a fourth transistor connected to control electrodes of the first and second transistors, respectively.
JP09572497A 1997-04-14 1997-04-14 Output circuit Expired - Fee Related JP3516569B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09572497A JP3516569B2 (en) 1997-04-14 1997-04-14 Output circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09572497A JP3516569B2 (en) 1997-04-14 1997-04-14 Output circuit

Publications (2)

Publication Number Publication Date
JPH10290154A true JPH10290154A (en) 1998-10-27
JP3516569B2 JP3516569B2 (en) 2004-04-05

Family

ID=14145431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09572497A Expired - Fee Related JP3516569B2 (en) 1997-04-14 1997-04-14 Output circuit

Country Status (1)

Country Link
JP (1) JP3516569B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6559676B1 (en) 2001-11-30 2003-05-06 Oki Electric Industry Co., Ltd. Output buffer circuit
US6844753B2 (en) 2003-01-17 2005-01-18 Oki Electric Industry Co., Ltd. Output circuit of semiconductor integrated circuit device
WO2024180909A1 (en) * 2023-02-28 2024-09-06 ソニーセミコンダクタソリューションズ株式会社 Drive circuit, imaging device, and method for controlling drive circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6559676B1 (en) 2001-11-30 2003-05-06 Oki Electric Industry Co., Ltd. Output buffer circuit
US6844753B2 (en) 2003-01-17 2005-01-18 Oki Electric Industry Co., Ltd. Output circuit of semiconductor integrated circuit device
WO2024180909A1 (en) * 2023-02-28 2024-09-06 ソニーセミコンダクタソリューションズ株式会社 Drive circuit, imaging device, and method for controlling drive circuit

Also Published As

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