JPH0834424B2 - Output circuit - Google Patents

Description

The present invention relates to an output circuit, and more particularly to an output circuit used as an output buffer or the like of a semiconductor integrated circuit.

[Conventional technology]

In this type of conventional output circuit, the driving capability is set according to the magnitude of the load connected to the output end.

FIG. 2 shows a conventional output circuit using an inverter 6 having a CMOS structure. The transistor P6 is a P-channel MOS transistor, and the transistor N6 is an N-channel MOS transistor. The source and drain of both are connected in series to be connected to the power supply voltage VDD, the interconnection point is connected to the output end 2, and the gates of both are connected to the input end 1 to form the inverter 6. A capacitive load C _L is connected to the output terminal 2. The drive capability of this output circuit is
It can be determined by the channel width of P6 and N6.

[Problems to be solved by the invention]

The conventional output circuit described above uses a transistor P6 to adapt to the case where the load C _L to be driven has a large capacitance value.
If the channel width of N6 and N6 are set wide, there is a drawback that excessive transient current is generated at the time of switching to cause power supply noise. That is, when the capacitance value of the load C _L is large, by setting the channel width of the transistors P6 and N6 to be wide to reduce the drive resistance value for the load C _L at the time of switching, the switching operation is performed within a predetermined time. By setting the time constant of the drive path so that the above is completed, the required drive capacity can be obtained. However, since there is wiring inductance in the drive path, when the load C _L has a large capacitance value and a drive resistance value is small as described above, as shown in FIG. appear. Along with this, a transient current flows through the power supply wiring to cause power supply noise, which causes a malfunction of the semiconductor circuit supplied with the power supply.

An object of the present invention is to provide an output circuit that suppresses oscillatory transient current at the time of switching to reduce power supply noise and obtains a desired driving capability in a steady state.

[Means for solving problems]

In the output circuit of the present invention, the sources of the first and second transistors connected in series and having a large driving resistance are respectively connected to the first source.
And an inverter connected to a second power supply potential and having a drain of the interconnection connected to an output terminal and gates of the first and second transistors connected to an input terminal; and a source and a drain of the first and second terminals, respectively.
Third and fourth transistors connected in parallel between the source and drain of the transistor and having a smaller drive resistance than the first and second transistors; and a source connected to the first power supply potential and a drain. A fifth transistor having a gate connected thereto, a sixth transistor having a source connected to the drain of the fifth transistor and a drain connected to the gate of the fourth transistor, and a source connected to the second power supply potential. A seventh transistor having a drain and a gate connected to each other, a source being the drain of the seventh transistor, a drain being the gate of the third transistor, and a gate being the gate of the sixth transistor and the first transistor. And an eighth transistor connected to the drain of the interconnection of the second transistor, respectively. Transistors, ninth and tenth transistors having sources connected to the first and second power supply potentials, interconnecting drains and interconnecting gates connected to the input terminal, and sources connected to the first and second transistors. Control having drains of a second power supply potential connected to the gates of the third and fourth transistors and gates connected to the drains of the interconnections of the ninth and tenth transistors, respectively. This control circuit detects the level of the binary input signal at the input end and the level of the output signal at the output end, and detects the change in the level of the input signal. After the transistor is turned off, the level of the output signal is set by the fifth and sixth transistors or the seventh and eighth transistors. Therefore, the electric charge of the load connected to the output terminal is gradually discharged or charged until the set threshold value is reached, and when the threshold value is reached, depending on the direction of the level change of the input signal, the third and fourth transistors A control signal for turning on one of them is generated and applied to the gates of the third and fourth transistors.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The transistors P1 to P6 are channel MOS transistors, and the transistors N1 to N6 are N channel MOS transistors. The transistors P1 and N1 have a narrow channel width and a large driving resistance. There is. Inverter 3 composed of transistors P1 and N1
The input end of is connected to the input end 1, and the output end of the inverter 3 is connected to the output end 2. The control circuit 5 controls the level of the input signal at the input end 1 and the output end 2 as described below.
Output level of, and generates a signal for controlling the operation of the transistors P6 and N6 according to the detection result,
This is applied to the gates of transistors P6 and N6.

When the level of the binary input signal from the input terminal 1 is low (or high), the sources and drains of the transistors P1, P2, N3 to N5, P6 are on (or off)
Then, the transistors N1, N2, P3 to P5, N6 are in the off state (or on state), and the output signal of the output terminal 2 is at the high level.

When the level of the input signal changes from low to high, first, the transistors P1 and P2 are changed from the on state to the off state, and the transistors N1 and N2 are changed from the off state to the on state.
As a result, the level of the output signal of the inverter 4 including the transistors P2 and N2 changes from high to low. In response to this, the transistor P5 changes from the off state to the on state, and the transistor N5 changes from the on state to the off state. At this time, since the transistors P3, P4, N5 are all in the off state, the gate potential of the transistor N6 holds the low level, and therefore the transistor N6 remains in the off state. At this time, the transistors N3, N4,
P5 is all on, and the gate potential of the transistor P6 is a value obtained by dividing the power supply voltage VDD by the on resistance of the transistor P5 and the on resistances of the transistors N3 and N4. In this embodiment, the on resistance of the transistor P5 is
It is set to be sufficiently smaller than the on-resistance of 4 so that the transistor P6 is turned off when all the transistors N3, N4, P5 are turned on. In this state, the charged charge of the capacitive load C _L begins to be discharged through the source and gate of the transistor N1. As this discharge progresses,
When the level of the output terminal 2 decreases and reaches the sum of the thresholds of the transistors P3 and P4 or less, the transistors P3 and P4 shift from the off state to the on state, and accordingly, the gate potential of the transistor N6 rises, The transistor N6 is changed from the off state to the on state. When the level of the output terminal 2 further decreases and reaches the sum of the thresholds of the transistors N3 and N4 or less, the transistors N3 and N4 change from the ON state to the OFF state, and the gate potential of the transistor N6 becomes completely high level. After this, the discharge of the charge on the load C _L takes place through both the transistors N1 and N6.

As described above, only the transistor N1 is the discharge path at the beginning after the start of discharge, and the transistor N6 is load-connected to the discharge path by detecting the drop in the output level accompanying the progress of discharge.

The case where the level of the input signal at the input terminal 1 changes from low to high has been described above. However, when the level of the input signal changes from high level to low level, relative operation to this causes the load C _L to be changed. At the beginning of charging, the charging is performed only through the transistor P1, and the transistors P1 and P6
Charge both.

In this embodiment, first, a transistor with a large drive resistance is used.
Sudden change of charge / discharge current is suppressed by making P1 or N1 conductive, detecting output level change, and making transistor P6 or N6 with small drive resistance conductive when the output level approaches the final level. Power noise can be reduced. Moreover, in the steady state, the two transistors P1 and P6 (or N1 and N6) are both in the conductive state, so that the drive resistance value for the load C _L can be kept sufficiently low. FIG. 3 is a signal waveform diagram illustrating, by comparison, output signals obtained with respect to the same input signal in both the present embodiment and the conventional output circuit. In the conventional example, when the level of the input signal changes, the load is charged and discharged from the beginning with a small drive resistance.
In particular, a fairly large transient vibration occurs in the output signal immediately after the rise of the input signal. On the other hand, in this embodiment, the charging / discharging is first performed in the state where the driving resistance is large, and the driving resistance value is lowered to the same value as the conventional example, so that no transient vibration occurs in the output signal.

〔The invention's effect〕

As described above, by applying the output circuit of the present invention, it is possible to reduce power supply noise generated due to switching, and particularly when the load capacitance is large or a large number of output circuits operate simultaneously. Since noise can be reduced, the limitation on the number of output lines that can operate simultaneously in a large-scale semiconductor integrated circuit or the like can be relaxed more than before.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional output circuit, and FIG. 3 is a signal waveform diagram illustrating an operation of the embodiment of the present invention and a conventional output circuit. . 1 ... input terminal, 2 ... output terminal, 3,4,6 ... inverter, 5 ... control circuit, P1 to P6, N1 to N6 ... transistors, C _L ... load.

Claims (1)

[Claims] 1. Sources of first and second transistors connected in series and having a large driving resistance are first and second sources, respectively.
An inverter in which the drains of the interconnections are connected to the output end and the gates of the first and second transistors are connected to the input end of; and a source and a drain of the first and second transistors, respectively. Third and fourth transistors connected in parallel between the source and drain and having a driving resistance smaller than that of the first and second transistors; a source connected to the first power supply potential, and a drain and a gate A fifth transistor connected to the fifth transistor, a sixth transistor having a source connected to the drain of the fifth transistor and a drain connected to the gate of the fourth transistor, and a source connected to the second power supply potential. A seventh transistor having a drain and a gate connected to each other and a source connected to the drain of the seventh transistor. An eighth transistor having a drain connected to the gate of the third transistor and a gate connected to the gate of the sixth transistor and the drain of the interconnection of the first and second transistors, respectively, and the source to the eighth transistor. Ninth and tenth transistors connected to the first and second power supply potentials, interconnecting drains and interconnecting gates to the input terminal, and source to the first
And a drain to the second power supply potential,
A control circuit having a gate of the transistor and an eleventh and a twelfth transistor whose gates are connected to the drains of the interconnections of the ninth and tenth transistors, respectively; When the level of the input signal of the value and the level of the output signal of the output end are detected and the level change of the input signal is detected, first the third and fourth
Charge of the load connected to the output terminal until the level of the output signal reaches a threshold value preset by the fifth and sixth transistors or the seventh and eighth transistors after turning off the transistor of The control signal is generated to gradually turn on or discharge one of the third and fourth transistors according to the direction of the level change of the input signal when the threshold voltage is reached by discharging or charging the third and the third transistors. An output circuit provided to the gate of a fourth transistor.