JP2550674B2 - Bus driver - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus driver, and more particularly to a bus driver capable of controlling the drive capability from outside the IC.

[Conventional technology]

In the conventional bus driver, the drive capacity is fixed for each sample, and it is impossible for the user to change it.

[Problems to be Solved by the Invention]

As described above, the conventional bus driver has a fixed drive capability, and even if the drive capability is insufficient or too large, the user cannot handle it.

When the drive capacity is insufficient, the fan-out is insufficient, and the high-speed bus cycle cannot be kept up, and it cannot be used at all.

On the other hand, if the drive capacity is too large, when the bus is charged / discharged, that is, when the output level of the bus driver changes, large noise is generated in the power supply line and ground line of the mounting board, which may cause malfunction of the circuit. Become.

For the above reasons, it is desirable that the drive capacity is the minimum necessary, but the absolute value depends on the circuit and mounting state of each user, and cannot be determined unconditionally. Further, in the MOS output driver, the parasitic diode in the output stage is sometimes used for electrostatic protection, and the size of the driver cannot be reduced to a certain extent or less.

[Differences from the Prior Art of the Invention]

The bus driver of the present invention is different from the above-described conventional bus driver in that the user can set the optimum drive capability by using the external terminals of the bus driver.

[Means for solving the problem]

The bus driver of the present invention has a function of controlling the drive capability by an external terminal.

〔Example〕

FIG. 1 is a circuit diagram of a first embodiment of the present invention, which is a CMOS output driver capable of controlling a low level drive capability.

The output driver is composed of enhancement type P-channel transistors 1 and 2 and enhancement type N-channel transistors 3 and 4. Output data 5
Has its logic level output to the output terminal 6. The source-gate voltage V _GS when the transistor 3 is turned on is the voltage between the ground and the control terminal 7, and the drive capability of the transistor 3 can be controlled by changing V _GS according to the following equation.

I _D = 1 / 2K {2 (V _GS −V _T ) V _DS −V _DS ² } (1) (1) is an approximate expression for the drain current I _D of the MOS transistor, and K is the process and transistor , V _T is the threshold voltage, V _DS is the drain-source voltage, and is equal to the output voltage here. According to the equation (1), when V _DS is kept constant and V _GS is increased, I _D is increased, and when V _GS is decreased, I _D is reduced. In this way, the drive capability of the transistor 3 can be controlled.

2 and 3 are circuits of Embodiments 2, 3 and 4, respectively, all of which are CMOS, and the low level drive capability can be controlled.

In FIG. 2, the enhancement type P-channel transistor 8 and the enhancement type N-channel transistors 9 and 10 constitute a driver. The low level drive capability can be increased because the transistors 9 and 10 are connected in parallel. When the control terminal 7 is low, the output of the AND gate 11 is low
Since 0 is off and only the transistor 9 drives a low level, the capability is low. On the contrary, when the control terminal 7 is high, both the transistors 9 and 10 drive so that the capability is high.

In FIG. 3, an enhancement P channel transistor 12, an enhancement N channel transistor 13, and a depletion type transistor 14 constitute an output driver. Similar to the first embodiment, the drive capability of the transistor 14, that is, the resistance value can be controlled by the control terminal 7 according to the equation (1) to change the low level drive capability.

〔The invention's effect〕

As described above, the bus driver of the present invention has an effect that the driver user can set the optimum drive capacity by providing the external terminal capable of controlling the drive capacity.

[Brief description of drawings]

1, 2 and 3 are circuit diagrams of Embodiments 1, 2 and 3 of the present invention. 1,2,8,12 …… Enhancement type P-channel transistor, 3,4,9,10,13 …… Enhancement type N-channel transistor, 14 …… Depletion type N-channel transistor, 5 …… Output data, 6 …… Output terminal, 7
...... Control terminal, 11 …… AND gate.

Claims (3)

(57) [Claims] 1. A bus driver comprising a transistor connected between a bus to be driven and a power supply terminal and driving the bus to the potential of the power supply terminal in response to a data signal, the external terminal and the transistor. And a control means for changing the voltage applied based on the data signal between the gate and source of the bus driver according to the voltage supplied to the external terminal. 2. A first and a second transistor are connected in parallel between a bus to be driven and a power supply terminal to supply a data signal to a gate of the first transistor and a gate circuit, The external terminal of the gate circuit is the first
Is transmitted to the gate of the second transistor, and when the external terminal is at the second logic level, the second transistor is held in the off state regardless of the data signal. A bus driver, characterized in that a level is applied to the gate of the second transistor. 3. A transistor and a variable resistance element are connected in series between a bus to be driven and a power supply terminal, the transistor receives a data signal at its gate, and the variable resistance element responds to a voltage of an external terminal. Bus driver characterized in that its resistance value is changed.