JP3271269B2 - Output drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low noise output drive circuit in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional output drive circuit using a conventional insulated gate field effect transistor (hereinafter abbreviated as MOSFET) has a source electrode of a P-type MOSFET connected to a positive power supply terminal + VDD as shown in FIG. The source electrode of the N-type MOSFET is connected to the negative power supply terminal -VSS, and the drain electrode and the gate electrode of the P-type and N-type MOSFETs are connected to each other.

[0003]

In the conventional circuit described above, the output potential fluctuates to the full power supply from + VDD to -VSS as shown in FIG. 5, and further transiently exceeds the power supply potential, causing overshoot. Since the undershoot is caused, the driving capability is increased, and the noise due to the transient current when the output potential changes is excessively large, which adversely affects other circuits.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an output drive circuit in which noise due to a transient current when an output potential changes is reduced.

[0005]

According to the present invention, there is provided an output driving circuit for outputting a signal having an amplitude between a first potential and a second potential based on an input signal inputted to a signal input point (13). A drive circuit for outputting to an output point (14), wherein the drive circuit is connected to the signal input point and the signal output point and corresponds to a change in the input signal from a first logic level to a second logic level. A first drive circuit that outputs a third potential between the first potential and the second potential, and is connected to the signal input point, and wherein the input signal changes from the first logic level to the first logic level. A first signal is output to the first signal line in response to the change to the second logic level, and in response to the input signal changing from the first logic level to the second logic level. A delay control circuit for outputting a second signal to a second signal line, and supplying the first potential A first power supply line and a second power supply line for supplying the second potential. The first power supply line and the second power supply line are connected in series. The gate of the second transistor is connected to the first signal line, and the gate of the second transistor is connected to the second signal line.
And a second drive circuit having a connection point between the second transistor and a signal output point, respectively, wherein the delay control circuit is configured to change a response of the second signal to a response of the first signal. It is characterized in that it is configured to be output after a given time delay. Further, the output drive circuit of the present invention,
The first driving circuit includes a third transistor of a first conductivity type having a source terminal connected to a first power supply line, and a second conductivity type transistor having a source terminal connected to a second power supply line. A fourth transistor, and fifth and sixth transistors of complementary conductivity type connected between a drain terminal of the third transistor and a drain terminal of the fourth transistor; A gate terminal of the third transistor is connected to a drain terminal of the third transistor;
A gate terminal of the fourth transistor is connected to a drain terminal of the fourth transistor, a source terminal of the fifth transistor is connected to a drain terminal of the transistor of the third transistor, and the sixth transistor Is connected to the drain terminal of the transistor of the fourth transistor, the gate terminals of the fifth and sixth transistors are connected to the signal input point, and the drain terminals of the fifth and sixth transistors are Are connected to a signal output point. Further, the output drive circuit according to the present invention, when the input signal changes from the first logical level to the second logical level,
Are turned off within a shorter time than the given time.

[0006]

According to the above construction of the present invention, the P- type M is provided on the + VDD side.
OSFET, the first using an N- type MOSFET on the -VSS side
In the initial stage, the output potential does not swing to the full power supply potential, the transient current when the output potential changes can be suppressed, and the overshoot and undershoot can be suppressed. Therefore, the output drive circuit is less likely to generate noise.

[0007]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, a circuit surrounded by a broken line 10 is a first drive circuit, a circuit surrounded by a broken line 11 is a second drive circuit, and a circuit surrounded by a broken line 12 is a delay control circuit. In the first drive circuit 10, the P-type MOSFET 15
Is connected to the positive power supply electrode + VDD, and the gate electrode and the drain electrode are connected to each other. P
The source electrode of the MOSFET 16 is the P-type MOSFET.
It is connected to the drain electrode of T15. N-type MOSF
The source electrode of ET17 is connected to the negative power supply electrode -VSS, and the gate electrode and the drain electrode are connected to each other. The source electrode of the N-type MOSFET 18 is
It is connected to the drain electrode of OSFET17. The gate electrodes of the P-type MOSFET 16 and the N-type MOSFET 18 are connected to each other and to the input terminal 13, and the drain electrodes are connected to each other and to the output terminal 14. In the second drive circuit 11, the source electrode of the P-type MOSFET 19 is connected to + VDD, the source electrode of the N-type MOSFET 20 is connected to -VSS, and the P-type MOSFET 19 and the N-type MOSFET are connected.
The respective drain electrodes of the SFET 20 are connected to each other and to the output terminal 14. The delay control circuit 12 includes two inverter circuits 23 and 24 serving as delay elements, an OR circuit 21 and an AND circuit 22. The input terminal 13 is connected to the input terminal of the inverter circuit 23, and the output signal terminal of the inverter circuit 23 is connected to the input signal terminal of the inverter circuit 24. The output signal terminal of the inverter circuit 24 is connected to the first gate of each of the OR circuit 21 and the AND circuit 22,
The input terminal 13 is connected to each of the second gates.
The output signal terminal of the OR circuit 21 is connected to the gate electrode of the P-type MOSFET 19 in the second drive circuit 11, and
The output signal terminal of the D circuit 22 is connected to the gate electrode of the N-type MOSFET 20 in the second drive circuit 11.

When a low-potential signal is input to the input terminal 13, the N-type MOSFET 18 is immediately turned off (OFF), and the N-type MOSFET 20 is also immediately turned off through the AND circuit 22. Also, the P-type MOSF in the first drive circuit 10
The ET 16 is immediately turned on. However, the P-type MOSFET 19 in the second drive circuit 11 is connected to the inverter circuits 23 and 24 in which the signal at the input terminal 13 serves as a delay element.
Does not turn on until the output of the OR circuit 21 goes to a low potential through. Assuming that the threshold voltage of the P-type MOSFET is VTP, the P-type MOSFET 15 has a gate electrode and a drain electrode connected to each other, so that the potential of the drain electrode is at least a potential difference between the potential VDD of the source electrode and the potential of the threshold voltage VTP. Remains. Therefore P-type MOS
After the FET 16 is turned on, the potential of the output terminal 14 becomes (VDD)
-VTP), the P-type MOSFETs 15, 1
The ability to pass current from the + VDD power supply to the output terminal 14 through 6 is lost. On the other hand, inverter circuits 23 and 24
, The P-type MOSFET 19 in the second drive circuit 11 turns on next through the OR circuit 21,
The output terminal 14 reaches the level of + VDD. The above situation is illustrated in the waveform at the time of rising in FIG. When a high potential signal is input to the input terminal 13, a P-type M0SFET
16 turns off immediately, and the P-type MOSFET 19
It is turned off immediately through the circuit 21. The N-type MOSFET 18 in the first drive circuit 10 is immediately turned on, while the N-type MOSFET 20 in the second drive circuit 11 is connected to the inverter circuits 23 and 24 in which the signal at the input terminal 13 serves as a delay element. , And does not turn on until the output of the AND circuit 22 becomes high potential. Assuming that the threshold voltage of the N-type MOSFET is VTN, the N-type MOSFET 17 has a gate electrode and a drain electrode connected to each other, so that the potential of the drain electrode is at least as much as the threshold voltage VTN between the potential 0 (-VSS) of the source electrode. Only the potential difference remains. Therefore, when the potential of the output terminal 14 reaches VTN after the N-type MOSFET 18 is turned on, the N-type MOSFET 18
Output terminal 1 from power supply of 0 (-VSS) through 17 and 18
The ability to apply current to 4 is lost. On the other hand, the signal delayed through the inverter circuits 23 and 24 is output to the AND circuit 22.
Through the N-type MOSFET 2 in the second drive circuit 11
0 turns on next, and the output terminal 14 reaches the 0 level of -VSS. FIG. 2 shows the waveform at the time of the fall in FIG.

As described above, in the case of rising, the output potential first rises to (VDD-VTP) by the first drive circuit, and then reaches + VDD by the second drive circuit. After the output potential is first reduced to VTN by the circuit, the second drive circuit operates to reach -VSS (0 potential). Therefore, although the potential of the output terminal eventually swings between the power supplies, only the first drive circuit operates in the initial stage of the output change, and changes only during a time narrower than the power supply voltage. It is suppressed, overshoot and undershoot do not occur,
It can be seen that the output drive circuit has low noise.

Next, a description will be given of the power consumption due to charging and discharging when a capacitive load is applied to the output terminal.
Assuming that the frequency of the output signal is f, the power supply voltage is VDD, and the capacitance of the load is CL, the charge / discharge is repeated directly between the power supply voltages VDD as in the conventional circuit shown in FIG. Po becomes P0 = f.CL.VDD ² (101). On the other hand, at the time of rising as in the circuit of FIG. 1 according to the first embodiment of the present invention, first, the output terminal is set to (VDD-VTP).
Then, for the sake of simplicity, when V DD is set to VTN and then to VTN at the falling time, V TH = V TP = V
Assuming TN, the power consumption is f · CL · (VDD−VTH) ^{2 in} the first stage and f · CL · VTH ^{2 in} the second stage, so the total power consumption PN is PN = f · CL · (VDD− VTH) ² + f · CL · VTH ² (102) Therefore, the difference ΔP between the power consumption P0 of the conventional system and the current consumption PN of the system of the present invention is expressed by the equation (101) and the equation (1).
From equation (02), ΔP = P0−PN = f · CL · 2 (VDD−VTH) VTH (103) Normally, VDD> VTH and VTH> 0, so △ P
> 0, that is, P0> PN (104) Therefore, it can be seen from equation (104) that the circuit system of the present invention reduces the power consumption for charging and discharging the capacitive load as compared with the conventional circuit system.

Although the embodiment of the present invention has been described with reference to the circuit of FIG. 1, the present invention is not limited to the circuit of FIG. For example, since the inverter circuits 23 and 24 function as delay elements, they may be resistors, and any number of inverter circuits may perform the same function as long as the number is even.

The OR circuit 21 and the AND circuit 22 in the delay control circuit 12 for controlling the second drive circuit 11 have an odd number of inverter circuits serving as delay elements. MOSFET17,18 in the circuit
In the case where an inverter circuit for driving the above is provided, the logic circuit is changed to a corresponding one.

Each of the MOSFEs of the first and second drive circuits
The drive capability of T and the delay time of the delay element in the delay control circuit 12 are adjusted to optimal values according to the drive capability, slew rate, and allowable noise limit of the low noise output drive circuit of the present invention.

FIG. 3 is an expanded view of the method of supplying the output potential to three stages. In the rising stage, the first stage is (VDD−2VTP), the second stage is (VDD−VTP), and the third stage is (VDD−VTP). VDD. At the time of falling, 2 VTN is used in the first stage, VTN is used in the second stage, and 0 is used in the third stage. Three sets of drive circuits are prepared to further reduce noise and power consumption, and delay control is performed accordingly. The circuit has been changed.
Similarly, a circuit having four or more stages can be configured.

Although the above example shows a configuration in which noise is not generated on both the + VDD side and the -VSS side, when the noise on either side is not a problem, only one side is a countermeasure. Is also good.

[0016]

As described above, according to the present invention, when the output potential is switched, the first drive circuit that does not swing to the power supply voltage operates first, and then the second drive circuit changes the power supply potential to the power supply potential. Since a two-stage operation in which the output potential is achieved is performed, the transient current is suppressed to be low, and an overshoot or undershoot does not occur. Therefore, there is an effect that a low-noise output drive circuit having high drive capability is provided.

Further, since the first drive circuit and the second drive circuit having different output levels charge and discharge the load in two stages, there is an effect of reducing the charge and discharge power.

Further, heat generation is suppressed because power consumption is reduced,
In addition, there is an effect that a change in electrical characteristics can be prevented and quality assurance can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an output waveform diagram showing the operation of the circuit of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional output drive circuit.

5 is an output waveform diagram showing the operation of the circuit of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... 1st drive circuit 11 ... 2nd drive circuit 12 ... delay control circuit 13 ... input terminal 14 ... output terminal 15, 16, 19 ... P-type MOSFET 17, 18, 20 ... N-type MOSFET 23, 24 ... Inverter circuit 21 ... OR circuit 22 ... AND circuit

Claims (3)

(57) [Claims] A drive circuit for outputting a signal having an amplitude between a first potential and a second potential to a signal output point (14) based on an input signal input to a signal input point (13). The first potential and the second potential are connected to the signal input point and the signal output point, and correspond to a change in the input signal from a first logic level to a second logic level. A first drive circuit that outputs a third potential between the first and second logic levels, the first drive circuit being connected to the signal input point and corresponding to a change in the input signal from the first logic level to the second logic level. And outputs a first signal to a first signal line, and outputs a second signal to a second signal line in response to the input signal changing from a first logical level to a second logical level. Delay control circuit, a first power supply line for supplying the first potential, and a second power supply for supplying the second potential. A first power supply line and a second power supply line connected in series with the second power supply line; and a gate of the first transistor connected to a first signal line and a second signal line connected to the second signal line. A second drive circuit in which a gate of the transistor is connected to a second signal line, and a connection point between the first and second transistors is connected to a signal output point, respectively. The response of the second signal is the first signal
An output drive circuit configured to be output with a given time delay from the response of the signal. 2. The first driving circuit according to claim 1, wherein the first driving circuit includes a third transistor of a first conductivity type having a source terminal connected to the first power supply line, and a third transistor having a source terminal connected to the second power supply line. A fourth transistor of a second conductivity type; and fifth and sixth transistors of a complementary conductivity type connected between a drain terminal of the third transistor and a drain terminal of the fourth transistor. A gate terminal of the third transistor is connected to a drain terminal of the third transistor; a gate terminal of the fourth transistor is connected to a drain terminal of the fourth transistor; The source terminal of the third transistor is connected to the drain terminal of the third transistor, and the source terminal of the sixth transistor is connected to the transistor of the fourth transistor. The fifth transistor and the sixth transistor are connected to the signal input point, and the fifth and sixth transistors are connected to the signal output point. The output drive circuit according to claim 1, wherein: 3. When the input signal changes from a first logic level to a second logic level, the first transistor is turned off within less than the given time. The output drive circuit according to claim 1.