JPH05114852A - Low-noise output driving circuit - Google Patents

Abstract

PURPOSE:To provide the low-noise output driving circuit. CONSTITUTION:A 1st driving circuit 10 which has an MOSFET, which has its gate and drain connected to each other to decrease the threshold voltage, on a power source side and a 2nd driving circuit 11 of normal CMOS inverter constitution are prepared and a delay control circuit 12 performs control so that the 1st driving circuit 10 operates first and the 2nd driving circuit 11 operates next. In this constitution, the 1st driving circuit NO leaves a voltage drop as large as the threshold voltage, so the potential does not rise up to a power supply potential and then reaches the power supply potential by the 2nd driving circuit. This method suppresses an excessive transient current at the time of output variation and eliminates overshooting and undershooting. Consequently, the transient current is made small and a noise is reduced. Further, the output level varies in two stages, so the power consumption by the charging and discharging of a capacitive load is reducible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to noise reduction of an output drive circuit in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A complementary output drive circuit using a conventional insulated gate field effect transistor (hereinafter abbreviated as MOSFET) connects a source electrode of a P-type MOSFET to a positive power supply terminal + VDD as shown in FIG. The source electrode of the N-type MOSFET is connected to the negative power supply terminal -VSS, and the drain electrodes and the gate electrodes of the P-type and N-type MOSFETs are connected to each other.

[0003]

In the above-mentioned conventional circuit, the output potential swings from + VDD to -VSS to the full power source as shown in FIG. Since undershoot is caused, there is a problem that the driving capability is increased and the noise due to the transient current when the output potential changes becomes excessive and adversely affects other circuits.

Therefore, the present invention solves such a problem, and an object of the present invention is to provide an output drive circuit in which noise is less generated due to a transient current when the output potential changes.

[0005]

A low noise drive circuit according to the present invention comprises: a) a semiconductor integrated circuit using an insulated gate field effect transistor, and b) a source electrode connected to a positive power supply terminal and a gate electrode. A first P-type MOSFET in which drain electrodes are connected to each other and a source electrode in the first
Second P connected to the drain electrode of the P-type MOSFET of
-Type MOSFET, a first N-type MOSFET in which a source electrode is connected to a negative power supply terminal, and a gate electrode and a drain electrode are connected to each other, and a source electrode is connected to a drain electrode in the first N-type MOSFET 2 N-type MO
A first FET including an SFET and having gate electrodes of the second P-type MOSFET and the second N-type MOSFET connected to each other as input terminals, and drain electrodes thereof connected to each other as output terminals; A driving circuit and c) a third P-type MOSFE in which a source electrode is connected to a positive power supply terminal.
T and a third N in which the source electrode is connected to the negative power supply terminal
Type MOSFET, and the third P-type MOSF
ET and a second drive circuit that connects the respective drain electrodes of the third N-type MOSFETs to each other as an output terminal, d) a delay control circuit including a delay element and a signal control element, and e) the second The input terminal of the first drive circuit is connected to the input signal terminal of the delay control circuit, and the first output signal terminal and the second output signal terminal of the delay control circuit are the second output signal terminal.
Third P-type MOSFET and third N-type M of the driving circuit of
The gate electrodes of the OSFETs are respectively connected to the first
The output terminals of the drive circuit and the second drive circuit are connected to each other.

[0006]

According to the above configuration of the present invention, the N type M is provided on the + VDD side.
OSFET, first using P-type MOSFET on -VSS side
Since the output potential changes at first by the drive circuit of, the output potential does not swing to the full power supply potential at this initial stage, transient current when the output potential changes can be suppressed, and overshoot and undershoot. The output drive circuit has less noise.

[0007]

1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, a circuit surrounded by a broken line 10 is a first drive circuit, a circuit surrounded by a broken line 11 is a second drive circuit, and a circuit surrounded by a broken line 12 is a delay control circuit. In the first drive circuit 10, the P-type MOSFET 15
Has a source electrode connected to the positive power supply electrode + VDD, and a gate electrode and a drain electrode connected to each other. P
The source electrode of the MOSFET 16 is the P-type MOSFET.
It is connected to the drain electrode of T15. N-type MOSF
The source electrode of ET17 is connected to the negative power supply electrode -VSS, and the gate electrode and drain electrode are connected to each other. The source electrode of the N-type MOSFET 18 is the N-type M
It is connected to the drain electrode of the OSFET 17. The gate electrodes of the P-type MOSFET 16 and the N-type MOSFET 18 are connected to each other and to the input terminal 13, and their drain electrodes are connected to each other and to the output terminal 14. In the second drive circuit 11, the source electrode of the P-type MOSFET 19 is connected to + VDD, the source electrode of the N-type MOSFET 20 is connected to -VSS, and the P-type MOSFET 19 and the N-type MO are connected.
The drain electrodes of the SFET 18 are connected to each other and to the output terminal 14. The delay control circuit 12 is composed of two inverter circuits 23 and 24, which function as delay elements, an OR circuit 21 and an AND circuit 22. The input terminal 13 is connected to the input terminal of the inverter circuit 23, and the output signal terminal of the inverter circuit 23 is connected to the input signal terminal of the inverter circuit 24. The output signal terminal of the inverter circuit 25 is connected to the first gates of the OR circuit 21 and the AND circuit 22, respectively.
An input terminal 13 is connected to each second gate.
The output signal terminal of the OR circuit 21 is connected to the gate electrode of the P-type MOSFET 19 in the second drive circuit 11, and AN
The output signal terminal of the D circuit 22 is connected to the gate electrode of the N-type MOSFET 20 in the second drive circuit 11.

When a low potential signal is input to the input terminal 13, the N-type MOSFET 18 is immediately turned off (OFF), and the N-type MOSFET 20 is immediately turned off through the OR circuit 22. In addition, the P-type MOSFE in the first drive circuit 10
T16 turns on immediately (ON). However, the P-type MOSFET 19 in the second drive circuit 11 does not turn on until the output of the OR circuit 21 becomes a low potential via the inverter circuits 23 and 24 in which the signal at the input terminal 13 functions as a delay element. If the threshold voltage of the P-type MOSFET is VTP, the gate electrode and the drain electrode of the P-type MOSFET 15 are connected to each other. Therefore, the potential of the drain electrode differs from the potential VDD of the source electrode by a potential difference of at least the threshold voltage VTP. Remains. Therefore, P-type MOSF
After the ET16 is turned on, the potential of the output terminal 14 becomes (VDD-
When VTP) is reached, it is no longer P-type MOSFETs 15 and 16
There is no ability to pass current from the + VDD power supply to the output terminal 14 through. On the other hand, the signal delayed through the inverter circuits 23 and 24 passes through the OR circuit 21, the P-type MOSFET 19 in the second drive circuit 11 is turned on next, and the output terminal 14 reaches the level of + VDD. The above waveform is the waveform at the time of rising in FIG. When a high potential signal is input to the input terminal 13, the P-type M0SFET1
6 turns off immediately, and the P-type MOSFET 19 also turns off immediately through the OR circuit 21. In addition, the first drive circuit 1
The N-type MOSFET 0 in 0 immediately turns on 18, but the N-type MOSFET 20 in the second drive circuit 11 uses the inverter circuit 2 in which the signal at the input terminal 13 functions as a delay element.
It does not turn on until the output of the AND circuit 22 becomes a high potential via 3 and 24. If the threshold voltage of the N-type MOSFET is VTN, the gate electrode and the drain electrode of the N-type MOSFET 17 are connected to each other. Only the potential difference remains. Therefore, after the N-type MOSFET 18 turns on, the output terminal 1
When the potential of 4 reaches VTN, it is no longer N-type MOSFET1
Output terminal 14 from 0 (-VSS) power supply through 7 and 18.
It loses the ability to draw current into. On the other hand, the signal delayed after passing through the inverter circuits 23 and 24 passes through the AND circuit 22 and the N-type MOSFET 20 in the second drive circuit 11.
Next turns on, and the output terminal 14 reaches the 0 level of -VSS. The above waveform is the waveform at the time of falling in FIG.

As described above, in the case of rising, the first driving circuit first raises the output potential to (VDD-VTP), then the second driving circuit reaches + VDD, and in the case of falling, the first driving. The circuit first reduces the output potential to VTN, and then the second drive circuit operates to reach -VSS (0 potential). Therefore, the potential of the output terminal eventually swings between the power supplies, but at the initial stage of output change, only the first drive circuit operates and changes only within a narrower range than the power supply voltage, so the transient current is low. It is suppressed, overshoot and undershoot do not occur,
It can be seen that the output drive circuit has low noise.

The power consumption due to charging / discharging when a capacitive load is applied to the output terminal will be described below.
If the frequency of the output signal is f, the power supply voltage is VDD, and the capacitance of the load is CL, the power consumption at that time is repeated directly between the power supply voltages VDD as in the conventional circuit as shown in FIG. PO becomes ^{P0 = f · CL · VDD 2} (101). On the other hand, at the time of rising as in the circuit of FIG. 1 which is the first embodiment of the present invention, first, the output terminal is (VDD-VTP).
For the sake of simplicity, VTH = VTP = V for the following reason.
If TN, the power consumption is f · CL · (VDD-VTH) ^{2 in} the first stage and f · CL · VTH ^{2 in} the second stage, so the total power consumption PN is PN = f · CL · (VDD- VTH) ² + f · CL · VTH ² (102). Therefore, the difference ΔP between the power consumption P0 of the conventional method and the current consumption PN of the method of the present invention is expressed by equations (101) and (1).
From equation (02), ΔP = P0-PN = f.CL.2 (VDD-VTH) VTH (103). Normally VDD> VTH and VTH> 0, so ΔP
> 0, that is, P0> PN (104). Therefore, it can be seen from the equation (104) that the circuit system of the present invention has lower power consumption for charging and discharging the capacitive load than the conventional circuit system.

Although the embodiment of the present invention has been described with reference to the circuit of FIG. 1, the present invention is not limited to the circuit of FIG. For example, since the inverter circuits 23 and 24 function as delay elements, the inverter circuits 23 and 24 may be resistors, and the same number of inverter circuits may be used as long as the number is even.

Further, the OR circuit 21 and the AND circuit 22 in the delay control circuit 12 for controlling the second drive circuit 11 are also used when the number of stages of the inverter circuit which functions as a delay element is odd. MOSFET 17 and 18 in the circuit
When an inverter circuit for driving the above is provided, the logic circuit is changed accordingly.

Further, each MOSFE of the first and second drive circuits
The drive capability of T and the delay time of the delay element in the delay control circuit 12 are adjusted to optimum values according to the drive capability, the slew rate and the allowable noise limit as the low noise output drive circuit of the present invention.

FIG. 3 is a diagram in which the method of supplying the output potential is expanded to three stages. The first stage is (VDD-2VTP) at the time of rising, the second stage is (VDD-VTP), and the third stage is It is VDD. At the time of falling, 2 VTN at the first stage, VTN at the second stage, and 0 at the third stage, three sets of drive circuits are prepared to further reduce noise and power consumption, and delay control is performed accordingly. The circuit has been changed.
Similarly, a circuit having four or more stages can be configured.

In the above example, the noise is not generated on either the + VDD side or the -VSS side. However, if the noise on either side does not cause a problem, it is a circuit in which only one side is dealt with. Is also good.

[0016]

As described above, according to the present invention, when the output potential is switched, the first drive circuit that does not swing up to the power supply voltage operates first, and then the second drive circuit changes the power supply potential to the power supply potential. Since the two-stage operation of reaching the output potential is performed, the transient current can be suppressed to a low level, and neither overshoot nor undershoot occurs, so that there is an effect of providing an output drive circuit having high drive capability and low noise.

Further, since the load is charged / discharged in two stages by the first drive circuit and the second drive circuit having different output levels, there is an effect of reducing charge / discharge power.

Since the power consumption is reduced, heat generation can be suppressed,
In addition, it is possible to prevent changes in electrical characteristics and improve quality assurance.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an output waveform diagram showing the operation of the circuit of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional output drive circuit.

FIG. 5 is an output waveform diagram showing the operation of the circuit of FIG.

[Explanation of symbols]

 10 ... 1st drive circuit 11 ... 2nd drive circuit 12 ... Delay control circuit 13 ... Input terminal 14 ... Output terminal 15, 16, 19 ... P-type MOSFET 17, 18, 20 ... N-type MOSFET 23, 24 ... Inverter circuit 21 ... OR circuit 22 ... AND circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/003 Z 8941-5J

Claims (1)

[Claims] 1. A semiconductor integrated circuit using an insulated gate field effect transistor (hereinafter abbreviated as MOSFET), b) a source electrode connected to a positive power supply terminal, and a gate electrode and a drain electrode connected to each other. First P-type MOS
An FET, a second P-type MOSFET having a source electrode connected to the drain electrode of the first P-type MOSFET, a source electrode connected to a negative power supply terminal, and a gate electrode and a drain electrode connected to each other N-type MOSFET
And a second N-type MOSFET having a source electrode connected to the drain electrode of the first N-type MOSFET, and the second P-type MOSFET and the second N-type MOS.
A first drive circuit in which each gate electrode of the FET is connected to serve as an input terminal and each drain electrode is connected to serve as an output terminal; and c) A third P circuit in which a source electrode is connected to a positive power supply terminal. -Type MOSFET and a third N-type MOSFET in which a source electrode is connected to a negative power source terminal, and the third P-type MOSFET is provided.
Second drain of the third MOSFET and the third N-type MOSFET are connected to each other as an output terminal
D) a delay control circuit including a delay element and a signal control element, e) an input terminal of the first drive circuit is connected to an input signal terminal of the delay control circuit, and The first output signal terminal and the second output signal terminal are the third P-type MOSFET and the third N-type MOSFET of the second drive circuit.
A low-noise output drive circuit connected to respective gate electrodes of the first drive circuit and output terminals of the first drive circuit and the second drive circuit.