JPS6143799B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed MOS drive circuit implemented as an IC with a MOS structure.

In order to operate a charge-coupled device (hereinafter abbreviated as CCD), a drive pulse or DC bias is required to drive the transfer electrode of the MOS capacitor, and a drive pulse or DC bias is required to drive the transfer electrode of the MOS capacitor. Control pulses, control pulses for detection and amplification in the output section, etc. are required. In particular, as pulses to be supplied to the input/output (I/O) section of the latter, high-speed, high-voltage switching with a sample rate of 10 MHz or higher is required in video band CCDs, regardless of whether or not a multi-transfer channel method is adopted. A pulse is required. Such a pulse has a rise/fall time of 10 nsec or less and a short duty cycle. (50% or less) is the norm. Since the area of the electrode portion receiving the I/O control pulses is small, the load capacitance of the drive circuit on the pulse supply side is not very large, and is several pF including the wiring capacitance of the drive circuit. However, in order to ensure that the CCD has a wide dynamic range and good linearity, the pulse amplitude of these I/O sections is not limited to the TTL level, but usually requires a peak level of 10 V or more. Moreover, since it requires high-speed switching pulses, it is almost impossible to implement with a conventional enhancement type MOS structure. In particular, such drive circuits are designed to eliminate pulse ringing and harmonic radiation outside the clock frequency, that is, crosstalk.
It is considered preferable to implement the IC on the same chip as the CCD. This integration into ICs also makes it possible to provide low-cost, easy-to-use devices. Since CCDs are essentially MOS structures,
When implementing an IC on the chip, the desired circuit must have a MOS configuration that provides high-speed switching characteristics. Moreover, when implementing an IC, the input of the pulse drive circuit must be TTL compatible. This is an important condition for ease of use of the device. It is desirable that the delay time between this TTL level pulse and its output pulse be as small as possible in order to facilitate phase alignment of the pulse system required for such a high-speed CCD. Conventionally, an ED MOS structure as shown in FIG. 1 has been considered as a circuit configuration that satisfies these conditions. The circuit shown in the figure is an example of a high-speed drive circuit that performs switching at the operation timing shown in FIG. 2 and can supply an output pulse V ₀ with a duty of 25%. The operation of this circuit will be explained below. The unit element consisting of MOS transistors M1 and M2 is a one-stage ED inverter circuit, which inverts the phase of the TTL level input pulse 11 and generates a pulse with an amplitude equal to the power supply V _GG supplied to the drain of the depletion type MOS transistor M1. Amplify to N1. MOS transistor _M3 , _M4
The unit element consisting of is a buffer circuit for controlling the pull-up terminal potential of a boot circuit to be described later. The boot circuit for supplying charge/discharge current to the load capacitance C _L includes MOS transistors M ₅ , M ₆ , M ₇
and boot capacitance C _b . This boot circuit performs NOR type logic operation and maintains V ₀ at a low level (OV) when either TTL level input pulse I1 or I2 is at a high level (on), and both are at a low level. (off)
The charging current supplied from _M5 charges the load C _L to a high level potential. Now, since the clock frequency of the input pulse I2 is set to twice that of the input pulse I1, even when the input pulse I2 is on, there is a period T1 in which the input pulse I1 is off, and during this period, the MOS transistor M4 is cut off. do. Therefore, when the drain part _V0 of the MOS transistor M7 turned on by the high level input pulse I2 is at a low level, the phase inverted amplified pulse N1 (high level) of the input pulse I1 turns on the depletion type MOS transistor M3. The potential of the output terminal N2 of the buffer circuit is increased as shown by the solid line 21 in FIG. Since this transistor M3 is a depletion type, it is always turned on during the period when it is supplied with the gate voltage N1 (equal to V _GG ) which is higher than the threshold voltage (〓-several volts), and reaches a potential of approximately V _GG at time _t1. reach The potential of N2 at this time constitutes a buffer circuit.
Although it is determined by the driving ability of the MOS transistor M3, it is usually preferable to design the constant so that it is approximately V _GG in order not to reduce the driving ability of the boot circuit. Next, when the input pulse I2 turns off, the MOS transistor M7 turns off, so during the period _T2 , the voltage between the gate and source of the depletion MOS transistor M5, that is, the charging voltage between the terminals of the boot capacitor C _b (approximately V High transconductance gm obtained by (equal to _GG )
applies a large load charging current to the MOS transistor M5, attempting to raise the potential of V ₀ to the vicinity of V _DD of the power supply. However, in the conventional configuration, the potential of N2, which is raised as the potential of V ₀ rises, is V
As soon as the voltage exceeds _GG , the depletion MOS transistor M3 turns on, and a leakage current in the opposite direction begins to flow from the N2 terminal to the power supply _VGG . This phenomenon is caused by M3 being a depletion type.
This occurs because it is a MOS transistor.
In the period _T2 when the potentials of terminal N1 and _VGG are equal,
Just by applying a slight voltage between the drain (N2) and the source (V _GG ) of the MOS transistor M3, the MOS transistor M3, which has a low threshold voltage (several volts), is turned on. Therefore, the voltage between the terminals of the boot capacitor, which had been holding a charging voltage of about V _GG at time t ₁ , is discharged and slightly increased as shown by the solid line 22 due to this reverse leakage current. If the discharge speed due to the leakage current of the MOS transistor M3 is faster than the load charging speed of the MOS transistor M5, the voltage at the N2 terminal will not rise at all. Due to the occurrence of such a leakage phenomenon, the drain-source voltage of the MOS transistor M5 is attenuated, resulting in a problem that the gm of the MOS transistor M5 during dynamic operation is reduced. Therefore, the output terminal
The potential of V ₀ also showed a gradual rising characteristic as shown by the solid line 24, and due to the decrease in charging speed due to the decrease in gm, the transition to the off state occurred before the potential rose to the potential of the power supply V _DD . Such pulses are not useful for I/O control of high-speed CCDs. Furthermore, since a sufficient voltage amplitude cannot be obtained, not only the operational dynamic range of the CCD is reduced, but also the linearity is degraded because the signal level that can be input is reduced.

The object of the present invention is to eliminate such drawbacks and to provide a high-speed
Our goal is to provide MOS drive circuits.

According to the present invention, an IC is formed on a semiconductor substrate.
This is a drive circuit with a MOS structure, and an ED inverter circuit that inverts and amplifies the second input pulse.
The EDNOR gate circuit controlled by the output pulse of the ED inverter circuit and the first input pulse, and this
an ED buffer circuit comprising a load MOS transistor supplied with the output pulse of the EDNOR gate circuit, a drive MOS transistor supplied with the first input pulse; The NOR boot circuit is controlled by two input pulses, and the load-side MOS transistors of the ED inverter circuit, EDNOR gate circuit, and ED buffer circuit are connected to the first power supply, and the NOR boot circuit boots. said circuit connected to the second or first power supply and providing the necessary pulses to carry out the operation;
A high-speed MOS drive circuit is obtained, characterized in that the NOR boot circuit supplies an output pulse whose peak value is the voltage value of the second or first power supply.

Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 3 shows an embodiment of the high speed MOS drive circuit of the present invention. In this figure, the same symbols as those shown in FIG. 1 represent the same components. The operation of the circuit of the present invention is similar to the principle of operation of the high-speed drive circuit shown in FIG. 1, except for some parts. The difference from the conventional circuit configuration of the present invention is that instead of an inverter circuit that supplies control pulses for the buffer circuit,
A NOR gate is provided, and this NOR gate is controlled by an E/D type inverter circuit that inverts and amplifies the second input pulse. By adopting such a configuration, during the period _T2 (see Figure 2) in which the potential of the output terminal _V0 rises, the voltage across the boot capacitor _Cb (approximately equal to _VGG ) that was charged immediately before was maintained. The potential of the output terminal N2 of the buffer circuit can be increased in this state. That is, the second input pulse I2 is inverted and amplified by an inverter circuit composed of a depletion MOS transistor M8 and an enhancement MOS transistor M9, and becomes a pulse N3. This N3 pulse is applied to the depletion MOS transistor M1 and the two enhancement MOS transistors M10,
Drive of NOR gate circuit composed of M2 and
Supplied to the gate of MOS transistor M10,
Control this NOR gate. FIG. 4 shows the operation timing of the circuit shown in this embodiment, and the following explanation will be given using this diagram. During the period _T1 when the N3 pulse is off, the other input pulse I1 of the NOR gate is also off, so
The output N1 of the NOR gate is maintained at a high level potential (on). Next, in period T ₂ , the second
State transition of input pulse I2 (from on to off)
As the output N3 of the inverter circuit turns on, the depletion MOS transistor M, which is the power supply side MOS transistor of the buffer circuit,
A low level pulse (OV) is supplied to the gate of 3. This M3 is composed of a depletion type MOS transistor. However, the gate potential N1 is much higher than its threshold voltage (〓-several V) compared to the potential of the output N2 of the buffer circuit, which rose to the power supply voltage of about V _GG at the _end of the period t 1 of T1. Since it is set to a low potential, the M3 MOS transistor moves to a cut-off state. At this time, since the MOS transistor M4, which is a component of the buffer circuit, is also in a cut-off state, the terminal N2 is placed in a floating state. Therefore, input pulses I1 and I
In the period T 2 when both 2 and ₂ are in the off state, in the period T1
The voltage of approximately V _GG charged in the boot capacitor C _b forming the NOR type boot circuit is maintained as it is.
Also, in this period of T ₂ , the enhancement
Since the input pulses of I1 and I2 supplied to the gates of MOS transistors M6 and M7 are both turned off, the drive side MOS transistor M of the boot circuit that directly drives the load capacitance C _L of the output section
6, M7 is in the cut-off state. On the other hand, the load side MOS transistor M5 of the boot circuit has a negative number V.
It is a depletion MOS transistor with a threshold voltage of
Since the voltage of _GG is applied, it is turned on and a charging current is supplied from the power supply V _DD to the load C _L to increase the voltage of the output terminal V ₀ as shown by the solid line 25 and charge it to the potential of V _DD . do. In this transition state (period _T2 ), the potential of the output N2 of the buffer circuit becomes a value equal to or higher than _VGG , but the gate potential of the depletion MOS transistor M3 is low and M3 is always kept in the cut-off state.
No large leakage current from N2 to V _GG occurs. Even if there is leakage, it is a reverse junction current between the N ⁺ impurity diffusion layer that forms the N2 terminal and the P-type semiconductor substrate, but this current value is usually very small on the order of nA, so it is only a few hundred μA. It can be ignored compared to the circuit current of ~ several mA. In this way, since there is no leakage of the charging voltage of the boot capacitor, the potential of N2 becomes V _GG + V _DD as shown by the solid line 23 during the period T ₂ .
reaches a peak potential close to . The potential of the output terminal _V0 is increased rapidly due to the large gm of the MOS transistor M5 obtained by the leak-free charging voltage of this boot capacitor. In other words, a stable, high-speed, high-amplitude pulse can be obtained as the output pulse V ₀ , which is different from that seen in conventional drive circuits.
This eliminates the problems of CCD dynamics and low linearity.

The circuit configuration shown in this example is a typical E/
Prototypes can be manufactured using the DMOS process. That is, MOS transistors M1, M3, M5, M8 are P or A _s
This is a depletion MOS transistor in which the threshold voltage V _T is controlled to a potential of a negative number V by implanting impurity ions such as ions into the channel portion of the substrate surface. In addition, MOS transistors M2, M4,
M6, M7, M9, and M10 are enhancement MOS transistors in which impurity ions such as boron are implanted into the substrate surface to obtain a V _T of approximately 1V. The above-mentioned high-speed switching operation can be obtained by using an E/DMOS configuration having such a V _T . In particular, in a circuit configured with a depletion MOS transistor as the load side MOS transistor, the load charging current at startup is E-
Since it is larger than the MOS configuration, the delay time of unit elements such as inverters is short. Therefore, in a cascade circuit of unit elements with a small number of stages as shown in this embodiment, the input TTL level pulses I1 and I2
The propagation delay between the output pulse V 0 and the output pulse V ₀ becomes smaller. As a result, when used as a pulse drive circuit for I/O control of a CCD or the like, it becomes possible to easily set an appropriate phase relationship with pulses for driving transfer electrodes and other I/O pulses. This advantage is particularly important for CCDs that use high-speed pulses of 10MHz or higher, and by appropriately matching the pulse phase,
This makes it possible to make full use of the inherent characteristics of CCDs. Furthermore, even if the circuit of this embodiment is implemented as an IC, the occupied area will only increase so much, and even if it is integrated with other circuits or systems on-chip, higher density will not be prevented. In this embodiment, an example in which the power supplies are divided into two power supplies, V _GG and V _DD, has been explained, but it is clear from the above description that it is also possible to use a common power supply. Furthermore, in order to reduce power consumption, it is also possible to supply power by dividing the unit into an appropriate combination of several unit elements.

As is clear from the above explanation, according to the present invention, a high-speed
A MOS drive circuit is obtained. Since this circuit can supply high-speed, high-amplitude pulses and has a small delay time between input and output pulses, it is particularly useful as a drive circuit for supplying high-speed pulses for I/O control of CCDs. Furthermore, the present invention can be prototyped using a normal E/DMOS process.
Since it has a MOS structure, it can be easily incorporated into the CCD process and turned into an on-chip IC. In addition, the drive circuit of the present invention can be used as a RAM with a MOS structure,
If applied to LSI such as ROM or random logic, high-speed I/O operations can be achieved. Incorporating an IC on the same chip as these LSIs is
It is as easy as with CCD.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of a conventional MOS drive circuit, Fig. 2 is a diagram showing the operation timing of the MOS drive circuit, and Fig. 3 is a diagram showing the high-speed MOS drive circuit of the present invention.
FIG. 4 is a diagram showing an embodiment of the drive circuit, and FIG. 4 is a diagram showing the operation timing of this high-speed MOS drive circuit. In the figure, M1, M2, M3, M
4, M5, M6, M7, M8, M9, M10 are
MOS transistors, I1 and I2 are input pulses,
C _b is the boot capacitance, N1, N2, N3 are terminal 2
1, 22, 23, 24, and 25 indicate pulse waveforms.

Claims (1)

[Claims] 1. A drive circuit with a MOS structure integrated on a semiconductor substrate, which is controlled by an ED inverter circuit that inverts and amplifies the second input pulse, and the output pulse of this ED inverter circuit and the first input pulse.
an ED buffer circuit consisting of an EDNOR gate circuit, a load MOS transistor supplied with the output pulse of this EDNOR gate circuit, a drive MOS transistor supplied with the first input pulse, and the first input pulse and its double. and a NOR boot circuit controlled by the second input pulse having a clock frequency of A boot circuit of the NOR supplies the necessary pulses to perform a boot operation, and the boot circuit of the NOR connected to the second or first power supply adjusts the voltage value of the second or first power supply to a peak value. A high-speed MOS drive circuit characterized by supplying output pulses that