JPH01240013A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce noise generated in a power source line by composing a time constant circuit of a resistance element and a capacitor provided at the drains of an N channel MOSFET and a P channel MOSFET which are a CMOS inverter constitution to form the gate driving voltage of an output MOSFET, respectively. CONSTITUTION:A CMOS inverter circuit, which consists of an N channel MOSFET Q1 and a P channel MOSFET Q2, constitutes a driving circuit. That is, the inverter circuits Q1 and Q2 receive a signal Vi formed by a appropriate internal circuit, and form a driving signal Vo to be supplied to the gates of outputs MOSFET Q3 and Q4. An output circuit consists of a CMOS inverter circuit which consists of the P channel MOSFET Q3 and the N channel MOSFET Q4. A drain commonly connected to the outputs MOSFET Q3 and Q4 is connected to an output terminal OUT. A capacitive load CL and the like to be driven are connected to the output terminal OUT.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, such as a MOS
The present invention relates to a technique that is effective for use in a semiconductor integrated circuit device equipped with an output circuit composed of FETs (insulated gate field effect transistors).

[Conventional technology]

In the output circuit formed in a semiconductor integrated circuit device,
It is necessary to be able to drive a relatively large load capacitance (stray capacitance), which consists of stray capacitance existing on a mounting board such as a printed wiring board coupled to the output terminal (external terminal), and the input capacitance of a signal input device. It is said that Therefore,
The output MOSFET allows a relatively large current to flow through the power supply line and the circuit ground line to charge up or discharge the load capacitance. The power supply voltage line in the semiconductor integrated circuit and the circuit ground line each have non-negligible resistance and inductance components, so the above output MO
When the SFET is activated and charges up or discharges the load capacitance, relatively large noise is generated in each case. Therefore, it has been proposed to provide a mirror capacitor between the input and output of the output inverter circuit to moderate the change in the output signal (for example, in Japanese Patent Laid-Open No.
(Refer to Publication No.-62725).

[Problem to be solved by the invention]

However, when adding such mirror capacitance,
For example, just forming an MO3 capacitor of about 0.4 pF requires an area as large as about 115 times the area occupied by the output circuit. In semiconductor integrated circuit devices such as gate arrays,
In order to enhance circuit functions, it is necessary to incorporate a large number of gates and to have a correspondingly large number of input/output functions. For this reason, the area occupied by the output circuit is also small (needing to be small), so it is not practical to use the Miller capacitance described above.When using a Miller capacitance, a special protection circuit against electrostatic damage is required. Furthermore, when a 0MO3 (complementary MO3) circuit is used as an output circuit, changes in the input signal Vin are suppressed by the Miller capacitance, so that N-channel MOSFET and P-channel MOSFET
The period during which ET and ET are simultaneously turned on is made relatively long. This causes a large through current to flow through both MOSFETs, increasing current consumption and also causing noise generation.

An object of the present invention is to provide a semiconductor integrated circuit device including an output circuit that reduces noise generated in a power supply line.

Another object of the present invention is to reduce the through-1111 current while
An object of the present invention is to provide a semiconductor integrated circuit device equipped with an output circuit that achieves high speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a time constant circuit is provided at the gate of the output MOS FET.

[For production]

According to the above-mentioned means, the output M OS is
Since the input signal transmitted to the gate of the FET can be slowly changed, noise generation can be suppressed.

[Embodiment 1] FIG. 1 shows a circuit diagram of a basic embodiment of an output circuit according to the present invention. Each of the circuit elements shown in the figure is formed on a single semiconductor substrate, such as pure crystalline silicon, by a known CMO3 integrated circuit manufacturing technique.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MO
SFET is made of polysilicon formed through a source region, a drain region, and a thin gate insulator on the semiconductor substrate surface between the source region and the drain region. It consists of a gate electrode that looks like this. The P-channel MOS FET is formed in an N-type trench region formed on the surface of the semiconductor substrate.

As a result, the 5-pi base forms a common substrate gate for a plurality of N-channel MOS FETs formed thereon. The N-type well region constitutes the substrate gate of the P-channel MOS FET formed thereon. The substrate gate of the P-channel MOS FET, that is, the N-type transistor region, is supplied with the power supply voltage VDD shown in FIG.

N-channel MOSFETQI and P-channel MOSF
The 0MO3-f inverter circuit consisting of ETQ2 constitutes a drive circuit. That is, this inverter circuit (Ql, Q
2) receives a signal Vi formed by an appropriate internal circuit (not shown) and outputs an output MOSFET as described below.
A drive signal vO to be supplied to the gates of Q3 and Q4 is formed. If the drive voltage Vo formed by the inverter circuit (Ql, Q2) is left as it is, the rise and fall of the signal will be steep, and the switching operation of the output MOS FET will be accelerated (this will cause the noise described above to occur). Therefore, the driving j signal Vo is connected to the resistor R1.
It is converted into a drive signal VD through a time constant circuit consisting of a capacitor C1 and a capacitor C1. Here, the capacitor C1 has an output M
The gate capacitance of OSFETQ3 and C4 may be used.

The output circuit consists of a CMOS inverter circuit consisting of a P-channel MOSFETQ3 and an N-channel MOSFETQ4. The drains of the output MO3FE'T'Q3 and C4, which are connected together by 11M, are connected to the output terminal OUT. The capacitive load CL to be driven as described above is connected to the output terminal OUT.

In the figure, in order to facilitate understanding of the present invention, "power supply terminal" is shown. . There is an inductance Ll and a distributed resistance R2 formed by wire bonding, etc., and a connection between the ground terminal GND of the circuit and the internal ground line to which the source of the output MOSFET Q4 is connected. Similarly, inductance L2 and distributed resistance R3 due to wire bonding or the like are also shown in between.

FIG. 2 shows a waveform diagram for explaining the operation of the embodiment circuit shown in FIG. 1.

In response to changes in the input signal Vi, the drive signal Vo formed by the drive inverter circuit (Ql and C2) has a waveform whose phase is inverted. Since the rise and fall of this drive signal Vo are steep, if this is directly transmitted to the gates of the output M'OS FET Q3 and C4, the drive signal Vo will be (2) The P-channel MOSFET Q3 is suddenly switched to the on state in response to the fall of the low level from the high level of 0.

As a result, the charge-up current ioI+ of the load CL changes sharply and becomes a current having a large peak value. Similarly, the N-channel MOSFET Q4 is suddenly switched to the on state in response to the rise of the drive signal 0 from the low level to the high level.

Therefore, the discharge current ia++ of the load CL also has a large peak value that changes rapidly. When such currents io+1 and iGo flow in the power supply, large noise is generated in the power supply voltage VDD and the ground potential VGD due to the parasitic inductance components L1 and R2 and resistance components R2 and R3 that exist there.

On the other hand, in this embodiment, the resistor R1 and the capacitor C
1, the drive signal VD that is actually supplied to the gates of the output MO5FETs Q3 and C4 has a waveform whose fall and rise are gentler than the drive signal ①0. becomes. In other words, the signal VD is the reciprocal of the time constant 01·R1 of the time constant circuit (R1°C1) with respect to the signal vO, 1/(C1·
R1) The current i6I has the following rate of change, and therefore has a gradual change and a small peak value, as shown by the solid line in the figure, although it differs depending on the setting of the above-mentioned time constant.
, and it+o will flow. Accordingly, noise generated in internal power supply voltage VDD and ground potential VCD can be reduced. By the way, the output M
The gate length of OSFETQ3 and C4 is about 3 μm and the gate width is about 500pm, and the gate capacitance of MOSFETQ3 and C4 is used as a capacitor CI that constitutes a time constant circuit, and MOSFETQI and C2 are used as a drive circuit.
If it has sufficient driving ability and high speed, the resistor R1
When set to 400Ω, when the load CL is 100pF, the delay time increases by a maximum of 2ns, and the noise on the power supply voltage VDD side can be halved and the noise on the ground potential VGD can be reduced to less than 1/3. It was done.

In this configuration, compared to the configuration using the Miller integration circuit as described above, the external terminal OUT has an output MOS
Since the drains of FETQ3 and C4 are only connected, a special electrostatic breakdown prevention circuit is not required by utilizing the PN junction between each drain region and the substrate or well region.

[Embodiment 2] FIG. 3 shows a circuit diagram of another embodiment of the output circuit according to the present invention.

In this embodiment, the output circuit is configured to have tristate output functionality, including an output high impedance state. Therefore, CMOS inverter circuits forming drive circuits are provided for the P-channel MOSFET Q3 that forms a high-level output signal and the N-channel MOSFET Q4 that forms a low-level output signal.

The MOSFETs QI and Q2 as shown in FIG.
Forms the drive voltage of channel output MO5FETQ3,
MOSFETs QI' and Q2° similar to those described above are arranged to form a driving voltage for N-channel output MOSFET Q4. Input signal v of each inverter circuit above
If MOSFET 1 is set to low level and input signal v2 is set to high level, both output MOSFETs Q3 and Q4 can be turned off, so that an output high impedance state can be created.

In this case, in order to optimally set the switching from the off state to the on state and the switching from the on state to the off state of the output MOSFETQ3, the drive MOSFETQ
1 and Q2 have drain resistors R11 and R12, respectively.
A capacitor C1 constituting a time constant circuit is connected to both connection points.

The cono capacitor C1 may utilize the gate capacitance of MOSFET Q3 (7).

Similarly, in order to optimally set the switching from the off state to the on state and the switching from the on state to the off state of the output MOSFET Q4, the drive MOSFET QI'
and Q2' are provided with drain resistors R21 and R22, respectively, and a capacitor C2 constituting a time constant circuit is connected to both connection points. This capacitor C2 is a MOSFE
The gate capacitance of TQ4 may also be used.

In this embodiment, in order to reduce the noise generated in the power supply voltage VDD, the resistance value of the resistor R12 is set large so that the switching from the off state to the on state of the output MOSFET Q3 is delayed, and the current flows between the output MOSFETs Q3 and Q4. In order to reduce the through current, the resistance value of the resistor R11 is set to be small (or may be deleted). Similarly, in order to reduce the noise generated at the ground potential VGD of the circuit, the resistor R2 that forms the drive voltage of the output MOSFET Q4 is
1 and R22, similarly, the resistance value of the resistor R21 is set to be relatively large, and the resistance value of the resistor R22 is set to be small (or may be deleted).

For example, when switching the output signal from low level to high level, the output MOSFET Q4, which is in the on state, is quickly turned off to prevent the generation of through current, and the output MOSFET
By slowing down the transition of OS FETQ 3 to the on state, it is possible to prevent the generation of noise as described above. Conversely, when switching the output signal from high level to low level, the output MOSFET Q3, which is in the on state, is quickly turned off to prevent the generation of through current, and the output MOSFET Q3 is switched off.
By slowing down the transition of ETQ4 to the on state, it is possible to prevent the generation of noise as described above.

MOS by reducing the resistance values of the resistors R12 and R22.
The configuration in which FETs Q3 and Q4 are respectively switched from the on state to the off state at high speed can also quickly create an output high impedance state. In addition, P channel 7/L, MOSFETQI, which constitutes the drive circuit.
(Ql') and N channel 7L, MOSFETQ2
The configuration in which a resistor is inserted into the drain of (Q2'') is
It is also possible to prevent the generation of through current in the drive circuit itself.

[Embodiment 3] FIG. 3 shows a circuit diagram of yet another embodiment of the output circuit according to the present invention.

In this embodiment, a resistor R is provided between the output MOSFETs Q3 and Q4, and this resistor R is provided with a tap as described later to function as a variable resistor. That is, the drain of P-channel MOS FETQ 1 constituting the drive circuit is connected to tap T1, and the drain of P-channel MOS
The drain of FETQ2 is connected to tap T2.

In this configuration, when viewed from tap T1, the MOS
The resistance value to the gate of FETQ3 is small, and the MOSF
The resistance value to the gate of ETQ4 increases. Therefore, MOSFET QI is turned on and tap T1
When changes from low level to high level, MOSFE
The rise of the gate voltage of TQ4 becomes gradual, and the MO
The rise of the gate voltage of SFETQ3 becomes faster. This makes it possible to prevent the generation of through current and noise when the output signal changes from high level to low level. Conversely, when viewed from tap T2, MOSFETQ
The resistance value for the gate of MOSFETQ3 is small,
The resistance value to the gate becomes large. Therefore, M
When OSFETQ2 turns on and tap T2 changes from high level to low level, the fall of the gate voltage of MOSFETQ3 becomes gradual, and the MOSFET
The fall of the gate voltage of Q4 becomes faster. Thereby, when the output signal changes from low level to high level, generation of through current and noise can be prevented.

The above selection or change of taps T1 and T2 may involve changing the pattern of one or more layers, mechanically, thermally destroying the completed wiring layer after manufacturing, or cutting by chemical methods. It will be done. When such a tapped resistor is used, it is suitable for a developed product of an output circuit manufactured on a trial basis.

FIG. 5 shows a modification of the resistor R. In this modification, two resistors ROI and RO2 are provided in parallel between output MOSFETs Q3 and Q4, and a resistor R
A tap T1 coupled to the drain of the drive MOSFET Q1 is provided on OI, and a tap T1 coupled to the drain of the drive MOSFET Q1 is provided on the other resistor RO2.
A tap T2 is provided which is coupled to the drain of Q2. Further, each of the resistors ROI and RO2 is provided with a wiring (tap) for adjusting the resistance value, and by selectively disconnecting the wiring, the resistance value can be adjusted as described above.

In this configuration as well, as in the circuit shown in FIG. 4, it is possible to prevent the generation of through current and reduce noise when switching output signals.

The effects obtained from the above examples are as follows. That is, (1) By providing a time constant circuit at the gate of the output MOSFET, changes in the input signal transmitted to the gate of the output MOSFET can be made gradual, which has the effect of suppressing noise generation. .

(2) As a time constant circuit provided at the gate of the output MOS FET, it slows down the change in the drive signal that turns the output MOS FET from the off state to the on state, and slows down the change in the drive signal that turns the output MOS FET from the on state to the off state. By adopting a configuration that speeds up the process, it is possible to suppress the generation of noise and also to prevent the generation of through current.

(3) P channel M for driving as the above time constant circuit
By adopting a configuration in which resistors are provided at the drains of the OS FET and N-channel MOSFET, it is possible to prevent the generation of through current and noise in the output circuit, and also to prevent through current in the drive circuit itself. is obtained.

(4) Due to (1) or 3) above, compared to the conventional technology that uses a Miller integrating circuit, it is possible to achieve higher integration and eliminate the need for a special electrostatic protection circuit. It will be done.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the output circuit is N
It may be a quasi-complementary push-pull circuit using channel MOSFETs, or it may be of an oven drain output type.

The resistive element and the capacitor may be made of any material, structure, and shape that can be included in a semiconductor integrated circuit device. For example, the resistance element can be made of an impurity diffusion layer, polycrystalline silicon, a silicon-metal compound, metal, or the like.

This invention can be widely used in semiconductor integrated circuit devices including custom LSIs (Large Scale Integrated Circuits) such as gate arrays and standard cell type circuits, as well as various semiconductor memory devices and output circuits such as microprocessors and nosers. .

(Effects of the Invention) A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by providing a time constant circuit at the gate of the output MOS FET, the input signal transmitted to the gate of the output 10SFET can be gradually changed, so that the generation of noise can be suppressed. In this case, as a time constant circuit, it slows down the change in the drive signal that turns the corresponding output MOS FET from the off state to the on state,
By adopting a configuration that speeds up the change in the drive signal from the on state to the off state, it is possible to suppress the generation of noise and also prevent the generation of through current.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the output circuit according to the present invention, FIG. 2 is a waveform diagram for explaining an example of its operation, and FIG. 3 is a circuit diagram showing an example of the output circuit according to the present invention. FIG. 4 is a circuit diagram showing still another embodiment of the output circuit according to the present invention; FIG. 5 is a modification of the embodiment circuit shown in FIG. 4. It is a circuit diagram. Q1~Q4, Qlo, Q2°...MOSFET. R, R1-R3, R11-R22, ROI, RO2...
Resistance, C1, C2...Capacitor, CL...Load capacitance,
LL, I, 2... Inductance Fig. 1 Fig. 2 Fig. 3 Fig. 4

Claims (1)

[Claims] 1. Output MOSFET whose gate is provided with a time constant circuit
A semiconductor integrated circuit device comprising: 2. A patent characterized in that the above-mentioned time constant circuit is composed of a resistive element and a capacitor respectively provided at the drains of an N-channel MOSFET and a P-channel MOSFET of a CMOS inverter configuration, which form the gate drive voltage of the output MOSFET. A semiconductor integrated circuit device according to claim 1. 3. The above output MOSFET is an N-channel MOSFET.
3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device constitutes a CMOS circuit consisting of T and P channel MOSFETs.