JPS6380620A - Output circuit - Google Patents

Abstract

PURPOSE:To preclude a transient phenomenon and the generation of a through current by delaying the gate inputs of CMOS inverters by the resistance of polysilicon wiring successively and connecting MOS transistors(TR) for off control between the gates of respective TRs and a power source. CONSTITUTION:The gate inputs of the CMOS inverters P1.N1-P3.N3 of respective stages are delayed in order by resistance components r1.r1'-r3.r3' of the polysilicon wiring to charge and discharge a load capacitor slowly. Consequently, the TRS of the respective stages turn on at the same time and the transient phenomenon and source voltage variation in switch operation are suppressed. Further, the MOS TRs N5-N7 and P5-P7 for accelerating the off operation of TRs which are turned off among the TRs of the COMS inverters are provided, so one TR is turned off earlier than any other TRs, so no through current flows and the source voltage never varies.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an output circuit of a semiconductor integrated circuit, and in particular, to an output circuit of a plurality of 0MO8 (complementary insulated gate type) inverters. Regarding commonly connected output circuits.

(Prior Art) This type of conventional output circuit has a circuit connection as shown in FIG. 3(a) and a pattern arrangement as shown in FIG. 3(b). That is, Pz, P, r, and PJ are nine P-channel MOS transistors whose sources S are connected to the VDD power supply line 31, respectively.F), NJ.

N2. The source S of each Ns is the ground (GND) line 32
The drains D of the transistors P1 to P3 and N1 to N3 are commonly connected to one output pad 35 via metal wiring (usually aluminum) 33 and 34. has been done. Then, the P channel transistors PJ, Pj, Pj and the N channel transistors N1. Each gate wiring Nz, Ns (made of polysilicon, same as the gate electrode) 36 is commonly connected to one signal power node IN via metal wiring M (usually aluminum>syt. In other words, P
Channel transistor P1゜PJ, PJ and N-channel transistor NZ.

Each corresponding set of Nx and Ns forms a CMOS inverter, and the CMOS inverters of each set are connected in parallel. In other words, 1+7) CMOS inverters are divided into multiple sets of CMOS inverters.

Note that 38 is the P-channel transistor P1°Par.
, Ps are arranged and insulated from each other in an N type substrate region, a source Sm region and a VDD power line 3.
The contact portion between the metal wiring 33 and the drain D region 1 and the drain D region is indicated by an X mark in the figure. Similarly, 39 is a P-type substrate region in which the N-channel transistors NJ, NJ, NJ are arranged and insulated from each other, and includes a source S region, a ground line 32, a drain D region, and a metal wiring 34. The contact portion with is indicated by an x in the figure.

According to the above output circuit, since the gates of the plurality of CMOS inverters are commonly connected to the metal wiring 37, the input signal is transmitted from the first stage inverter to the last stage inverter with a short delay time. However, each set of CMOS
Since the inverter performs switch operation at the same time, P channel transistors PJ, PJ, Ps
or N-channel transistor N1. N2. A large transient current flows through N3. This will be explained in detail below.

BACKGROUND ART Recent advances in semiconductor technology have led to miniaturization of semiconductor devices, making it possible to increase the integration and density of chips, and to increase the speed of devices. In order to miniaturize elements, the wiring width made of aluminum or the like is narrowed to reduce the wiring area, but when the wiring width t is made thinner, the inductive load of the wiring, that is, the inductance increases. do. On the other hand, in order to increase the speed of devices, the transistor size is increased to increase the transistor's 'current' JA performance, but as the transistor size increases, its on-resistance decreases. . Due to phenomena such as an increase in the inductive load of the wiring and a decrease in the on-resistance O of the MOS (MOS) run lister, the following problems arise in the conventional output circuit. That is, in the output circuit shown in Figure 3 (11>), Ll is the inductive load of the VDD power supply wiring, Ll is the inductive load of the ground wiring, L3 is the inductive load of the output wiring, and C is the load capacitance of the output wiring. Therefore, V on the high potential side
Between the DD power supply and the output terminal (output pad) 35 and between the low potential side VS8 power supply (ground power supply) and the output terminal 35, inductive loads Lx, L; A resonant circuit is formed. Therefore, the input potential of the input node IN is inverted from the VSS potential to the vDDt level, and the N-channel transistors Nl, N2 . When N3 becomes conductive, the charge accumulated in the load capacitor C suddenly flows into the Vss1 source, and when the output potential of the output terminal 35 falls from the VDD potential to the V8S potential, a transient current is generated. This causes an undershade phenomenon as shown by the dotted line in FIG. Contrary to the above, the input potential is VD
D potential is inverted to Vss@, and P channel transistor P1. When PJ and PJ become conductive, the load capacitance fC is rapidly charged and the output potential changes from VSS to VDD.
2, a transient current flows, causing an overshoot phenomenon as shown by the dotted line in FIG. When such undershoot and overshading occur, the output potential will fluctuate immediately after being reversed.
A problem often arises in which a signal with an incorrect potential is transmitted. Furthermore, a large voltage is induced due to the sudden large current flowing through the inductive loads LJ and L2, and VDD I! Since the potential of the power source and the potential of the VSa power source also fluctuate, the input/output levels of other circuits connected to this power source may fluctuate, causing circuit malfunction.

Furthermore, in the conventional output circuit, when the input signal is inverted, the P channel transistors P1°Pz, Ps
and N-channel transistor NJ.

N2. N.? There is a moment when both are turned on at the same time, and a through current flows. This through current flows through the inductive loads Lz, L
Since a large voltage is induced in the circuit 2, it causes fluctuations in the stain source and is one of the causes of malfunction of other circuits.

(Problems to be Solved by the Invention) The present invention solves the problem of inductive loads and M
OS) This was created to solve the problem that the increase in the driving force of the run lister increases transient phenomena and power supply voltage fluctuations during switch operation, causing circuit malfunction. It is an object of the present invention to provide an output circuit that can suppress fluctuations, prevent the generation of through current, and eliminate the risk of malfunctioning of other circuits.

[Structure of the invention]

(Means for Solving the Problems) The output circuit of the present invention sequentially applies a delay due to the resistance of polysilicon wiring to the gate inputs of a plurality of CMOS inverters whose output nodes are commonly connected, and A MOS (MOS) run lister for off control is connected between the gate of the transistor and the power supply, and the CMO
M for off control connected to the gate of the transistor that inverts from the on state to the off state in the S inverter.
OS) The run lister is controlled to be turned on.

(Function) Since on-current does not flow through the transistors of the CMOS inverters at each stage at the same time, the transient state of the switch operation
fvA phenomenon and power supply voltage fluctuations are suppressed. Also, CM
Among the transistors in the OS inverter, the OFF operation of the transistor that inverts from the ON state to the OFF state is promoted by the ON operation of the transistor for OFF control, so the CM
In the OS inverter, one transistor is turned off before the other transistor is turned on, so no through current flows, and no power supply voltage fluctuations occur due to this.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) and 1(b) show the circuit connections and pattern arrangement of an output circuit in which each output node of a plurality of sets of CMOS inverters is commonly connected. That is, P1 to P3 are a plurality (three in this example) of P-channel MOS transistors each having a source S connected to the VDD power supply line 11 (the contact portion is indicated by an x mark), and N1 to N3 are each having a source S connected to the VDD power supply line 11. are a plurality of (three in this example) N-channel MOS transistors connected to the VaS power supply line (ground line) 12 (the contact portions are indicated by x marks). The drains D of each of the transistors P1 to PJ and Nz to N2 (these are referred to as first MOS transistors) are commonly connected to one output pad 14 via a metal wiring (usually aluminum) 13. . Note that C is the load capacitance of the metal wiring 13. On the other hand, IN is a signal input node, and each gate (polysilicon ) are connected to the polysilicon wiring 17, 1 gK connection (the contact portion is indicated by an x mark), and are further connected to the off control ON channel MOS transistors N5 to NF, P via the metal wiring 19°2Q.
Channel MOS transistors P5 to Py (these are
It is connected to each gate (/resilicon wiring 21, 22) of a MOS (referred to as a run lister) (the contact portion is indicated by an x mark). The above N-channel transistor N
4. Each of the sources S of N5 to N7 is connected to the VSS power supply line 12 (the contact portion is indicated by an X mark), and the sources S of the above P
Each source S of the channel transistors P4, P5 to P7 is connected to the VDD power supply line 11 (the contact portion is indicated by an x mark). The drain D of the N-channel transistor N4 for on-control is connected to the silicon wiring I through the metal wiring 23 and then connected to each gate (resilicon) of the P-channel transistors P1 to P3, which are the first MOS run listers. Similarly, it is connected to one end of 24 (the contact portion is indicated by an x).
The drain D of the P-channel transistor P4 for ON control is connected to each gate (/
(1A) is connected to one end of the continuous polysilicon arrangement 1A26 (the contact portion is indicated by an x mark). Further, each drain D of the ON-channel transistors N5 to N7 for OFF control is connected to a portion of the polysilicon wiring 26 in the vicinity of each gate of the N-channel transistors N1 to N3 via a metal wiring (contact portion). (indicated by an X). Similarly, the drains of the off-control P-channel transistors P5 to P7 correspond to the drains of the P-channel transistors P1 to P1 in the polysilicon wiring 24, respectively.
It is connected to the vicinity of each gate of No. 3 via metal wiring (the contact portion is indicated by an x mark).

The N-channel transistors N1 to N3, which are the first MOS) run listers, are formed in a P-type substrate region 27 insulated and lined up, and the polysilicon wiring 26 connected to each gate is a comb as a whole. The pattern is bent multiple times. A P-type substrate region 28 in which the off-control N-channel transistors N5 to Nr are insulated and separated from each other is located adjacent to this region. Similarly, the first M.O.
S) P-channel transistors P1 to P that are run listers
3 are formed in an N-type substrate region 29 so as to be insulated from each other and lined up, and the polysilicon wiring 24 connected to each gate has a comb-like pattern which is bent multiple times as a whole. Then, the P-channel transistors P5 to P7 for OFF control are arranged in this vicinity.
An N-type substrate dependent region 30 is located in which the substrates are insulated and separated from each other.

In the output circuit having the above configuration, the resistance of the polysilicon wiring 24 connected to each gate of the P-channel transistors P1 to P3, which are the first MOS transistors, exists as r1 to r3 corresponding to the input side of each gate. There is. Similarly, the resistance of the polysilicon wiring 26 connected to each gate of N-channel transistors N1 to N3, which are first MOS transistors, is r J / corresponding to the input side of each gate.
~13'. Therefore, P channel transistors P1 to P3 and N channel transistor N1
CMO layered by each corresponding pair with ~N3
The S inverter is configured such that the input signal is gradually delayed and transmitted from the front stage side to the rear stage side due to the presence of the resistor component.

Next, the operation of the output circuit will be explained with reference to FIG. When the signal input node IN is at the VDD potential, the N channel transistor N4Fi is in the on state, the P channel transistors D5 to P2 are in the off state, and the gate potential of the P channel transistors P1 to P3 is at the VB+1 potential.
Channel transistors P1 to P3 are in an on state. On the other hand, at this time, the P-channel transistor P4 is in the off state, and the N-channel transistors N5 to N7 are in the on state, and their respective drain D potentials are at about Vsa IE, so the N-channel transistor Nz-N3 is almost in the off state. ing. Therefore, the output terminal (output pad) 14 is at VDD potential. Now, the input potential is the above VDD il! When the potential is reversed from VB8 to VB8, N
channel transistor N4tri is turned off), and the input potential v8ε is input to the gates of P-channel transistors D5 to P5. Transistors P1 to P3 are turned off to promote their discharge. On the other hand, the input potential V8B of the N-channel transistors N5 to N7 is directly input to the gate and is turned off, but the P-channel transistor P4 is not turned on, and the input potential VaB of the N-channel transistors N1 to N3 is set to the above-mentioned P. Since the voltage VDD inverted by the channel transistor P4 becomes the gate input, each transistor is turned on. Therefore, the output potential becomes V88 potential.

In this case, the VDD potential is input to each gate of the N-channel transistors N1 to N3 with a delay of the resistance molecule J /~rs'yc, so they are turned on one after another, and they are not turned on at the same time, so the load capacitance C If the inflow of charge from the output voltage is gradual, as shown by the solid line in Figure 2, no transient phenomenon (under-rate phenomenon) occurs when the output potential falls, but the output current characteristics are not impaired. do not have. In addition, the above N
Before the channel transistors N1 to N3 are sequentially turned on, the P channel transistors P5 to P7 are turned on, and VDD potential is applied to each gate of the P channel transistors P1 to P3, so that the P channel transistors P1 to P3 are turned off. No through current flows through each CMOS inverter.

Contrary to the above, when the input potential is reversed from the V8g potential to the VDD potential, the P channel transistors D5 to P5 turn off, but the N channel transistor N4 turns on, so each of the P channel transistors P1 to P3 A VSS potential, which is an inversion of the input potential VDD, is sequentially delayed and input to the gate. On the other hand, P-channel transistor P4
is turned off, but N-channel transistors N5 to N7 are turned on and V811 potential is applied to each gate of N-channel transistors N1 to N3 to turn them off and promote their discharge. Therefore, the output potential becomes VDD potential, but the P-channel transistors P1 to P3 are turned on sequentially), but not at the same time.
Charge from the VDD power supply to the load capacitor C becomes gradual, and as shown by the solid line in Figure 2, no transient phenomenon (overshoot phenomenon) occurs when the output potential rises.
The output current characteristics are not impaired. Also, CMOS
In each inverter, N-channel transistors N1-N3 are turned off before P-channel transistors P1-P3 are turned on, so no through current flows.

According to the output circuit of the above embodiment, the load capacitance is charged and discharged by sequentially applying a delay due to the resistance of the polysilicon wiring to the gate input of the CMOS inverter in each stage. Since this is done slowly, the transistors in each stage are not turned on at the same time, and transient phenomena and power supply voltage fluctuations during switch operation can be suppressed. Also, CMOS
Among the transistors in the innocoutor, the transistors in the CMOS inverter have MOS) run resistors N5 to Ny and Ps to P7 to promote the off operation of the transistors that reverse from on state to off state. is performed before the other transistor is turned on, no through current flows, and no power supply voltage fluctuation occurs due to this.

In the above embodiment, each interval between N-channel transistors N5 to N2 for off control is set to N-channel transistor N
The gate intervals of 1 to N3 are set to be equal to tt,
Similarly, the intervals between the off-control P-channel transistors D5 to Pf are approximately equal to the gate intervals of the P-channel transistors P1 to P3, but the off-control N-channel transistors and P-channel transistors The number of MOS) run listers may be increased and a plurality of MOS run listers for controlling one gate π-off of the first MOS run lister may be connected in parallel.

Moreover, instead of the drain Di polysilicon wiring 23 of the N-channel transistor N4 for on-control in the above embodiment, the N-channel transistor N5 to N6 for off-control is used.
(polysilicon wiring 21), one end of the polysilicon wiring 24 is connected to the input node IN, and similarly the drain of the P-channel transistor D4 for ON control is connected to the gate (polysilicon wiring 21) for OFF control instead of the I-silicon wiring 26. When the input potential is VDD, the output potential is VSS, and when the input potential is VB2, the output potential becomes VDD.

In addition, P channel transistors P5 to P7 for off control
Alternatively, in order to quickly transmit the input potential to the N-channel transistors N5 to N7, the P-channel transistor P
A metal wiring (not shown) is provided to connect the vicinity of each of the gates of N-channel transistors N5 to P7 with the metal wiring 20, and also connect the vicinity of each gate of N-channel transistors N5 to N7 with the metal wiring 19. Metal wiring (not shown)
may be provided.

Nlista.

〔Effect of the invention〕

As described above, according to the output circuit of the present invention, it is possible to suppress transient phenomena, through current, and power supply voltage fluctuations during switch operation, to correctly transmit the output potential to the subsequent stage, and to prevent other circuits that use a common power supply. It has advantages such as eliminating the risk of malfunction, and is effective when applied to MO8 integrated circuits.

[Brief explanation of the drawing]

FIG. 1(a) is an equivalent circuit diagram showing one embodiment of the output circuit of the present invention, and FIG. 1(b) is a diagram showing an example of pattern arrangement on a semiconductor chip corresponding to the circuit of FIG. 1(a). , FIG. 2 is a waveform diagram showing the output potential waveform of the circuit in FIG. 1(a) and the output potential waveform of the conventional output circuit, FIG. 3(a) is an equivalent circuit diagram showing the conventional output circuit, Figure 3 (b) is the same figure (a)
FIG. 3 is a diagram showing an example of pattern arrangement on a semiconductor chip corresponding to the circuit of FIG. IN...Input node, 14...Output pad, 24°26...-Resilicon wiring, 27.29...Substrate area, P1~Ps, N1~N3...MOS) Run lister, P5~ P7. N5~N7... MO8 for off control
) Applicant's agent Patent attorney Takehiko Suzue Procedural amendment

Claims (2)

[Claims] (1) Each is connected to a common high-potential side V_D_D power supply and a low-potential side V_S_S power supply, each output node is connected to a common output pad, and each P-channel MOS
a plurality of CMOS inverters in which complementary input potentials are applied to polysilicon wiring that connects the gates of the transistors and polysilicon wiring that connects the gates of the respective N-channel MOS transistors;
For off control, each gate is connected between each gate of the P channel MOS transistor of each S inverter and the V_D_D power supply, and an input potential complementary to the gate input potential of the P channel MOS transistor is applied to each gate. a plurality of P-channel transistors, and an N-channel MO of each of the CMOS inverters.
a plurality of N channels for off control, each connected between each gate of the S transistor and the V_S_S power supply, and each gate of which is supplied with an input potential complementary to the gate input potential of the N channel MOS transistor; An output circuit comprising a transistor. (2) P channel M of each of the CMOS inverters
The OS transistors are formed side by side in the same substrate region, and the polysilicon wiring connected to each gate has a comb-like pattern that is bent multiple times as a whole, and similarly, the N-channel MO of each of the CMOS inverters
Claim 1, wherein the S transistors are formed side by side in the same substrate region, and the polysilicon wiring connected to each gate has a comb-like pattern that is bent multiple times as a whole. output circuit.