KR100284297B1 - Output buffer - Google Patents

Abstract

The present invention relates to an output buffer. In the prior art, since an output buffer is applied with the same input signal to the P-MOS transistor and the N-MOS transistor, the input value is either logic 1 (power supply voltage level) or logic 0 (ground level). If fixed to), the output terminal outputs a fixed voltage value with GND or VDD value.If the input signal changes from logic 1 to logic 0 or from logic 0 to logic 1, the voltage level and logic of logic 0 A period in which the P-MOS transistor or the N-MOS transistor is turned on at the same time at the intermediate voltage of the voltage level of 1 is generated and the current flowing by shorting the two power terminals VDD and GND (hereinafter, referred to as 'short circuit current') Power consumption increases, and because the amount of current flowing per unit time is large, it may cause noise in the power supply stage, causing unwanted output. In addition, if the amount of short circuit current is reduced by reducing the rising time or falling time of the signal applied to the input terminal, the current change per unit time increases, causing noise, and increasing the rising time or the falling time. On the contrary, there is a problem in that the amount of short circuit current increases.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and by controlling the signals applied to the input terminal of the N-MOS transistor and the P-MOS transistor differently to reduce the short circuit current, rise time and By providing an output buffer to control the polling time to reduce the noise caused by the change of current per unit time, the P-MOS transistor or the N-MOS transistor is turned off and then driven before switching to prevent short circuit current. The power consumption can be reduced, and the signals applied to the P-MOS transistors and the N-MOS transistors at the output stage can be adjusted at the time of rising and falling, respectively, so that the rapid change in the current per unit time at the output stage during charging or discharging can be achieved. By suppressing, there is an effect of preventing generation of noise.

Description

Output buffer {OUTPUT BUFFER}

The present invention relates to an output buffer, and in particular, to control the signal applied to the output buffer stage consisting of the N-MOS transistor and the P-MOS transistor to reduce the short circuit current, and to control the rising time and the falling time per unit time The present invention relates to an output buffer that reduces noise caused by a change in current.

The conventional output buffer has a common gate of the P-MOS transistor 102 having the source connected to the power supply voltage VDD and the N-MOS transistor 103 having the source connected to the ground GND as shown in FIG. The input terminal 101 is connected, and the drains of the P-MOS transistor 102 and the N-MOS transistor 103 are connected to the output terminal 104 in common.

The operation process of the conventional output buffer configured as described above is as follows.

In FIG. 1, when the signal of the input terminal 101 is logic 1 (voltage level VDD) or logic 0 (voltage level GND), the P-MOS transistor 102 and the N-MOS transistor 103 are turned off and turned on, respectively. Or turned on and turned off.

That is, in the case of logic 1, the N-MOS transistor 103 is turned on while the P-MOS transistor 102 is turned off so that the output terminal 104 has a voltage level equal to GND.

However, in the case of logic 0, the N-MOS transistor 103 is turned off and the P-MOS transistor 102 is turned on, so that the output terminal 104 has a voltage level equal to VDD, which is a power supply voltage. Have

As described above, in the conventional technology, since the same input signal is applied to the P-MOS transistor and the N-MOS transistor, the output buffer has a GND or VDD value when the input value is fixed to logic 1 or logic 0. A fixed voltage value is output. When a signal at an input terminal is changed from logic 1 to logic 0 or from logic 0 to logic 1, the P-MOS transistor is connected to the voltage level of logic 0 and the voltage level of logic 1 at an intermediate voltage. The N-MOS transistor is turned on at the same time, and the power is increased by the current (hereinafter, referred to as a short circuit current) that flows as the two power terminals VDD and GND are momentarily shortened, and per unit time. Since the amount of current flowing is large, it may cause noise in the power supply stage, causing unwanted output, and also rising the signal applied to the input terminal. Reducing the amount of short circuit current by reducing the rising time or falling time increases the current change per unit time, causing noise, and increasing the rising time or the polling time, conversely, increases the amount of short circuit current. There was a problem.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and by controlling the signals applied to the input terminal of the N-MOS transistor and the P-MOS transistor differently to reduce the short circuit current, rise time and Its purpose is to provide an output buffer that controls the polling time to reduce noise due to current changes per unit time.

1 is a circuit diagram showing the configuration of a conventional output buffer.

2 is an exemplary view showing a configuration of an output buffer of the present invention.

3 is a diagram of voltage waveforms at each node of FIG. 2;

*** Explanation of symbols for the main parts of the drawing ***

102,202,203,206: P-MOS transistor 101,201: input terminal

103,204,205,207: N-MOS transistor 104,208: Output stage

N220: Node 1 N230: Node 2

In order to achieve the above object, a configuration of an output buffer of the present invention may include connecting the gates of the first and second P-MOS transistors and the first and second N-MOS transistors to an input terminal in common, The source is connected to the power supply voltage in common with the source of the third P-MOS transistor, and the source of the second P-MOS transistor is connected to the third P- through the node 1 in common with the drain of the first P-MOS transistor. A gate of the MOS transistor, a drain of the first N-MOS transistor, and a node of the node 1; a source of the second N-MOS transistor and a third N-MOS transistor in common; A source of the first N-MOS transistor and a drain of the second N-MOS transistor are connected in common to a gate of the third N-MOS transistor through a node 2; The drain of the P-MOS transistor is connected to the node 2, and the drain of the third P-MOS transistor and the drain of the third N-MOS transistor are commonly connected to an output terminal.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a diagram illustrating a configuration of an output buffer according to the present invention. As shown in FIG. The gate is connected to the input terminal 201 in common, and the source of the first P-MOS transistor 202 is connected to the power supply voltage VDD in common with the source of the third P-MOS transistor 206. A source of the second P-MOS transistor 203 is connected to the gate of the third P-MOS transistor 206 through node 1 (220) in common with the drain of the first P-MOS transistor 202, and The drain of the first N-MOS transistor 204 is connected to the node 1 (N220), and the source of the second N-MOS transistor 205 and the third N-MOS transistor 207 are commonly grounded (GND). ), The source of the first N-MOS transistor 204 and the drain of the second N-MOS transistor 205 Is commonly connected to the gate of the third N-MOS transistor 207 through a node 2 (N230), the drain of the second P-MOS transistor 203 is connected to the node 2 (N230), and The drain of the third P-MOS transistor 206 and the drain of the third N-MOS transistor 207 are connected to the output terminal 208 in common.

Referring to Figure 3 attached to the operation of the embodiment according to the present invention configured as described above are as follows.

FIG. 3 is a diagram of voltage waveforms at each node of FIG. 2. As shown in FIG. 3, when the waveform as shown in FIG. As the body is shared, the threshold voltage Vthn2 of the first N-MOS transistor 204 located at the upper end may be higher than the threshold voltage Vthn1 of the second N-MOS transistor 205 at the lower end according to the body bias effect. At this time, when the signal of the input terminal 201 reaches the threshold voltage Vthn1 at the time of rising, the second N-MOS transistor 205 is first turned on to quickly discharge the charge charged in the node 2 (N230) (second yen). -The MOS transistor 205 makes the size relatively larger than the size of the first N-MOS transistor 204).

Subsequently, when the level of the signal of the input terminal 201 reaches the threshold voltage Vthn2, the first N-MOS transistor 204 is turned on and is relatively smaller in size than the second N-MOS transistor 250. There is a relatively large delay time for discharging the electric charge charged in the node 1 (N220).

That is, when switching from logic 0 to logic 1 as shown in FIG. 3, when the node 1 N220 connected to the gate of the third P-MOS transistor 206 of the output terminal 208 maintains the logic 1 state. The node 2 (N230) connected to the gate of the third N-MOS transistor 207 generates a section having a logic 0 state (section a in FIG. 3), so that a short circuit current does not flow (when switching). Since the third P-MOS transistor 206 is turned on while the N-MOS transistor 207 is first turned off, a short circuit does not occur).

In addition, since the delay of the signal input to the third P-MOS transistor 206 can be increased by adjusting the size of the first N-MOS transistor 204, the output terminal 208 without generating a short circuit. ), It is possible to control the time that the power supply voltage (VDD) is charged, thereby making it possible to reduce the change in the current per unit time to prevent noise generated at the output terminal.

If the signal applied from the input terminal 201 is changed from logic 1 to logic 0, as shown in FIG. 2, the first and second P-MOS transistors 202 and 203 share a body bias, so that the body According to the bias effect, the threshold voltage Vthp2 of the second P-MOS transistor 203 located at the lower end becomes higher than the threshold voltage Vthp1 of the first P-MOS transistor 202 at the upper end. The absolute value of the difference from the supply voltage VDD). At this time, when the signal of the input terminal 201 reaches the threshold voltage Vthp1 during polling, the first N-MOS transistor 204 is first turned on to charge the node 1 N220 (the first P-MOS transistor 202). ) Makes the size relatively larger than the size of the second P-MOS transistor 203).

Subsequently, when the level of the signal of the input terminal 201 reaches the threshold voltage Vthp2, the second P-MOS transistor 203 is turned on and is relatively smaller in size than the first P-MOS transistor 202. The node 2 N230 has a relatively large delay time when the power supply voltage is charged.

In this case, the waveforms applied to the nodes 1 and 2 (N220) and N230 have the same shape as in section b of FIG. That is, the first node N220 is charged first, and then the second node N230 is charged with a delay time.

Therefore, when the third P-MOS transistor 206 is turned off, the third N-MOS transistor 207 is turned on. In this case, since a short circuit does not occur, no short circuit current flows. .

In addition, by adjusting the size of the second P-MOS transistor 203, the output stage 208 may have a sufficient delay time without generating a short circuit when the third N-MOS transistor 207 is turned on. It is possible to reduce the amount of change in the current per unit time in, thereby suppressing the generation of noise.

As described above, the output buffer of the present invention controls the input signal to be applied, and then turns off the P-MOS transistor or the N-MOS transistor in advance during switching, thereby driving power consumption by preventing short circuit current from occurring. In addition, the signals applied to the P-MOS transistors and the N-MOS transistors at the output stage can be adjusted at the time of rising and falling, respectively, thereby suppressing a sudden change in the current per unit time at the output stage during charging or discharging, thereby reducing noise. It is effective to prevent the occurrence of.

Claims (3)

The gates of the first and second P-MOS transistors and the first and second N-MOS transistors are connected to the input terminal in common, and the source voltage of the first P-MOS transistor is common to the source of the third P-MOS transistor. A source of the second P-MOS transistor connected to a gate of the third P-MOS transistor through node 1 in common with a drain of the first P-MOS transistor; A drain of the second N-MOS transistor and a source of the third N-MOS transistor are connected to ground in common, and a source of the first N-MOS transistor and the second N-MOS transistor The drain of the transistor is commonly connected to the gate of the third N-MOS transistor through node 2, the drain of the second P-MOS transistor is connected to the node 2, and And a drain of the third P-MOS transistor and a drain of the third N-MOS transistor in common. The output of claim 1, wherein the sizes of the first P-MOS transistor and the second N-MOS transistor are larger than the sizes of the second P-MOS transistor and the first N-MOS transistor, respectively. buffer. The method of claim 1, wherein the first and second P-MOS transistors and the first and second N-MOS transistors share the same body bias, respectively, so that the threshold voltage changes due to the body bias effect during polling and rising of the input signal. Output buffers are sequentially turned on with a time difference according to the.