JPH09148909A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent malfunction owing to the sudden change of current without delaying an output signal by controlling the change speed of gate control voltage when a MOS transistor is switched from 'off' to 'on' in a semiconductor integrated circuit having a digital output buffer circuit by means of the MOS transistor. SOLUTION: When an input signal Din changes from L to H, the respective gate control voltages Vgp and Vgn of the MOS transistors P3 and N3 with p/n channels in an output stage 3 pulled down/driven from H to L by the MOS circuits 21 and 22 and are switched from L to H by turning on/off P3 and N3. Vgp of P3 pulling up the output signal Dout to H becomes less than a threshold level, a switch S1 is turned off and R1 is laid between P11 and N11. The pull-down driving of Vgp is suppressed and moderate rise is executed. Thus, the start of the rise of Dout becomes rapid, time is shortened, time is set to be moderat after rise and the sudden change of output voltage is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effective when applied to a semiconductor integrated circuit device, and further to a semiconductor integrated circuit device having a large number of digital output buffer circuits built therein, for example, a microprocessor or a gate array. The present invention relates to a technology effectively used for VLSI (Very Large Scale Integrated Circuit Device) such as.

[0002]

2. Description of the Related Art In a VLSI such as a microprocessor or a gate array, a large number of input buffer circuits and output buffer circuits are formed for exchanging digital signals with the outside. The output buffer circuit applies an external load to H (high level) or L via the terminal pad and the terminal lead.
A digital signal for logically driving (low level) is output, but when the output logics of a plurality of output buffer circuits change in the same direction all at once, the magnitude of the power supply current flowing through the semiconductor integrated circuit device suddenly increases. The noise may change and the noise generated due to this abrupt change in current may flow into other circuits such as the input buffer circuit to cause malfunction.

Therefore, in the prior art, the change rate of the output voltage in the output buffer circuit, so-called slew rate, is suppressed to alleviate the change in the power supply current when the output logic changes all at once. The generation of noise accompanying changes has been suppressed. In this case, the slew rate is suppressed by setting the size (W / L: gate width / length) of the MOS transistor forming the pre-stage circuit of the output buffer circuit to be small or by interposing a current limiting resistor in the pre-stage circuit. It was

[0004]

However, it has been clarified by the present inventors that the above-described technology has the following problems.

That is, the above-described conventional semiconductor integrated circuit device may be effective in preventing malfunction due to a sudden change in current, but the slew rate is suppressed in the preceding circuit for that purpose, so that the output signal is suppressed. However, there is a problem that the delay becomes large.

An object of the present invention is to eliminate the above-mentioned trade-off, and more specifically, in a semiconductor integrated circuit device having a digital output buffer circuit using MOS transistors, to greatly increase the delay of the output signal. It is another object of the present invention to provide a technique capable of preventing a malfunction caused by a rapid change in current.

The above and other objects and characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor integrated circuit device, the change speed of the gate control voltage when the MOS transistor forming the output stage of the digital output buffer circuit is switched from OFF to ON is high at the threshold level of the MOS transistor. The slew rate control is performed to switch from low speed to low speed.

According to the above-mentioned means, the MOS transistor of the output buffer circuit is turned on / off after the logic of the input signal is switched while suppressing the sudden change of the power supply current when the output logic of the digital output buffer circuit is changed. It is possible to selectively reduce only the delay until it is done.

Thus, in a semiconductor integrated circuit device having a digital output buffer circuit using MOS transistors, the purpose is to prevent malfunction due to a sudden change in current without significantly increasing the delay of the output signal. To be achieved.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

In the figures, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a main part of a semiconductor integrated circuit device to which the technique of the present invention is applied. 1 is a digital output buffer circuit, 2 is a pre-stage circuit, and 3 is a circuit.
Is an output stage, 4 is a slew rate control circuit, 5 is a terminal pad, Din is an input signal, Dout is an output signal, Vdd is a positive power supply potential, and Vss is a negative power supply potential (reference potential).
It is.

The pre-stage circuit 2 includes a p-channel MOS transistor P11 and an n-channel MOS transistor N11.
A first CMOS circuit (inverter) 21, a p-channel MOS transistor P21 and an n-channel MO
It is configured by a second CMOS circuit (inverter) 22 including an S transistor N21. Each CMOS circuit 21,
22 respectively inverts the phase of the input signal Din and transmits it.

The output stage 3 is a p-channel MOS transistor P3 in which the gate control voltage Vgp is pull-down / pull-up driven by the output of the first CMOS circuit 21, and
The second CMOS circuit 22 controls the gate control voltage Vgn.
N-channel MO with pull-up / pull-down drive
The S-transistor N3 is CMOS-connected and outputs a logic signal Dout in phase with the input signal Din to the terminal pad 5.

The slew rate control circuit 4 includes a first CMO.
The first control circuit unit 41 that controls the changing speed of the gate control voltage Vgp applied to the p-channel MOS transistor P3 from the S circuit 21, and the gate control voltage Vgn applied to the n-channel MOS transistor N3 from the second CMOS circuit 22. And a second control circuit unit 42 for controlling the changing speed of the.

The first control circuit section 41 includes a first CMOS
By interposing in series between the output node of the circuit 21 and the n-channel MOS transistor N11, a first change (pull-down drive) of the gate control voltage Vgp of the p-channel MOS transistor P3 from H to L is suppressed.
Resistor R1, a first switch circuit S1 forming a current bypass path for the first resistor R1, and the gate control voltage Vgp below a threshold level for switching the MOS transistor P3 from off to on ( <Vthp)
First threshold detection circuit 4 for detecting whether or not
11 and the switch circuit S1 is controlled to be turned on / off by the output of the threshold value detection circuit 411.

The second control circuit section 42 includes a second CMOS
The second interposition between the output node of the circuit 22 and the p-channel MOS transistor P21 in series suppresses the rising change (pull-up drive) of the gate control voltage Vgn of the n-channel MOS transistor N3 from L to H.
Resistor R2, a second switch circuit S2 forming a current bypass path with respect to the second resistor R2, and the gate control voltage Vgn above the threshold level for switching the MOS transistor N3 from off to on ( > Vthn)
Second threshold detection circuit 4 for detecting whether or not
21 and the ON / OFF control of the switch circuit S2 is performed by the output of the threshold detection circuit 421.

FIG. 2 shows the digital output circuit 1 shown in FIG.
3 is a waveform chart showing an operation example in the main part of FIG. In the figure, the solid line shows the operation waveform obtained by the technique of the present invention, and the broken line shows the operation waveform when the technique of the present invention is not used.

In FIGS. 1 and 2, when the input signal Din changes from L to H, the gate control voltages Vgp and Vgn of the p-channel MOS transistor P3 and the n-channel MOS transistor N3 of the output stage 3 are respectively set as follows. By the CMOS circuits 21 and 22 of the front stage circuit 2,
Pulled down from H to L. This pull-down driving is performed by turning on the n-channel MOS transistors N11 and N21 of the CMOS circuits 21 and 22, respectively.

Here, the p-channel MOS transistor P3 of the output stage 3 is switched from off to on by pulling down its gate control voltage Vgp to a threshold level Vthp or less, but the gate control voltage Vgp
At the same time that gp becomes equal to or lower than the threshold value Vthp, the switch circuit S1 is switched from on to off. Then, the first C for pulling down the gate control voltage Vgp is driven.
A resistor R1 is interposed in series between the output node of the MOS circuit 21 and the n-channel MOS transistor N11. Due to the resistor R1 interposed, the gate control voltage V
The gp pull-down drive is suppressed. That is, the gate control voltage Vgp when the p-channel MOS transistor P3 of the output stage 3 is switched from off to on.
The speed of change of is switched from high speed to low speed with the threshold level Vthp of the output stage MOS transistor P3 as a boundary.

On the other hand, the n-channel MOS transistor N
3, the gate control voltage Vgn is the threshold value V
By pull-down driving below thn, it is switched from on to off, contrary to the p-channel MOS transistor P3. The pull-down driving is performed by the n-channel MOS transistor N of the second CMOS circuit 22.
At 21, it is performed at high speed without interposing the resistor R2.

As a result, the output signal Dout is turned on and off when the p-channel MOS transistor P3 in the output stage 3 is turned on.
Although the channel MOS transistor N3 is switched off from L to H, the output signal Dout is pulled up to H and the p-channel MOS transistor P3 is driven.
As described above, the gate control voltage Vgp of
The change is suppressed at the threshold level Vthp of the S transistor P3. That is, the output signal Dout changes from L to H.
The gate control voltage Vgp of the p-channel MOS transistor P3 when the switching drive is performed to
After the S-transistor P3 is switched on, it rises relatively slowly, but until then, it rises rapidly.

As a result, as shown in FIG. 2, after the input signal Din is switched from L to H, the output signal Dou is output.
Delay time TdH1 until t starts to rise from L to H
And the output signal Dout
It is possible to suppress the change in the output voltage after the start of rising, that is, the slew rate. Note that TdH2 represents the rising delay time when the above-mentioned slew rate control is not performed.

Next, contrary to the above case, the input signal D
A case where in changes from H to L will be described. In this case, the p-channel MOS transistor P3 of the output stage 3
And the gate control voltages Vgp and Vgn of the n-channel MOS transistor N3 are respectively the CMOS of the pre-stage circuit 2.
Pulled up from L to H by the circuits 21 and 22. This pull-up drive is performed for each CMOS circuit 21, 22.
This is performed by turning on the p-channel MOS transistors P11 and P21.

Here, the gate control voltage Vgn of the n-channel MOS transistor N3 has a threshold level V
Although it is switched from OFF to ON by being pulled up to thn or more, the switch circuit S2 is switched from ON to OFF at the same time when the gate control voltage Vgn becomes equal to or higher than the threshold value Vthn. Then, the output node of the second CMOS circuit 22 that pulls up the gate control voltage Vgn and the p-channel MOS transistor P
A resistor R2 is interposed in series between 21 and the pull-up driving of the gate control voltage Vgn is suppressed by the resistor R2. That is, the change speed of the gate control voltage Vgn when the n-channel MOS transistor N3 is switched from off to on is switched from high speed to low speed with the threshold level Vthn of the output MOS transistor N3 as a boundary.

On the other hand, p-channel MOS transistor P
3, the gate control voltage Vgp is the threshold value V
The pull-up driving is switched from on to off, contrary to the n-channel MOS transistor N3, by pull-up driving more than thp. The pull-up driving is performed by the p-channel MOS transistor P of the first CMOS circuit 21.
At 11, it is performed at high speed without interposing the resistor R1.

As a result, the output signal Dout is set to p when the n-channel MOS transistor N3 in the output stage 3 is turned on.
When the channel MOS transistor P3 is turned off, it is switched from H to L, but an n-channel MOS transistor N that pulls down its output signal Dout to L.
As described above, the gate control voltage Vgn of
The change is suppressed at the threshold level Vthn of the OS transistor N3. That is, the gate control voltage Vgn of the n-channel MOS transistor N3 when switching the output signal Dout from H to L is the n-channel M
After the OS transistor N3 is switched on,
It will be started up relatively slowly, but will be started up rapidly until then.

As a result, as shown in FIG. 2, after the input signal Din is switched from H to L, the output signal Dou is output.
Delay time TdL1 from when t starts to fall from H to L
Can also be shortened. Along with this, the output signal D
It is also possible to suppress a change in the output voltage after out has started to fall, that is, a slew rate. In addition, TdL2
Indicates the fall delay time when the above slew rate control is not performed.

As described above, the MOS transistor in the output stage is turned on / off after the logic of the input signal is switched while suppressing the rapid change of the power supply current when the output logic of the digital output buffer circuit 1 is changed. It is possible to selectively reduce only the delay time until the start.

As a result, in a semiconductor integrated circuit device having a digital output buffer circuit using MOS transistors, it is possible to prevent malfunction due to a sudden change in current without increasing the delay of the output signal so much.

FIG. 3 shows the essential parts of another embodiment of the present invention.

In the embodiment shown in the figure, a tristate circuit based on the digital output buffer circuit 1 shown in FIG.
It constitutes a buffer circuit.

Differences from the configuration shown in FIG. 1 will be described. First and second CMOSs constituting the pre-stage circuit 2.
The circuits 21 and 22 have p-channel MOS transistors P12 and P22 and n-channel MOS transistors N12 and N22 for tri-state control interposed, and the transistors P12, P22 and N22 are provided.
An inverter 11 for controlling ON / OFF of 12, N22 with an enable signal EN is provided.

6 is a digital input buffer circuit,
Its input is connected to the terminal pad 5. The terminal pad 5 serves both as an input and an output.

In addition, a p-channel MOS transistor P
41, the resistor R41, and the inverter 412 form a first threshold value detection circuit 411. Similarly, the n-channel MOS transistor N42, the resistor R42, and the inverter 422 are connected to the second threshold detection circuit 421.
Is composed.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, gate control voltages Vgp and Vgn
The resistors R1 and R2 for controlling the change of the can be composed of MOS transistors.

In the above description, the case where the invention made by the present inventor is mainly applied to the CMOS type semiconductor integrated circuit device for digital use which is the background field of the invention has been described, but the invention is not limited thereto. Without
For example, it can be applied to a Bi-CMOS type semiconductor integrated circuit device.

[0041]

The following is a brief description of an outline of typical inventions among the inventions disclosed in the present application.

That is, in a semiconductor integrated circuit device having a digital output buffer circuit using MOS transistors, the delay of the output signal is not increased so much,
It is possible to obtain an effect that it is possible to prevent a malfunction caused by a rapid change in current.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a main part of the present invention.

FIG. 2 is a waveform chart showing an operation example of a main part of the present invention.

FIG. 3 is a circuit diagram showing another embodiment of the essential part of the present invention.

[Explanation of symbols]

1 Digital Output Buffer Circuit 2 Previous Stage Circuit 3 Output Stage 4 Slew Rate Control Circuit 41 First Control Circuit Section 42 Second Control Circuit Section 411, 412 Threshold Detection Circuit S1, S2 Switch Circuit 5 Terminal Pad 6 Digital Input Buffer Circuit Din input signal Dout output signal P11, P12, P21, P22, P41 p-channel MOS transistor N11, N12, N21, N22, N41 n-channel MOS transistor P3 p-channel MOS transistor N4 n-channel MOS transistor 21 First CMOS circuit ( Inverter 22 Second CMOS circuit (inverter) Vgp, Vgn Gate control voltage R1, R2 Resistance Vthp, Vthn Threshold level

Claims (4)

[Claims] 1. A semiconductor integrated circuit device having a digital output buffer circuit including MOS transistors, wherein a rate of change of a gate control voltage when switching a MOS transistor forming an output stage of the output buffer circuit from off to on A semiconductor integrated circuit device comprising a slew rate control circuit for switching from high speed to low speed at a threshold level of a MOS transistor. 2. The slew rate control circuit includes an output stage MOS.
A resistor that suppresses a change in the gate control voltage of the transistor, a switch circuit that forms a current bypass path for the resistor, and the gate control voltage has a threshold level that switches the output stage MOS transistor from off to on. And a threshold detection circuit for detecting whether or not
2. The semiconductor integrated circuit device according to claim 1, wherein the switch circuit is controlled to be turned on / off by the output of the threshold detection circuit. 3. The digital output buffer circuit pulls down / pulls up a CMOS output stage formed by a p-channel MOS transistor and an n-channel MOS transistor, and a gate control voltage of the p-channel MOS transistor according to an input signal. First CMO
The slew rate control circuit has an S circuit and a second CMOS circuit that pulls up / down pulls down the gate control voltage of the n-channel MOS transistor according to an input signal. The slew rate control circuit includes a pull-down drive current by the first CMOS circuit. And a first resistor that limits the pull-up drive current of the second CMOS circuit, a first switch circuit that is connected in parallel to the first resistor, and a second resistor that is parallel to the second resistor. The second switch circuit connected to the MOS transistor and the gate control voltage of the p-channel MOS transistor
The first threshold value detection circuit for turning on the first switch circuit and the gate control voltage of the output n-channel MOS transistor are controlled by the threshold value of the MOS transistor until it is pulled down to the threshold level of the transistor. 3. The semiconductor integrated circuit device according to claim 1, further comprising a second threshold value detection circuit that turns on the second switch circuit until it is pulled up to a value level. 4. The semiconductor integrated circuit device according to claim 1, wherein the digital output buffer circuit is configured as a tri-state buffer circuit.