JPS5842658B2 - Level Henkan Kairono Hogo Kairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a level conversion circuit for MO8/IC memory, which protects the device from being destroyed due to power failure or the like.

In a level conversion circuit (hereinafter referred to as a level shifter) that converts a TTL level to a MOS level for a MOS-I C memory (e.g. equivalent to AMS6002), the level shifter may fail due to a power outage or power supply unit failure during memory operation. output transistors may be destroyed.

FIG. 1 is a circuit connection diagram showing an example of a TTL-MOS level shifter.

In the figure, 5■ is the TTL logic power supply, ■8x,
V88 is a special power supply, Ql, Q2 are output transistors, Q
a, Q4 is a control transistor, Q5 is a transistor forming a NAND circuit, D is a diode of the NAND circuit, TTL/IN is a TTL input of a level shifter, MO
8-OUT is a MOS level output.

When the power supply is normal and all TTL inputs are 1'', the diagram shows positive pulse logic, so no current flows through diode D, NAND gate transistor Q5 is turned on, and its output is 0. get.

When transistor Q is turned on, transistors Q4 and Q2 are also turned on.

On the other hand, transistor Q3. Since Q1 is off, the MOS level output of the level shifter has the ground voltage “O”.
n is obtained.

Also, if any of the TTL inputs is "0'", current flows through the diode D, and the base potential of the NAND gate transistor Q5 becomes low, so the transistor Q
, are turned off, and transistors Q4 and Q2 are also turned off.

In this case, the transistor Q3 is turned on and the output transistor Q□ is also turned on, so that 20V of VSS can be obtained as is at the MOS level output of the level shifter.

In this way, the NAND output for the TTL input is
Extracted at MOS level.

If a power outage or power supply unit failure occurs, the special power supply v
When the TTL logic power supply 5V goes down while sx j vss is on, the MOS level output becomes “'0”.
'', the output transistors Q1 and Q2 may be destroyed due to overcurrent on the circuit.

That is, all TTL inputs are "1", transistors Q5, Q4, and Q2 are on, and Q3 . When Ql is off and the MOS level output is "0", when the potential of 5V becomes low, the TTL input will still act as "1" and transistor Q5 will not turn off forever, reducing the base current of transistor Q4. .

Therefore, the collector-emitter of the transistor Q4 is no longer completely conductive, and the base current begins to flow to the transistor Q3 as well, and the output transistors Q1. A situation arises in which Q2 is turned on at the same time.

At this time, since a current limiting resistor is not included in the VSSQt Q2 GND route due to speed considerations, a phenomenon occurs in which either transistor Ql or Q2 is destroyed due to overcurrent.

The present invention solves the above-mentioned conventional drawbacks, and aims to provide a protection circuit so that a TTLMOS level shifter for a MOS/IC memory is not destroyed due to a power outage or power supply failure.

In the present invention, when the 5V potential drops due to a power supply failure, etc., the NAND gate transistor Q5 continues to be turned on indefinitely, causing destruction.
When this level is reached, the TTL input is forced to '0' and NAND gate transistor Q5 is immediately turned off, thereby preventing destruction.

Examples will be described below with reference to the drawings.

FIG. 2 is a connection diagram of a level shifter protection circuit showing an embodiment of the present invention, and FIG. 3 is a timing chart of the 5V power supply value in FIG. 2 after the power is cut off.

In Figures 2 and 3, IN is the input of the protection circuit, Q7 to Q1
o is a transistor, R1 and R2 are threshold level adjustment resistors, R3 is a current adjustment resistor, D2. D3 is a temperature compensation diode, PW/CUT is when the power is turned off, v
D is the destruction area of the level shifter, and ■P is the threshold level.

When the power supply is cut off due to a power outage or power supply failure, the potential decreases according to the curve shown in FIG. 3 due to the discharging time constant of the power supply capacitor.

In the breakdown region vD of approximately 3.0 to 3.5 cm, the level shifter output transistor Q1. If any of Q2 is to be destroyed, the destruction must be prevented before the 5-volt power supply value drops to this destruction region VD.

In this embodiment, a protection circuit as shown in FIG. 2 is connected to the TTL input terminal of the level shifter shown in FIG.

Connect to.

In other words, one of the protection circuit inputs IN is set to the level shown in Figure 1.
It can be connected to one of the shifter TTL inputs.

NAND gate transistor Q5 in FIG.
If one of inputs 1, 2, and 3 becomes “0” by hand, then 5
Since it is turned off regardless of the decrease in the v voltage power supply value, one of the protection circuit inputs IN is connected only to the TTL power supply 3, for example.

Other protection circuit inputs IN are connected to one of the inputs of other NAND gates (not shown) or to empty terminals, respectively.

In Figure 2, under normal conditions, transistor Q7 is on and Q
8~Qlo is off, but when the 5v supply drops, the values of resistors R1, R2 and diodes D2.
By adjusting the number of D3, the transistor Q7
is set so that it is turned off at the potential of Vp (approximately 4V) in FIG.

In the example of FIG. 2, in the normal case, the voltage drop across resistors R1J and R2 and the voltage drop across diode D2. Each 0.5V voltage drop on D3 causes a current of -2mA to flow between the base and emitter of transistor Q7, and the 20V power supply causes a current of 2mA to flow between the collector and emitter of transistor Q7 through resistor R3.
A current of mA is applied.

At this time, since the base potentials of transistors Q8 to Qto are low, Q6 is off.

When the 5V power supply is cut off, the 5V potential drops to about 4mm, and the base current of transistor Q7 stops flowing.
Transistor Q7 is turned off.

As a result, the base potential of transistors Q8-Q1o rises, and transistors Q8-Q1o are turned on.

This forces each input of the protection circuit to ground “Ot”.
dropped to t.

As a result, TTL input 3 in Figure 1 becomes "0",
By turning off the transistor Q5, turning on the output transistor Q1 of the level shifter, and turning off the output transistor Q2, it is possible to avoid a situation where both are turned on at the same time.

D2. D3 is for compensating for variations in operating point due to temperature, and turns on transistors Q8 to QIO at about 4V even when the temperature rises.

FIG. 4 is an input coupling diagram of a protection circuit according to the invention.

Three NAND circuits are connected to the level shifter, and the NAND
DI has one free terminal input, but three inputs are applied to each of the other NAND circuits.

One of the TTL inputs of each NAND circuit is taken out and connected to the input IN of the protection circuit.

In NANDl, empty terminal processing is performed.

Diode D1 is inserted to prevent current from flowing around.

As explained above, according to the present invention, when the TTL logic power supply drops due to a power failure or the like, the TTL input of the level shifter is forcibly grounded at a predetermined potential, so that the output transistor of the level shifter is Simultaneous turning on conditions are prevented, and destructive phenomena can be effectively protected.

[Brief explanation of drawings]

FIG. 1 is a one-way connection diagram showing an example of a TTL-MOS level shifter, FIG. 2 is a connection diagram of a level shifter protection circuit showing an embodiment of the present invention, and FIG.
Timing chart after power-off of power supply potential, No.
FIG. 4 is a circuit diagram of the connection between the protection circuit and the input terminal of the TTL level input circuit according to the embodiment of the present invention. 5V: TTLo thick power supply, vsX, v88: special power supply, Q, , Q2: output transistor, Q5: NAN
D gate transistor, D: NAND gate diode, TTL input of TTL/■N two-level shifter, M
OS-0UT: MO8 output, ■N: Input of protection circuit, R1, R2, R3: Resistor, Dl, D2. D3: Diode, vP: Threshold level, vD double level
Shifter destruction area, PW-CUT: At the time of power cut.

Claims (1)

[Claims] 1. An input circuit that has a plurality of input terminals that receive a first binary level that is the output of the preceding stage circuit, and operates on the power source of the preceding stage circuit, and a first and second power supply connected in series. 1
, a protection circuit for a level conversion circuit comprising an output circuit that generates a second binary level at a connection point between the first and second transistors by selectively operating a second transistor, the input circuit comprising: When the power supply voltage at which the input circuit operates decreases according to the discharging time constant of the power supply capacitor due to power cut-off, and both the first and second transistors become conductive and reach a predetermined voltage on the way to the breakdown region, the input circuit 1. A protection circuit for a level conversion circuit, characterized in that means for forcibly lowering a binary level input to a ground potential is connected to an input terminal of the input circuit.