JPS61292412A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent undershoot from being generated by lowering an output level voltage rapidly until a prescribed low level voltage and lowering comparatively slowly until the final power voltage level after that so as to decrease a period until the output reaches the specified voltage. CONSTITUTION:When a voltage at an output B is lowered up to a threshold voltage Vtb of an N-channel MIS transistor (TR) 31, since a gate of the N- channel MIS TR 31 reaches the voltage via an N-channel MIS TR 21, the N-channel MIS TR 31 is turned off and the current no longer flows from the output B via the N-channel MIS TRs 21, 31. Thus, the current from the output B afterward is only the current via the N-channel MIS TR 41. Since the ga of the N-channel MIS TR 41 is small, the change to a low level at the output B afterward is gentle and no undershoot is caused. That is, the output voltage cannot be below power voltage tentatively.

Description

[Detailed Description of the Invention] [Summary] An output circuit comprising a g-
A threshold element is provided between the source of the first MIS transistor with a large value and the low potential side power supply, and the gate is
connected to the gate of the S transistor and gn is the first MIS
By providing a second MIS transistor smaller than the transistor between the output end and the low potential side power supply, it is possible to prevent the output voltage from rapidly falling to a predetermined voltage and undershoot.

[Industrial application field]

The present invention relates to a semiconductor circuit, particularly an output circuit having a CMOS configuration.

[Conventional technology]

FIG. 6 shows an output circuit with a CMOS configuration according to a conventional example,
5 is a P-channel MIS transistor.

6 is an N-channel MIS transistor.

The gate of P-channel MIS transistor 5 and the gate of N-channel MIS transistor 6 are commonly connected to form input A, and the drain of P-channel MIS transistor 5 and the drain of N-channel MIS transistor 6 are commonly connected to form output B. (Vour). Further, the source of the P-channel MIS transistor 5 is connected to the power supply Vcc, and the source of the N-channel MIS transistor 6 is connected to the power supply VSS. In this circuit, when a low level signal is input to input A, output B becomes high level, while when a high level signal is input, output B becomes low level.
This is a so-called inverter circuit.

By the way, since output B is connected to an external circuit, it may have a fairly large load capacity. In this case, the level change of the output signal is significantly delayed, and the output voltage does not reach the standard voltage within a predetermined time, which may lead to malfunction of the external circuit.

Therefore, in general, g- of the MIS transistors 5 and 6 constituting the output circuit is increased to increase the driving ability and to prevent a delay in the level transition time.

[Problem that the invention seeks to solve]

Figure 7(a) is a diagram showing the output characteristics when transitioning from high level to low level when g- of MIS transistor is increased. In Figure 7, the horizontal axis t is time, and the vertical axis #Vo
uy indicates the output voltage, the dashed line on the voltage axis side is the output low level standard voltage (o, av in the figure), and t is the time required for the output to change from a high level to a standard low level. It shows. On the other hand, FIG. 7(b) is a diagram showing the output characteristics when g- of the MIS transistor 6 is not very large. The same symbols as in FIG. 7(a) indicate the same things, and the output load are also the same. t2 indicates the time required for the output to change from a high level to a standard low level.

In this way, by increasing g of the MIS transistor that constitutes the output circuit, it is true that the output level transition time can be made faster (t+<t2), but as shown in FIG. 7(a),
When the output level changes from a high level to a low level, the output voltage temporarily drops below the power supply voltage VSS (undershoot)0 Although not shown, this also occurs when the output level changes from a low level to a high level. Similarly, the output voltage temporarily rises above the power supply voltage VCC (overshoot), which not only causes fluctuations in the power supply voltage level and becomes a source of various noises, but also especially the undershoot of the output voltage in the 0M03 circuit. In some cases, this could trigger latch-up of the parasitic thyristor and destroy the circuit.

As described above, according to the conventional output circuit, the driving ability of the output MIS transistor cannot be increased beyond a certain level due to the risk of latch-up of the parasitic thyristor, and therefore the transition time cannot be sufficiently shortened. There was a point.

The present invention was created in view of these points,
It is an object of the present invention to provide an output circuit which is free from the risk of occurrence of ruff stub of a parasitic thyristor and which operates by shortening the transition time of output level change.

[Means for solving problems]

The configuration of the output circuit according to the present invention is as shown in FIG. and the first MIS transistor 2.

A threshold element 3 connected between the source of the first MIS transistor 2 and the low potential power supply VSS, and a second MIS transistor 4 connected between the output terminal B and the low potential power supply VS2. comprising the first. The gate of the second MIS transistor 2.4 is connected to the input terminal A, and the gate of the second MIS transistor 2.4 is connected to the input terminal A.
g of the transistor 2 to the second MIS transistor 4
It is characterized by being larger than the GM.

[Effect]

When the signal input to the input terminal A changes from low level to high level, the first MIS transistor 2 and the MIS of $2
Transistor 4 turns on.

Since the gn of the first MIS transistor 2 is large, most of the current initially flows through this MIS transistor,
The output voltage at output terminal B drops rapidly. However, output end B
When the output voltage reaches the threshold voltage of the threshold element 3, no current flows through the first MrS transistor 2 anymore.

After this, the current gradually flows through the second MIS transistor 4 with a small g-, and therefore the voltage at the output terminal B gradually decreases. This makes it possible to prevent the output voltage from rapidly falling to a predetermined voltage and undershoot.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a configuration diagram of an output circuit according to an embodiment of the present invention, in which 11 is a P-channel MIS transistor, 21, 31
．． 41 is an N-channel MIS transistor.

The source of P-channel MIS transistor 11 is Vcc
Connected to the power supply, an N-channel MIS transistor 31
．． The source of 41 is connected to the Vss power supply. Also P
Channel MIS transistor 11, N-channel MI
The gates of the S transistors 21 and 31 are commonly connected to form an input A, and the drains of the P channel MIS transistor 11 and the N channel MIS transistors 21 and 41 are commonly connected to form an output B. Furthermore, N-channel MIS transistor 21
The gate and drain of an N-channel MIS transistor 3X are connected to the source of the N-channel MIS transistor 3X.

Next, the operation of the output circuit according to the embodiment of the present invention will be explained with reference to FIG. FIG. 3 is a diagram showing the output characteristics when the output B of the output circuit of FIG. 2 changes from a high level to a low level, and the same symbols as in FIG. 7 indicate the same things.

Now consider the operation when the signal input to input A changes from high level to low level. First, when the input signal is at a high level, P-channel MIS transistor ll is turned off, and N
Since the channel MIS transistors 21, 31, and 41 are on, the output B is at a low level.

Next, when the input signal changes to a low level, the N-channel M
IS transistor 21.41 is off.

P-channel MIS transistor 11 is turned on and Vcc
Current flows from the power supply to output B. At this time, the transition time from the low level to the high level of the output B is as follows:
It is determined only by the gn of the IS transistor 11 (of course, it also depends on the magnitude of the load capacitance of the output B). Next, consider the operation when the input signal changes from a low level to a high level. Initially, input A is at a low level, so P
The channel MIS transistor it is y and the N channel MIS transistors 21.41 are OFF, so the output B is at a high level.

Next, when the input signal changes to high level, the P channel M
Since IS transistor 11 is turned off and N-channel MIS transistors 21, 31.41 are turned on, current flows from output B to power supply Vss via these N-channel MIS transistors 21, 31.41. By the way, g of the N-channel MIS transistor 21.31 is larger than g- of the N-channel MIS transistor 41, so the current from the output B to the current mVS2 is almost N
It flows rapidly through the channel MIS transistors 21 and 31. Therefore, the voltage at output B rapidly drops from a high level to a low level.

However, when the voltage of output B drops to the threshold voltage vth of N-channel MIS transistor 31.

Since the gate of the N-channel MIS transistor 31 also becomes this voltage via the N-channel MIS transistor 21, the N-channel MIS transistor 31 is turned off, and the output B is no longer connected to the N-channel MIS transistor 21.
No current flows through 31. Therefore, the current from output B after that is N-channel MIS transistor 4
Only the current flows through 1. By the way, since g of this N-channel MIS transistor 41 is small, the subsequent change of the output B to the low level is gradual, and the undershoot shown in FIG. 7(a) does not occur.

Further, for example, the threshold voltage Vt of the MIS transistor 31
By setting b lower than the low-level standard voltage (O, S V), the time t3 to reach the low-level standard voltage can be set quickly, so there is no possibility of malfunctions caused by delays in external circuit access time. .

Note that in the embodiment, the MIS transistor 31 is used as a threshold element.
However, by using a diode whose node side is connected to the source of the MIS transistor 31 and whose node side is connected to the Vgx power supply.

It is also clear that similar functions can be provided.

FIG. 4 is a block diagram of an output circuit according to another embodiment of the present invention, in which an N-channel MIS transistor 12 is used in place of the P-channel MIS transistor 11 in FIG. In this case, N-channel MIS transistor 12
An N-channel MIS transistor 21.3 is connected to the gate of
A complementary signal A to the signal A input to the gate No. 1 is input.

FIG. 5 is a configuration diagram of an output circuit according to yet another embodiment of the present invention, in which a depletion fiMIs transistor 13 is used in place of the P-channel MIS transistor 11 of FIG. Similar effects can be obtained with these other embodiments.

As described above, according to the output circuit according to the embodiment of the present invention, undershoot can be prevented and the transition time from high level to low level can be made sufficiently fast.

〔Effect of the invention〕

As explained above, according to the present invention, the output level voltage is rapidly lowered to a predetermined low level voltage, and thereafter is lowered relatively slowly to the final power supply voltage level. The period until the output reaches the specified voltage is short, and no undershoot occurs. Therefore, the output undershoot does not trigger the ruff-up of the parasitic thyristor in the 0M03 circuit and destroy the circuit.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an output circuit showing the principle of the present invention. FIG. 2 is a configuration diagram of an output circuit according to an embodiment of the present invention, and FIG. 3 is a waveform diagram showing output characteristics of the output circuit of FIG. 2. FIGS. 4 and 5 are configuration diagrams of an output circuit according to another embodiment of the present invention. FIG. 6 is a configuration diagram of an output circuit according to a conventional example, and FIG. 7 is a waveform diagram showing the output characteristics of the output circuit of FIG. 6. 1... High potential supply means 2... First MIS transistor 3... Threshold element 4... Second MIS transistor 5.12... P channel MIS transistor,
21.31.41・-N+7J MIS transistor

Claims (6)

[Claims] (1) High potential supply means connected between the high potential side power source and the output end, a first MIS transistor whose drain is connected to the output end, and the source of the first MIS transistor and the low potential side a threshold element connected between the power source and a second MIS transistor connected between the output terminal and the low potential power source, the gates of the first and second MIS transistors being connected to the input terminal; and connect g_n of the first MIS transistor to the second
An output circuit characterized in that g_n is larger than that of a MIS transistor. (2) The output circuit according to claim 1, wherein the high potential supply means is a P-channel MIS transistor, and the first and second MIS transistors are N-channel MIS transistors. (3) The high potential supply means is a third N-channel MIS
The first and second MIS transistors are N-channel MIS transistors, and the input signal of the third N-channel MIS transistor is
2. The output circuit according to claim 1, wherein the signal is a complementary signal to an input signal of an N-channel MIS transistor, which is a MIS transistor. (4) Claim 1, wherein the high potential supply means is a depletion type MIS transistor.
Output circuit described in section. (5) The output circuit according to claim 1, wherein the threshold element is an MIS transistor whose drain and gate are connected. (6) The output circuit according to claim 1, wherein the threshold element is a diode.