JP2990998B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a transistor circuit such as an output buffer circuit in a manufacturing process can be easily selected so as to suppress circuit noise or to have high-speed operation characteristics. The present invention relates to an apparatus and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a transistor constituting an output buffer circuit of a semiconductor device, how to select a large current supply capability for an output load or suppression of circuit noise becomes a problem. A conventional output buffer circuit of a semiconductor device will be described with reference to FIGS. FIG. 4 shows a basic circuit configuration of an output buffer circuit in a conventional semiconductor device. In the figure, reference numerals 1 and 2 denote MOS transistors constituting an output transistor, reference numerals 3 and 4 denote signal input terminals, reference numeral 5 denotes a first power supply, reference numeral 6 denotes a second power supply (GND), reference numeral 7 denotes an output terminal, and reference numeral 8 denotes an output. Shows the load capacity.

When the MOS transistor 1 is turned on when there is no charge in the output load capacitor 8 and the MOS transistor 2 is turned off or in the off state, the first power supply 5
The output load capacitance 8 is charged via the MOS transistor 1. Conversely, when the MOS transistor 2 is turned on when the output load capacitance 8 is charged with electric charge and the MOS transistor 1 is turned off or in an off state,
The charge stored in the output load capacitor 8 is discharged to the GND 6 via the MOS transistor 2.

In FIG. 4, when the current supply capability of the output transistors 1 and 2 is set high, the output load capacitance 8 can be charged and discharged at high speed, and the semiconductor device can operate at high speed. However, in this case, a large current change occurs in the power supply 5 or the GND 6 in a short time, so that the power supply voltage or the ground level fluctuates due to wiring inductance or the like, and large noise occurs in the circuit.

Conversely, if the current supply capability of the output transistors 1 and 2 is set low, the circuit noise can be suppressed, but the output load capacitance 8 cannot be charged and discharged rapidly. Speed slows down. That is,
Generally, in a semiconductor device, there is a trade-off relationship between suppression of circuit noise and speeding up of operation.

Conventionally, it is necessary to select an output transistor having a small current supply capability for a product requiring a noise suppression, and an output transistor having a large current supply capability for a product requiring a high speed operation. there were. As described above, since the size of the output buffer transistor is selected depending on the application of the semiconductor device, a mask or the like is different depending on the application, and the selection is complicated, which hinders the improvement of the production efficiency.

Japanese Patent Application Laid-Open No. Hei 3-171649 proposes to solve the above problem. FIG. 5 shows a circuit described in this publication. 17a to 17d are resistors, and 16a to
16f indicates fuses, respectively. For example, the resistor 17a has a smaller resistance value than the resistor 17b, and the resistor 17c has a smaller resistance value than the resistor 17d.

In FIG. 5, first, when the fuses 16a and 16d are connected for the purpose of high-speed operation, charging and discharging are performed via the fuses 16a and 16d. The output load capacity 8 is charged and discharged rapidly without passing through. Next, for example, when only the fuses 16b and 16e are connected and all other fuses are cut, the output load capacitance 8 is charged via the resistor 17a. Further, the output load capacitance 8 is discharged via the resistor 17c.

As a result, the circuit time constant becomes larger as compared with the previous case, and charging and discharging are performed slowly in time, so that circuit noise can be suppressed. As described above, by selecting an output buffer used for an application requiring a large current supply capacity and an output buffer used for an application requiring a small current capacity based on the state of the fuse, a mask or the like can be used. Main processes can be unified.

[0010]

According to the semiconductor device described in the above publication, a step of separately cutting a fuse after the diffusion step is required in order to cope with an application that emphasizes circuit noise suppression. . Since the fuse cutting step is generally performed separately from the diffusion step sequentially performed with the ROM code, a special step is required, and there is a problem that extra steps are required.

In view of the above-mentioned problems of the conventional semiconductor device, the present invention does not require a special step other than each step in a diffusion step which can be sequentially performed by a ROM code which can be set in advance, and has a large current supply capability or An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can be selected so as to correspond to an application of circuit noise suppression.

[0012]

In order to achieve the above object, a semiconductor device according to the present invention comprises a plurality of field-effect transistors in which a common power supply voltage is applied to a gate and a source and a drain are commonly connected. Wherein the parallel current path comprises a field effect transistor in a conductive state and a non-conductive state. Further, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a source / drain region, a step of forming a gate region, and a step of forming a source region and a plurality of field effect transistors.
And the drain region, respectively, and
A common power supply voltage is applied to the gate region of the effect transistor
A wiring forming a parallel current path, which is characterized in that it comprises a step of selectively forming a plurality of field effect transistors in either enhancement or depletion mode.

It is preferable that the plurality of field effect transistors constituting each parallel current path employ transistors having the same dimensional structure.

[0014]

One of a plurality of field effect transistors forming a parallel current path is formed as a depletion type transistor, and the other field effect transistor is selectively formed as a depletion type transistor or an enhancement type transistor. As a result, a transistor circuit having a high current supply capability and a transistor circuit capable of suppressing noise can be selected only by a slight difference in a diffusion step in a semiconductor device application. Any of them can be formed, and the steps performed for the selection are simple.

When a plurality of field effect transistors constituting each parallel current path are formed as transistors having the same dimensional structure, the mask can be unified regardless of the application, and furthermore, the production efficiency can be improved. Can be improved.

[0016]

FIG. 1 shows the configuration of an output buffer circuit of a semiconductor device according to a first embodiment of the present invention. Reference numerals 1 and 2 are switching transistors composed of MOS transistors, 3 and 4 are signal input terminals, 5 is a first power supply, and 6 is a second power supply G
ND and 7 are I / O terminals of the semiconductor device, 8 is an output load capacitance, 9a, 9b, 9d and 9e are depletion type transistors, respectively, and 9c and 9f are enhancement type transistors. In the case of this embodiment, each of the transistors 9a to 9f in the parallel current path is formed as a field effect transistor having an N-channel transistor structure.

The sources and drains of the three transistors 9a, 9b and 9c whose drains are connected to the first power supply 5 are commonly connected to form a first parallel current path 10. The gates of the three transistors 9a, 9b, 9c are connected in common and connected to GND6 forming a second power supply. With this configuration, the depletion type transistors 9a and 9b are always in a conductive state, and the enhancement type transistor 9c is always in a non-conductive state.

Similarly, when the source is connected to GND6,
The sources and drains of the transistors 9d, 9e, and 9f are commonly connected to each other to form a second parallel current path 11. Also, three transistors 9d, 9e, 9
The gates of f are connected in common and connected to GND6. With this configuration, the depletion type transistors 9d and 9e are turned on, and the enhancement type transistor 9d is turned on.
f is in a non-conductive state.

The first parallel current path 10, the first switching transistor 1, the second switching transistor 2, and the second parallel current path 11 are connected to the first power supply 5 and the GND 6
Are connected in series in this order. The first and second switching transistors 1 and 2 are controlled by signals input to their gates, respectively, to form an I / O terminal 7 forming a series connection node of the two switching transistors 1 and 2.
Outputs a high-level or low-level signal according to the gate input, and charges / discharges the output load capacitance 8.

In the above embodiment, each parallel current path 10,
The transistors 9a to 9f provided in the transistor 11 have the same dimensional structure, and are configured as a depletion type transistor or an enhancement type transistor depending on the selection of the channel diffusion concentration. Selection of the type of each transistor is performed on a mask ROM for each application, and in an actual process at the time of manufacturing, it is performed as an addition of a high energy ion implantation process of a channel portion in a transistor formed as a depletion type transistor. Will be Therefore, the number of steps required for selecting the transistor type is very small, and the number of steps is not increased.

FIG. 1 shows an example in which two of the transistors constituting each of the parallel current paths 10 and 11 are depletion type transistors and one is an enhancement type transistor. In this case, since the gates of the transistors are commonly connected and maintained at the ground potential, the depletion type transistor is always on, and the enhancement type transistor is always off. Parallel current path 1
For 0 and 11, the current supply capability is determined by the number of depletion type transistors.

That is, as shown in FIG. 3, when all of the MOS transistors 9a to 9f are depletion type transistors, charging and discharging of the output load capacitance 8 is performed by turning on or off the switching transistors 1 and 2. Is performed at a current value of 3I at high speed, where I is the current value of one depletion type transistor. Next, when the number of the depletion type transistors is sequentially reduced and the number of the enhancement type transistors is increased, the current value at which the output buffer circuit charges and discharges the output load capacitance 8 decreases to 2I and I. The number of depletion type transistors is selected for each application in consideration of the size of the output load capacitance 8 connected to the circuit, the required charge / discharge speed, and the necessity of noise suppression.

In the embodiment shown in FIG. 1, the case where the switching transistor is composed of one MOS transistor 1, 2 has been described. However, each switching transistor 1, 2 is connected to a plurality of MOS transistors connected in parallel. , The same result can be obtained. In this case, for example, there is an advantage that each transistor can be formed to have the same size as each other.

FIG. 2 shows an output buffer circuit of a semiconductor device according to a second embodiment of the present invention. Reference numerals similar to those in FIG. 1 are employed. M between power supply 5 and ground 6
The series current paths of the OS transistors 1 and 2 are connected, and M
Each gate of the OS transistors 1 and 2 has a parallel current path 1
Signal input terminals 3 and 4 are connected via 2 and 13, respectively.
The series connection node of the MOS transistors 1 and 2 charges and discharges the load capacitance 8 via the I / O terminal 7 as in the case of FIG. The gates of the field effect transistors 9a to 9f forming the first and second parallel current paths 12 and 13 are connected in common to each of the parallel current paths 12 and 13 to GND.
6 is connected.

In the embodiment shown in FIG. 2, the current value for driving the gates of the MOS transistors 1 and 2 is changed by selecting a depletion-type or enhancement-type transistor in the parallel current path, so that the output buffer circuit can operate at high speed. Selects circuit noise suppression. FIG. 2 illustrates a case where the number of depletion type transistors and the number of enhancement type transistors in the parallel current paths 12 and 13 are two.

In parallel current paths, MOS transistors 9a to 9a
When f is a depletion type transistor, the input signals 3 and 4 are MOS transistors at a current value of 3I, where I is the current value of one depletion type transistor.
The gate terminals of the transistors 1 and 2 are charged and discharged.
As a result, the MOS transistors 1 and 2 switch at high speed, and the output buffer circuit can operate at high speed.

As the number of depletion type transistors is reduced in the parallel current path, the charge / discharge capability of each input signal 3, 4 to the corresponding gate decreases to 2I, I, and MOS transistors 1 and 2 The time required for switching becomes longer. This is the same as the case shown in FIG. 3, and the circuit noise can be suppressed as the charging and discharging of the output load capacitance 8 becomes slower. The selection of the transistor type in this parallel current path is performed in the same manner as in the first embodiment, and only one step is added to the diffusion step only when forming the depletion type. Increase hardly occurs.

In each of the above embodiments, the case where the number of transistors in the parallel current path is three is illustrated in the drawings, but the number of transistors in the parallel current path can be arbitrarily selected. The selection of supply capability and circuit noise suppression is performed more finely.

Further, in each of the above embodiments, an N-channel transistor structure is shown as each transistor in the parallel current path. However, a P-channel transistor structure may be used instead.

[0030]

As described above, in the semiconductor device according to the present invention, the current supply of the circuit is controlled by selecting whether to form a plurality of field-effect transistors in a parallel current path as a depletion type or an enhancement type. The adoption of the configuration to select the capability enables the supply of products that can meet the requirements of circuit noise suppression or high-speed operation in each application with the same product specifications, and the selection is performed in the same diffusion process. Therefore, there is no particular need for a step of increasing the number of steps, and the effect of improving the production efficiency of the semiconductor device is achieved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an output buffer unit in a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an output buffer unit in a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is an output voltage waveform diagram accompanying selection of a parallel current path in the circuit of the embodiment of FIG. 1;

FIG. 4 is a diagram showing a basic circuit of an output buffer unit in a conventional semiconductor device.

FIG. 5 is a diagram showing an output buffer circuit in a conventional semiconductor device, in which circuit noise can be suppressed or high-speed operation can be selected.

[Explanation of symbols]

 1, 2 MOS transistor 3, 4 signal input terminal 5 power supply 6 GND 7 I / O terminal 8 output load capacitance 9a to 9f MOS transistor of parallel circuit 10 to 13 parallel current path

Claims (5)

(57) [Claims] 1. A power supply voltage is commonly applied to a gate , and a parallel current path including a plurality of field effect transistors having a source and a drain connected to each other in common is provided. A semiconductor device comprising a field-effect transistor in a conductive state. 2. The semiconductor device according to claim 1, wherein the parallel current path includes an enhancement type and a depletion type field effect transistor. 3. A first power supply and a second power supply comprising a first and a second switching transistor, the first and the second parallel current paths being respectively configured as the parallel current path according to claim 1 or 2. The first parallel current path, the first switching transistor, the second switching transistor, and the second parallel current path are connected in this order between the first and second power supplies. A gate or base of each of the switching transistors constitutes a signal input terminal, and a series connection of the first and second switching transistors constitutes a signal output terminal. 4. The parallel current path according to claim 1, further comprising a switching transistor connected to one of a gate and a base, and the other node of the parallel current path forming a signal input terminal. Characteristic semiconductor device. 5. A step of forming a source / drain region in a semiconductor substrate, a step of forming a gate region, and a step of forming a source region and a drain region of a plurality of field effect transistors.
And each of the plurality of field effect transistors
A parallel current path with a common power supply voltage applied to the gate region
A method of manufacturing a semiconductor device, comprising: a wiring step of forming; and a step of selectively forming the plurality of field-effect transistors into either an enhancement type or a depletion type.