JPH03272221A - Chemical compound semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To suppress ringing and to prevent malfunction in the case of using the circuit connecting to an IC by connecting a depletion mode FET made of a chemical compound semiconductor in parallel with an enhancement mode FET, and extracting the external output of the integrated circuit from sources of the FETs connected in parallel. CONSTITUTION:The combined characteristic of FETs 13, 14 in an output buffer circuit 15 is proper combination of both characteristics of the FETs and the fact of the impedance reaching a high impedance when an output goes to an L level is especially suppressed. Concretely, the output impedance at an L level output is 85ohms with an H output level of -0.85V and an L output level of -1.75V, thereby suppressing ringing largely when the output changes from H to L.

Description

[Detailed Description of the Invention] [Summary] Regarding compound semiconductor integrated circuits, a compound semiconductor that suppresses ringing in the output waveform when the output level becomes "L" and prevents malfunction when the IC is connected and used. Objective B is to provide an integrated circuit, which performs a predetermined logical operation using an internal circuit made of a compound semiconductor, and outputs the output of the internal circuit to the outside of the integrated circuit via a buffer circuit including a source follower output transistor. At the same time, in a compound semiconductor integrated circuit using at least an enhancement mode FET made of a compound semiconductor as the output transistor, a depletion mode FET made of the compound semiconductor is connected in parallel to the enhancement mode FET used as the output transistor of the buffer circuit. The integrated circuit is connected to the integrated circuit so that the output from the source side of these FETs connected in parallel can be taken out from the source side of the FETs connected in parallel.

[Industrial application field]

The present invention relates to a compound semiconductor integrated circuit, and specifically relates to a compound semiconductor integrated circuit.
The present invention relates to integrated circuits using compound semiconductors such as aAs.

In recent years, integrated circuits using field effect transistors such as C, aAsFETs and HEMTs have begun to be used as ultrahigh-speed ICs. One of the basic circuits of these ICs that is high speed, low power consumption, has a small number of elements, and is suitable for high integration is DCF L (Direct Coupled FE).
T Logic) is often used.

[Conventional technology]

An example of a conventional DCFL is the one shown in FIG. 5, which is an example of an inverter.

In the figure, 1 is an enhancement mode FET for switching, and 2 is a depletion mode FET for load.
The load depletion mode FET 2 is used as a constant current source by connecting the gate and source. The input terminal (IN) from the previous stage is applied to the gate of the switching enhancement mode FET1, and in the region where the input voltage is lower than the threshold voltage of the switching enhancement mode FET1, the switching enhancement mode FETI is turned off and the output is (OUT)
A load current flows through the stage, and when the next stage is not connected, the power supply voltage VDD is output. However, it is generally connected to the gate of the next stage, and the forward clamp voltage of that gate is V.

Since it is smaller than D, the potential of VF is output. Then,
When the input voltage increases and the switching enhancement mode FETI turns on, the output voltage rapidly decreases to the "L" level.

Moreover, FIG. 6 is an example of a two-man powered NOR gate using DCFL. In the figure, 3.4 is an enhancement mode FET for switching, and 5 is a depletion mode FET for load.
ET, switching enhancement mode F
Input voltages INI and IN2 are applied to ET3.4 from the previous stage, and the level of the output (OUT) changes by taking NOR logic and is transmitted to the subsequent stage.

Here, DCFL operates with a single power supply of about 1 to 2 V, but the ones that are put into practical use as products are compatible with the power supply voltage and input/output level of ECL, which is a high-speed IC using Si bipolar transistors. Generally speaking, a single power source is used. In addition, -2V is EC
This is the terminal voltage of L.

Therefore, in order to make the output compatible with ECL, as shown in FIG. 7, the DCFL IC chip 6 uses a source follower (open source) type switching enhancement mode FET 8 as a buffer circuit to transfer the signal from the internal circuit 7. It is received and transmitted to the next stage.

[Problem to be solved by the invention]

However, in such a CFL compound semiconductor integrated circuit, if a depletion type FET is used as the output source follower FET, the input potential from the internal circuit 7 to the gate of the switching enhancement mode FET 8 will be 2 times the power supply voltage. Even if the voltage drops to
- The ringing when it goes to “Lo” is large, and I'
There was a problem in that it could cause malfunctions when connected and used.

This is mainly due to the impedance ξ mismatch, which will be described in detail later.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a compound semiconductor integrated circuit that can suppress ringing when the output level becomes "L" and prevent malfunctions when used with an I'C connected.

[Means to solve the problem]

In order to achieve the above object, the compound semiconductor integrated circuit according to the present invention performs a predetermined logical operation using an internal circuit made of a compound semiconductor, and sends the output of the internal circuit to the integrated circuit through a buffer circuit including a source follower output transistor. In a compound semiconductor integrated circuit that outputs to the outside and uses at least an enhancement mode FET made of a compound semiconductor as the output transistor,
A depletion mode FET made of a compound semiconductor is connected in parallel to the enhancement mode FET used as an output transistor of the buffer circuit, and the output to the outside of the integrated circuit is taken out from the source side of these parallel connected FETs. It consists of

[Effect]

In the present invention, a depletion mode FET made of a compound semiconductor is connected in parallel to an enhancement mode FET used as an output transistor in a buffer circuit, and outputs to a subsequent stage are taken out from the sources of these FETs connected in parallel.

At this time, since the output impedance of the depletion mode FET is low, ringing when the output level becomes "'L" can be suppressed, and malfunctions can be prevented when the IC is connected and used.

In addition, in an output source follower using only a depletion mode FET, the "L" level rises too much, but by suppressing the gate width of the depletion mode FET within a certain value, the maximum "L" level of the ECL output voltage can be increased. The value (V Ot, -X) can be kept within the standard.

(Explanation of principle) FIG. 1 is a circuit diagram illustrating the present invention in detail.

In this figure, 11 is an IC chip made of, for example, a compound semiconductor and has a DCFL as its basic circuit, and 12 is a D
An internal circuit of a CFL that performs predetermined logical operations, 13
is an enhancement mode FET that receives the signal VING from the internal circuit 12 as a source follower (open source).
, 14 are depletion mode FETs connected in parallel to the enhancement mode FET 13, and these FETs 13 and 14 constitute an output buffer circuit 15. The drain of enhancement mode FET13 is connected to VDIl (GND), and the ECL
The potential (the current is ■.UT
) is now output.

In the above configuration, first, the causes of ringing as described in the prior art will be considered.

When an enhancement mode FET (E-FET) is used as an output source follower, the output impedance is approximately 35Ω when the output level is “H11”, but is much higher than 35Ω when the output level is “L°”. It becomes a high impedance state.In ECL, the output uses a line with a characteristic impedance of 50Ω.
It is common to terminate with a resistor.

However, as in the past, enhancement mode FET
In the output buffer circuit using only
There is almost no problem when setting the level to 'LI+', but due to impedance mismatch, ringing occurs in the output waveform, causing malfunction.

Therefore, in order to prevent ringing when the output is at the "L" level, it is necessary to prevent the output from becoming a high impedance even when the output is at the "L" level, and to make it as close to 50Ω as possible.

Therefore, in the present invention, in order to achieve this requirement, an enhancement mode FET 13 and a depletion mode FET 14 are connected in parallel as an output source follower, and FIG. 2 shows the relationship between the applied voltage and output current of the output source follower. As such, the characteristics resulting from the synthesis of each FET 13 and 14 are a combination of the characteristics of both, and in particular, the impedance is suppressed from reaching a high value when the output is at the "L" level, and ringing is prevented. be able to.

0 〔Example〕 Embodiments of the present invention will be described below based on the drawings.

FIG. 3.4 is a diagram showing an embodiment of a compound semiconductor integrated circuit according to the present invention, and is an example in which the present invention is applied to a gate array. Figure 3 shows an IC chip 20 as a gate array.
, the IC chip 20 is a GaAs MES
The basic circuit is FET DCFL, and includes an internal circuit 12, an output buffer circuit 15 similar to that shown in Fig. 1, an enhancement mode FET 21, and a depletion mode FET.
Inverter 23 consisting of ET22, enhancement mode FET24, 25 and depletion mode F
It is composed of a super buffer circuit 28 made of E726.27.

As each FET of the output buffer circuit 15, for example, a WS gate self-alignment type FET having a gate length of 0.8 μm similar to that of the internal circuit is used.

The threshold voltages of the enhancement mode FET 13 and the depletion mode FET 14 are respectively Vth (
E) = +0.2 V, Vth (D) = -0,6
It is V. In addition, the gate width of each FET 13 and 14 was optimized by symmetry considering the potential of the output "H" level, IIL" level, output impedance, etc., and was determined to be Wg (E) = 200 μm, Wg (D)
-100 μm.

In the above configuration, the output signal of the internal circuit 12 is sent to the output buffer circuit 15 via the inverter 23 and the super buffer circuit 28, and is taken out as the output signal OUT via the source follower to the next stage.

In this case, in this embodiment, each of the FETs 13 and 14 in the output buffer circuit 15 is
The characteristics resulting from the synthesis of both are a suitable combination of the characteristics of both, and in particular, the impedance is suppressed from becoming a high value when the output is at the "L" level.Specifically, the output "
'H' level -0,85V, output 'L' level = -1
, 75V, the output impedance at the output "L" level is 85Ω, and the output is "
Ringing when changing from "H" to "L" is greatly suppressed, making it possible to prevent malfunctions when the IC is connected and used.

[Effects of the Invention] According to the present invention, ringing when the output level becomes "L" can be suppressed, and malfunctions when an IC is connected and used can be prevented.

[Brief explanation of drawings]

1.2 are diagrams explaining the present invention in detail, FIG. 1 is its circuit diagram, FIG. 2 is a diagram showing the characteristics of its output buffer circuit, and FIG. 3.
4 is a diagram showing an embodiment of the compound semiconductor integrated circuit according to the present invention, FIG. 3 is its circuit diagram, FIG. 4 is a waveform diagram of its operation, and 5 to 8 are conventional compound semiconductor integrated circuits. Fig. 5 is a circuit diagram of the inverter, Fig. 6 is a circuit diagram of the NOR gate, Fig. 7 is a circuit diagram of the seven output buffer circuits, and Fig. 8 is the operation of the output buffer circuit. FIG. 11.20...IC chip, 12...Internal circuit, 13...Enhancement mode FET. 14... Depletion mode FET. 15... Output buffer circuit, 2124.25... Enhancement mode F
E.T. 22.26.27... Depletion mode FET. 23... Inverter, 28... Super buffer circuit. 3 4 VDD Circuit diagram of conventional inverter Figure 5 Circuit diagram of conventional output buffer circuit Figure 7

Claims (1)

[Scope of Claims] A predetermined logical operation is performed by an internal circuit made of a compound semiconductor, and the output of the internal circuit is output to the outside of the integrated circuit via a buffer circuit including an output transistor of a source follower, and the output In a compound semiconductor integrated circuit that uses at least an enhancement mode FET made of a compound semiconductor as a transistor, a depletion mode FET made of a compound semiconductor is connected in parallel to the enhancement mode FET used as an output transistor of the buffer circuit, and the depletion mode FET made of a compound semiconductor is connected in parallel. 1. A compound semiconductor integrated circuit characterized in that the compound semiconductor integrated circuit is configured so that an output to the outside of the integrated circuit is taken out from the source side of these connected FETs.