GB2245098A - Logic circuits - Google Patents
Logic circuits Download PDFInfo
- Publication number
- GB2245098A GB2245098A GB9016675A GB9016675A GB2245098A GB 2245098 A GB2245098 A GB 2245098A GB 9016675 A GB9016675 A GB 9016675A GB 9016675 A GB9016675 A GB 9016675A GB 2245098 A GB2245098 A GB 2245098A
- Authority
- GB
- United Kingdom
- Prior art keywords
- logic
- channel mos
- input terminal
- output terminal
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000005669 field effect Effects 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
A logic circuit having two inputs (A, B) and one output (35) comprises a first insulating gate field effect transistor (32) having a gate connected with one (A) of the two input terminals, a drain connected with the other input terminal (B) or the output terminal (35), and a source connected with the output terminal (34) or the other input terminal (B); and a second insulating field effect transistor having a drain connected with said output terminal (35), a gate connected with said one input terminal (A), and a source connected with a voltage source (31) or ground voltage. Saving of space in an integrated circuit is achieved in comparison with prior art four device circuits. <IMAGE>
Description
LOGIC CIRCUITS
The present invention relates to logic circuits, and is concerned particularly although not exclusively with NAND and NOR circuits having two inputs and one output, in a semiconductor device.
Generally, NAND and NOR logic circuits are widely used for predecoders, decoders, etc. However, since the technology for manufacturing semiconductor devices has demanded more and more highly integrated circuits, it is desirable that the layout area allotted for predecoders and decoders be taken into account.
Figures 1A and 1B of the accompanying diagrammatic drawings respectively illustrate examples of conventional
NAND and NOR circuits.
Referring to Figure 1A, the conventional NAND circuit comprises first and second P-channel MOS transistors 3 and 4 connected in parallel between a voltage source terminal and first node 1, and first and second N-channel MOS transistors 5 and 6 connected in series between the first node 1 and ground.
The gates of both the first P-channel MOS transistor 3 and the first N-channel MOS transistor 5 are connected with an input terminal A, while the gates of both the second P-channel MOS transistor 4 and the second N-channel
MOS transistor 6 are connected with another input terminal
B. Further, the first node 1 is connected with an output terminal 10. The operation of this conventional logic circuit is described in positive logic as follows.
If at least one of the logic states applied to the input terminals A and B represents logic 0, i.e. low state, at least one of the first and second P-channel MOS transistors 3,4 is conducting and at least one of the first and second N-channel MOS transistors 5,6 is nonconducting, so that the output terminal 10 takes logic 1, i.e. high state. If both the logic states applied to the input terminals A and B represent high state, the first and second P-channel MOS transistors 3 and 4 are nonconducting, and both the first and second N-channel MOS transistors 5 and 6 are conducting, so that the output terminal 10 takes low state. Hence, the circuit of Figure 1A realises a NAND logic function.
Referring to Figure 1B, the conventional NOR gate comprises first and second P-channel MOS transistors 16, 17 connected in series between the voltage source terminal and first node 15, and first and second N-channel MOS transistors 18, 19 connected in parallel between the first node 15 and ground.
The gates of both the first P-channel MOS transistor 16 and the first N-channel MOS transistor 18 are connected with one input terminal C, while the gates of the second
P-channel MOS transistor 17 and the second N-channel MOS transistor 19 are connected another input terminal D. The first node 15 is connected with an output terminal 23.
The operation of this NOR circuit is described in positive logic as follows.
If at least one of the logic states applied to the input terminals C and D represents logic 1, i.e. high state, at least one of the first and second P-channel MOS transistors 16, 17 is non-conducting, and at least one of the first and second N- channel MOS transistors 18, 19 is conducting, so that the output terminal 23 takes logic 0, i.e., low state. If both the logic states applied to the input terminals C and D represent low state, the first and second P-channel MOS transistors 16, 17 are both conducting, and the first and second N-channel MOS transistors 18, 19 are both non-conducting, so that the output terminal 23 takes high state. Hence, the circuit of Figure 1B realises a NOR logic function.
As described above with reference to Figures 1A and 1B, since the conventional logic circuits having two inputs and one output for serving as NAND and NOR gates each comprise two P-channel MOS transistors and two
N-channel MOS transistors, this limits the reduction of layout area for the design of NAND and NOR logic circuits.
Hence, this impedes high integration of a semiconductor chip.
Preferred embodiments of the present invention aim to provide logic circuits having two inputs and one output that may considerably reduce the layout area required for the design of the logic circuits.
According to one aspect of the present invention, there is provided a logic circuit having two input terminals and one output terminal and comprising:
a first insulating gate field effect transistor having a gate connected with one of the two input terminals, and a source and drain connected between the other input terminal and the output terminal; and
a second insulating field effect transistor having a gate connected with said one input terminal, and a source and drain connected between said output terminal and a voltage source or ground.
Said first insulating gate field effect transistor may be N-type and said second insulating gate field effect transistor P-type.
Alternatively, said first insulating gate field effect transistor may be P-type and said second insulating gate field effect transistor N-type.
Said source of said first transistor may be connected to said other input terminal.
Said source of said second transistor may be connected to said voltage source or ground.
The invention extends to a semiconductor device incorporating such a logic circuit.
For a better understanding of the invention and to show how the same may be carried into effect, reference will now be made, by way of example, to Figures 2 and 3 of the accompanying diagrammatic drawings, in which:
Figure 2A illustrates an example of a NAND logic circuit having two inputs and one output;
Figure 2B illustrates an example of a NOR logic circuit having two inputs and one output;
Figure 3A shows the truth table for the NAND logic circuit of Figure 2A; and
Figure 3B shows the truth table for the NOR logic circuit of Figure 2B.
Figures 2A and 2B respectively illustrate NAND and
NOR logic circuits each having two inputs and one output and embodying the present invention.
The NAND logic circuit of Fig.2A comprises an
N-channel MOS transistor 32 having a gate connected with one input terminal A and a drain and source connected between another input terminal B (which receives the inverse of a logic input B) and an output terminal 35, and a P-channel MOS transistor 33 having a gate connected with the one input terminal A and a source and a drain connected between a source voltage 31 and the output terminal 35.
The NOR logic circuit of Figure 2B comprises a
P-channel MOS transistor 38 having a gate connected with one input terminal C and a source and drain connected between another input terminal D (which receives the inverse of a logic input D) and an output terminal 40, and an N-channel MOS transistor 39 having a gate connected with the one input terminal C and a drain and source connected between the output terminal 40 and ground.
- Referring to Figures 2A, 2B, 3A, and 3B, the operation of the logic circuits will be more specifically described.
Firstly, the circuit of Figure 2A will be described in positive logic with reference to the truth table of
Figure 3A.
If the one input terminal A is applied with logic 0, the N- channel MOS transistor 32 is non-conducting wie the P-channel MOS transistor 33 is conducting, so that the output becomes logic 1 regardless of the state of the other input terminal B that is inverted.
On the other hand, if the one input terminal A is applied with logic 1, the P-channel MOS transistor 33 is non-conducting and the N-channel MOS transistor 32 is conducting. In this case, if the other input terminal B takes logic state 1, the output terminal 35 takes logic state 1. Alternatively, if the other input terminal B is applied with logic state 0, the output terminal takes logic state 0.
However, as input terminal B receives the inverse of original logic input signal B, the circuit of Figure 2A serves as a NAND logic circuit on inputs A and B, whose output terminal 35 takes logic state 0 only when both the input logic signals A and B are at logic state 1.
Next, the circuit of Figure 2B is described in positive logic with reference to Figure 3B.
If the one input terminal C is applied with logic state 1, the P-channel MOS transistor 38 is non-conducting and the N- channel MOS transistor 39 is conducting, so that the output terminal takes logic state 0 regardless of the state of the other input terminal D that receives the inverse of logic signal D.
On the other hand, if the one input terminal C is applied with logic state 0, the N-channel MOS transistor 39 is non-conducting and the P-channel MOS transistor 38 is conducting. In this case, if the other input terminal D takes logic state 1, since the P-channel MOS transistor 38 is conducting, the output terminal 40 also takes logic state 1. Similarly, if the other input terminal D is applied with logic state 0, since the P-channel MOS transistor 38 is conducting, the output terminal 40 takes logic state 1.
Since input terminal D receives the inverse of original logic input signal D, the circuit of Figure 2B serves as a NOR logic circuit on inputs C and D, whose output terminal 40 takes logic state 1 only when both the input logic signals C and D have logic state 0.
Thus, the illustrated embodiments provide NAND and
NOR logic circuits having two inputs and one output that employ only two insulating gate field effect transistors, which may considerably reduce the layout area for design of the logic circuit, thereby achieving a highly integrated semiconductor chip.
In the embodiments of Figures 2A and 2B, the inputs
B and D may be derived from the original inputs B and D by inverters. However, it is common for complementary signals B, B and D, D, etc., to be present anyway in semiconductor devices, in which case a NAND or NOR operation may be performed on signals A, B or C, D respectively simply by inputting the already available signals A, B or C, D respectively to the illustrated circuits.
The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.
All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.
Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.
Claims (7)
1. A logic circuit having two input terminals and one output terminal and comprising:
a first insulating gate field effect transistor having a gate connected with one of the two input terminals, and a source and drain connected between the other input terminal and the output terminal; and
a second insulating field effect transistor having a gate connected with said one input terminal, and a source and drain connected between said output terminal and a voltage source or ground.
2. A logic circuit as claimed in Claim 1, wherein said first insulating gate field effect transistor is N-type and said second insulating gate field effect transistor is
P-type.
3. A logic circuit as claimed in Claim 1, wherein said first insulating gate field effect transistor is P-type and said second insulating gate field effect transistor is
N-type.
4. A logic circuit as claimed in Claim 1, 2 or 3, wherein said source of said first transistor is connected to said other input terminal.
5. A logic circuit according to any of Claims 1 to 4, wherein said source of said second transistor is connected to said voltage source or ground.
6. A logic circuit substantially as hereinbefore described with reference to Figures 2A and 3A, or with reference to Figures 2B and 3B of the accompanying diagrammatic drawings.
7. A semiconductor device incorporating a logic circuit according to any of the preceding claims.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR900008698 | 1990-06-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9016675D0 GB9016675D0 (en) | 1990-09-12 |
| GB2245098A true GB2245098A (en) | 1991-12-18 |
Family
ID=19300068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9016675A Withdrawn GB2245098A (en) | 1990-06-13 | 1990-07-30 | Logic circuits |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH0446416A (en) |
| FR (1) | FR2663479A1 (en) |
| GB (1) | GB2245098A (en) |
| IT (1) | IT1241518B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998042075A1 (en) * | 1997-03-19 | 1998-09-24 | Honeywell Inc. | Free inverter circuit |
| NL1020289C2 (en) * | 2002-04-02 | 2003-10-03 | Jan Hendrik Van De Pol | Device for adding or subtracting. |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4562515B2 (en) * | 2004-12-22 | 2010-10-13 | ルネサスエレクトロニクス株式会社 | Logic circuit and word driver circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0249789A1 (en) * | 1986-06-10 | 1987-12-23 | Siemens Aktiengesellschaft | Non-equivalence and equivalence gate circuits |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3986042A (en) * | 1974-12-23 | 1976-10-12 | Rockwell International Corporation | CMOS Boolean logic mechanization |
| JPS5471973A (en) * | 1977-11-18 | 1979-06-08 | Nec Corp | Logical operation circuit |
| JPS5662427A (en) * | 1979-10-26 | 1981-05-28 | Pioneer Electronic Corp | Logic circuit |
| JPS5834629A (en) * | 1981-08-24 | 1983-03-01 | Toshiba Corp | Logic integrated circuit |
| US4710649A (en) * | 1986-04-11 | 1987-12-01 | Raytheon Company | Transmission-gate structured logic circuits |
| JPS6418314A (en) * | 1987-07-13 | 1989-01-23 | Mitsubishi Electric Corp | Logic circuit |
| JPS6481321A (en) * | 1987-09-24 | 1989-03-27 | Hitachi Ltd | Plasma treatment device |
| JPH0671203B2 (en) * | 1987-12-23 | 1994-09-07 | 株式会社東芝 | Logic circuit |
| JPH022713A (en) * | 1988-06-16 | 1990-01-08 | Kawasaki Steel Corp | Semiconductor integrated circuit |
| JPH02101819A (en) * | 1988-10-08 | 1990-04-13 | Sharp Corp | Digital comparator |
-
1990
- 1990-07-18 FR FR9009151A patent/FR2663479A1/en active Pending
- 1990-07-26 JP JP2196395A patent/JPH0446416A/en active Pending
- 1990-07-30 GB GB9016675A patent/GB2245098A/en not_active Withdrawn
- 1990-07-31 IT IT48183A patent/IT1241518B/en active IP Right Grant
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0249789A1 (en) * | 1986-06-10 | 1987-12-23 | Siemens Aktiengesellschaft | Non-equivalence and equivalence gate circuits |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998042075A1 (en) * | 1997-03-19 | 1998-09-24 | Honeywell Inc. | Free inverter circuit |
| US5982198A (en) * | 1997-03-19 | 1999-11-09 | Honeywell Inc. | Free inverter circuit |
| NL1020289C2 (en) * | 2002-04-02 | 2003-10-03 | Jan Hendrik Van De Pol | Device for adding or subtracting. |
| EP1351393A1 (en) * | 2002-04-02 | 2003-10-08 | Jan Hendrik Van De Pol | Device and method for adding and/or subtracting |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0446416A (en) | 1992-02-17 |
| GB9016675D0 (en) | 1990-09-12 |
| FR2663479A1 (en) | 1991-12-20 |
| IT9048183A0 (en) | 1990-07-31 |
| IT9048183A1 (en) | 1992-01-31 |
| IT1241518B (en) | 1994-01-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |