JPS5471973A - Logical operation circuit - Google Patents
Logical operation circuitInfo
- Publication number
- JPS5471973A JPS5471973A JP13937677A JP13937677A JPS5471973A JP S5471973 A JPS5471973 A JP S5471973A JP 13937677 A JP13937677 A JP 13937677A JP 13937677 A JP13937677 A JP 13937677A JP S5471973 A JPS5471973 A JP S5471973A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- appears
- terminals
- constitution
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
Abstract
PURPOSE:To make it possible to constitute even a complicated circuit with a small of elements to facilitate making the circuit into a LSI by constituting a logical circuit with IGEFTS which have channel types different from each other. CONSTITUTION:The drain electrode of N channel-type FET element Q1 is connected to the first input terminal A, and the gate electrode and the source electrode are connected to the second input terminal B and output terminal t0 respectively. Next, the drain electrode of P channel-type FET element Q2 is connected to power source terminal +VD, and the gate electrode is connected to the second input terminal B, and further, the source electrode is connected to the source electrode of element Q1 and output terminal tO. Thus, when teminals A and B are ''0''-level, level ''1'' appears at terminal tO; and when terminchs A and B are ''0'' and ''1'' respectively, ''0'' appears at terminal tO. Further, when terminals A and B are ''1'' and ''0'' respectively, ''1'' appears at terminal tO; and when terminals A and B are ''1'', ''1'' appears at terminals tO. As a result, this constitution gives the same function as a normal element constitution.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13937677A JPS5471973A (en) | 1977-11-18 | 1977-11-18 | Logical operation circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13937677A JPS5471973A (en) | 1977-11-18 | 1977-11-18 | Logical operation circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5471973A true JPS5471973A (en) | 1979-06-08 |
Family
ID=15243871
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13937677A Pending JPS5471973A (en) | 1977-11-18 | 1977-11-18 | Logical operation circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5471973A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61142821A (en) * | 1984-12-17 | 1986-06-30 | Nippon Telegr & Teleph Corp <Ntt> | Cmos logical circuit |
JPS62124A (en) * | 1985-06-26 | 1987-01-06 | Mitsubishi Electric Corp | Pulse width modulation circuit |
JPS63149915A (en) * | 1986-12-12 | 1988-06-22 | Sharp Corp | Cmos logic gate circuit |
JPS6418314A (en) * | 1987-07-13 | 1989-01-23 | Mitsubishi Electric Corp | Logic circuit |
JPH02309816A (en) * | 1989-05-25 | 1990-12-25 | Nec Corp | Logic computing element |
JPH0446416A (en) * | 1990-06-13 | 1992-02-17 | Samsung Electron Co Ltd | Logic circuit having two input and one output |
JP2006180197A (en) * | 2004-12-22 | 2006-07-06 | Nec Electronics Corp | Logic circuit and word driver circuit |
-
1977
- 1977-11-18 JP JP13937677A patent/JPS5471973A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61142821A (en) * | 1984-12-17 | 1986-06-30 | Nippon Telegr & Teleph Corp <Ntt> | Cmos logical circuit |
JPS62124A (en) * | 1985-06-26 | 1987-01-06 | Mitsubishi Electric Corp | Pulse width modulation circuit |
JPH0466136B2 (en) * | 1985-06-26 | 1992-10-22 | Mitsubishi Electric Corp | |
JPS63149915A (en) * | 1986-12-12 | 1988-06-22 | Sharp Corp | Cmos logic gate circuit |
JPS6418314A (en) * | 1987-07-13 | 1989-01-23 | Mitsubishi Electric Corp | Logic circuit |
JPH02309816A (en) * | 1989-05-25 | 1990-12-25 | Nec Corp | Logic computing element |
JPH0446416A (en) * | 1990-06-13 | 1992-02-17 | Samsung Electron Co Ltd | Logic circuit having two input and one output |
JP2006180197A (en) * | 2004-12-22 | 2006-07-06 | Nec Electronics Corp | Logic circuit and word driver circuit |
JP4562515B2 (en) * | 2004-12-22 | 2010-10-13 | ルネサスエレクトロニクス株式会社 | Logic circuit and word driver circuit |
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