JPH02309816A - Logic computing element - Google Patents

Abstract

PURPOSE:To attain high speed operation by making a delay time of a logical computing element equal to a signal transmission time equivalent to that of a share of MOS transistor(TR). CONSTITUTION:The element consists of an N-channel 1st MOS TR T1 switching between a 1st negative input I1 and a positive output Q, and using a 2nd positive input I2 as its gate input, a P-channel 2nd MOS TR T2 switching between a 1st power supply and the positive output Q, and using a 2nd positive input I2 as its gate input, a P-channel 3rd MOS TR T3 switching between a 2nd power supply and an output Q, and using a 2nd negative input I2 as its gate input and an N-channel 4th MOS TR T4 switching between a 2nd power supply and an output Q and using a 2nd input I2 as its gate input. Thus, positive and negative logical arithmetic operations are implemented simultaneously to output both outputs Q, and Q in the complementary relation simultaneously. Thus, it is not required to connect an inverter in cascade to an output to obtain an inverted output to decrease the delay time. Moreover, since both outputs Q, and Q in the complementary relation are obtained simultaneously, the change in both the outputs is detected at a high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a logic operation unit which is a basic component of a digital information processing device, and in particular to a logic operation unit with differential output using a transfer gate using a MOS (MOS) transistor. Regarding.

[Conventional technology]

Digital L generally represented by microprocessors, etc.
SI is NAND gate, NOR gate.

It is constructed by combining a large number of logical operation units such as inverters.

A two-man power NOR gate or NOR gate with a typical CMOS structure consists of two P-type MO transistors and two N-type M transistors.
OS) consists of transistors. Also, the inverter is P
It consists of one each of type and N type MOS transistors. A
ND gates and OR gates are realized by cascading inverters to each output of the NAND gate and NOR gate9 [Problem to be solved by the invention] The conventional CMOS structure NAND gate described above
In logical operation units such as AND gates and OR gates, input signals pass through two MOS transistors to reach the output, so the delay time is long. Also, AND gates and OR
When implementing a gate or requiring an inverted output, inverters must be connected in cascade. In other words, conventional logical arithmetic units have the disadvantage of being slow.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned conventional drawbacks and provide a high-speed logical arithmetic unit.

[Means to solve the problem]

The configuration of the logic operator of the present invention is that an N-type first MO opens and closes between a first negative input and a positive output, and uses a second positive input as a gate input.
an S transistor, opening and closing between the first power supply and the positive output;
P-type second M03) with the second positive input as the gate input
a transistor, a third P-type MOS transistor which opens and closes between the first positive input and the negative output and whose gate input is the second negative input; and a third P-type MOS transistor which opens and closes between the second power supply and the negative output and connects the second negative input. A fourth M08) N-type transistor is used as a gate input.

[Effect]

By adopting such a configuration, two input signals A,
By B, Q = person - + "Togu - = Performs the positive logic and negative logic operations of A -C at the same time, and both outputs Q in a complementary relationship,
Low output can be output at the same time. Therefore, there is no need to connect an inverter in cascade to the output to obtain an inverted output.
Further, the delay time can be reduced to one MO81 to one transistor. Further, since the forces Q and ζ- of both rivers having a complementary relationship can be obtained at the same time, changes in the output can be detected at high speed by detecting the difference between the forces of the two rivers. That is, high-speed operation is possible.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, input signal I1. Us, I 2. 'T'2 are a first positive input signal, a first negative input signal, a second positive input signal, and a second negative input signal, respectively. Also, the first negative input signal λ-
is an inverted signal of the first positive input signal A, and the second negative input signal W is an inverted signal of the second positive input signal B. T, and T4 are N-type Mo3) transistors, and T2 and T3 are P-type MoS.
′ indicates a transistor.

First positive input signal 11. 1st negative input signal rl, 2nd positive input signal 2. 4 as shown in FIG. 2 as the second negative input signal r2.
When a logical signal is given as follows, the MOS transistor T, ~
T4 operates as shown in the figure. Here, the symbol “X
The symbol "0" indicates an open state and the symbol "0" indicates a conductive state, respectively. As a result, the positive output signal Q is the first positive input signal 1. °“0” only when both of and the second positive input signal ■2 are “1”
'', and the negative output signal is the opposite. In other words, the logical operation of Q-[-heat τ-'Q-=I + ·Work2 is possible.

Note that when the first positive input signal I is "0'" and the second positive input signal 2 is "1°", the amplitude of "1" of the positive output signal Q decreases by the threshold voltage, and the negative The amplitude of output signal Q-'O°' increases by the threshold voltage. Generally, the threshold voltage is about 0.8 volts, which poses no practical problem, but a P-type MOS transistor is connected in parallel to the N-type MOS transistor T1, and an N-type Mo3 transistor is connected in parallel to the P-type Mo3)-transistor T3. ) By connecting a transistor, the amplitude of the logical value “1” is reduced and the logical value is
o'' amplitude increase can be completely eliminated.

By cascading these logical operation units, complex logical operations can be performed using a large number of input signals.

FIG. 3 is a block diagram showing another embodiment of the present invention. In the figure, the logical arithmetic units according to the present invention shown in FIG. 1 are connected in cascade. In FIG. 3(A), the first logical operator 10
The positive and negative outputs Q and -Q are connected to the first negative input 1 and the first positive input 11 of the second logical operation unit, respectively. The first logical operator 1o performs the calculation Q=A-Btogu=A-B, and the second logical operator 20 calculates ○UT=A-B, C and σ1T=A-B-C. Do this.

In FIG. 3(B), the connection between the output of the first logical operator 1o and the input of the second logical operator 20 is reversed from that in FIG. 3(A). As a result, the following calculation is performed: 0UT=A −B+σ 0UT=λ·BC. In this way, the logical operation to be realized can be selected by connecting the first and second stage logical arithmetic units.

Further, the first logical operation unit 10 and the first positive input 1. and the signal input to the first negative input car 1, the signal input to the second positive input I2 and the second negative input r2, and the first positive input 1 and the first negative input car of the second logical operator 20. By selecting the signal input to 1, the signal input to the second positive input 2 and the second negative input r2,
16 types of logical operations can be realized.

The delay time of each logical arithmetic unit is the signal passing time of one MOS)-Rangemetal, which is half the time of two conventional logic units.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to provide a logic arithmetic unit faster than the conventional one. In other words, in a two-man NAND gate that represents a conventional logical operation unit, there are two
In the past, the signal had to pass through several MOS transistors, but in the present invention, this is reduced by half to one MOS transistor. Furthermore, since both positive and negative forces are generated simultaneously, there is no need for an inverter, which is required in conventional logical arithmetic units, in order to obtain an inverted output. Furthermore, by detecting a differential between positive and negative outputs, changes in output can be detected at high speed. That is, the present invention is capable of high-speed operation.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is an explanatory diagram of its operation, and FIG. 3 is a configuration diagram of another embodiment.

1,...first positive input signal, I1...first negative input signal, I2...second positive input signal, I-2...second negative input signal, Q...positive Output signal, T... negative output signal,
T1. I4...N type MOS transistor, T2
, T3...P-type MOS) - transistor, 10.
...first logical operator, 20...second logical operator.

Claims (1)

[Claims] a first N-type MOS transistor that opens and closes between a first negative input and a positive output, and has a second positive input as a gate input; and a first N-type MOS transistor that opens and closes between a first power supply and the positive output, and has a second positive input as a gate input. a P-type second MOS transistor that opens and closes between the first positive input and the negative output, a third P-type MOS transistor that uses the second negative input as a gate input, and opens and closes between the second power supply and the negative output; an N-type fourth transistor whose gate input is the second negative input;
A logic operation unit characterized by comprising a MOS transistor.